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[209.85.167.169]) by smtp.gmail.com with ESMTPSA id h11-20020a9d6f8b000000b005b230ab0461sm7657435otq.64.2022.03.28.13.46.25 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Mar 2022 13:46:25 -0700 (PDT) Received: by mail-oi1-f169.google.com with SMTP id q129so16980030oif.4 for ; Mon, 28 Mar 2022 13:46:25 -0700 (PDT) X-Received: by 2002:a05:6808:2204:b0:2da:30c1:dd4c with SMTP id bd4-20020a056808220400b002da30c1dd4cmr529272oib.195.1648500384990; Mon, 28 Mar 2022 13:46:24 -0700 (PDT) MIME-Version: 1.0 References: <7d633e34-657c-539e-7df9-146c4dd649f2@suse.com> <808fd1e0-8993-66d9-e5aa-129e7916790a@suse.com> In-Reply-To: <808fd1e0-8993-66d9-e5aa-129e7916790a@suse.com> From: Andrew Waterman Date: Mon, 28 Mar 2022 13:46:13 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Ping: [PATCH v2] RISC-V: correct FCVT.Q.L[U] To: Jan Beulich Cc: Palmer Dabbelt , Nelson Chu , Jim Wilson , Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Mar 2022 20:46:30 -0000 Approved. The old mapping is harmless, but the new mapping honors the recommendation in the ISA spec for instructions that don't round. I'll also add the corresponding note in the ISA spec for these instructions. On Mon, Mar 28, 2022 at 1:52 AM Jan Beulich wrote: > > On 04.03.2022 13:41, Jan Beulich via Binutils wrote: > > While the spec isn't explicit about this, it pointing out the similarity > > with the D extension ought to extend to the ignoring of a meaningless > > rounding mode: "Note FCVT.D.W[U] always produces an exact result and is > > unaffected by rounding mode." Hence the chosen encodings also ought to > > match. > > > > Note that to avoid breaking existing code the forms with a 3rd operand > > are not removed, which means there continues to be a difference to > > FCVT.D.W[U]. > > I'd prefer to not commit such without arch maintainer approval; I guess > I'll give it another week and the will assume the absence of comments to > mean consent. > > Thanks, Jan > > > --- > > Oddly enough there's looks to be no testing of the Q (or D/F) extension > > beyond what was recently added for Zqinx (Zdinx/Zfinx). > > --- > > v2: Re-base. > > > > --- a/gas/testsuite/gas/riscv/zqinx.d > > +++ b/gas/testsuite/gas/riscv/zqinx.d > > @@ -28,8 +28,8 @@ Disassembly of section .text: > > [ ]+[0-9a-f]+:[ ]+46158553[ ]+fcvt.q.d[ ]+a0,a1 > > [ ]+[0-9a-f]+:[ ]+d6058553[ ]+fcvt.q.w[ ]+a0,a1 > > [ ]+[0-9a-f]+:[ ]+d6158553[ ]+fcvt.q.wu[ ]+a0,a1 > > -[ ]+[0-9a-f]+:[ ]+d625f553[ ]+fcvt.q.l[ ]+a0,a1 > > -[ ]+[0-9a-f]+:[ ]+d635f553[ ]+fcvt.q.lu[ ]+a0,a1 > > +[ ]+[0-9a-f]+:[ ]+d6258553[ ]+fcvt.q.l[ ]+a0,a1 > > +[ ]+[0-9a-f]+:[ ]+d6358553[ ]+fcvt.q.lu[ ]+a0,a1 > > [ ]+[0-9a-f]+:[ ]+26c58553[ ]+fsgnj.q[ ]+a0,a1,a2 > > [ ]+[0-9a-f]+:[ ]+26c59553[ ]+fsgnjn.q[ ]+a0,a1,a2 > > [ ]+[0-9a-f]+:[ ]+26c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -763,9 +763,9 @@ const struct riscv_opcode riscv_opcodes[ > > {"fcvt.l.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, > > {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, > > {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, > > -{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > > +{"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, > > -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, > > +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, > > > > /* Compressed instructions. */ > > >