Re: RISC-V: observations / questions

[Andrew Waterman <andrew@sifive.com>]

On Fri, Feb 25, 2022 at 6:59 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> Hello,
>
> besides the two relatively simple patches that I have sent earlier
> today, I do have a few more questions:
>
> 1) Many insn encodings using x0 as the destination are marked as hint
> encodings. Wouldn't things like "add x0, x1, x2" therefore better be
> at least warned about?

Encodings like that should not issue warnings, for a few reasons:
- It's always functionally correct to include stray HINTs in programs,
since by definition they don't affect architectural state.
- This style provides a clean way to encode hints before they've been
added to binutils.
- This style facilitates writing test programs.

>
> 2) Insns like "beq x0, x0, ." (perhaps not very useful outside of
> assembler / disassembler test suites) result in odd ".L0 " labels in
> the object's symbol table. My best guess so far was that this may be
> a result of "#define tc_fix_adjustable(fixp) 0". As these labels are
> somewhat confusing - would there be a way to suppress their emission?
>
> 3) When the assembler can determine a branch's destination, e.g. in
> "beq x0, x0, .+1", wouldn't it be useful to warn about the non-even
> destination address? And with the C extension disabled even about
> any one not evenly divisible by 4?

(Only in response to the second question:)  It's legal to include
branches to addresses that aren't divisible by 4 (but are divisible by
2) when C is disabled; the trap only occurs if the branch is taken.
Prohibiting these branches' inclusion would make it harder to write
test programs.

>
> 4) A number of CSRs are valid in RV32 mode only. Shouldn't their use
> be diagnosed when assembling 64-bit code? (I thought I had seen a
> patch to this effect, but not overly old gas still happily accepts
> them.)
>
> 5) While possibly not too interesting for RV32, in RV64 auipc and
> lui have immediate operands which are sign-extended. Yet gas chokes
> on any of
>
>         auipc   x31, -0x100
>         lui     x31, -0x100
>         c.lui   x31, -0x20
>
> Shouldn't signed operands be permitted (if not required) there, and
> then ideally permitted (but not required) also on RV32?

IMO, changing the set of immediates that these instructions can accept
risks causing more confusion than it resolves.  Part of the reason is
they already accept large unsigned immediates (e.g., lui t0, 0xfffff),
which is an odd holdover from the MIPS assembler, but one we can't
change for backwards-compatibility reasons.  IMO, it seems a bit funky
to accept both [-0x80000, -1] and [0x80000, 0xfffff] to refer to the
same set of numbers.

>
> Thanks for any helpful insight,
> Jan
>