From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by sourceware.org (Postfix) with ESMTPS id 593223858D28 for ; Mon, 10 Jan 2022 23:56:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 593223858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-oi1-x230.google.com with SMTP id t204so20801644oie.7 for ; Mon, 10 Jan 2022 15:56:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=o67XSoDV0ZxMl3f8vUp9zbSM5WfNRDyS6h8GaICGJYY=; b=O1qGm7K7PWtbYw/6WJQb6pa8QnZlA4iXSJt/JFyV1DzRT0CJPfGD9YxKKM4Mv6BQU6 IyxslbfvbyqUZaMVVG55hvyxTr2uEdmN3Vzjl6pnP+yuzy8WlrY41Q/ECCnuDrNKAt+V s3z/6hhZg72YkBQaGtxtQWrpzvT8kZ30VChDixi5kpdr77KufOeRGs24L8a8g3igzLQc b03V1iBn8RANfTGRtPC/W8XYm+YMc6R6wBfYoZbQB/1sg7ULKnFat3/9hkpEIzpeox75 w8SRO35VKofWLpQuKP0K0Ic0J7SPrwp6eJbEltETEkisE8PH+XUil+ljE0NKCTdyJHMT 0UnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=o67XSoDV0ZxMl3f8vUp9zbSM5WfNRDyS6h8GaICGJYY=; b=PVJFDPjG28oPvjJ/KvEX4UZXOiE3FUMz9Ww4mapZo5xJJEi+JDwXOyymmTEKmsW2hU 8TrhUJTwNFgoxgOGddkOO2VOmx3+Tt0Mkw3/uOqMQdo8ny0oJ9f8jrkyZ5HR00nUnXAb xX64O9O+46ZgVE2uM8HCnWwxk5rw2DRXloAyF0h17aDmvucSPNl8H6OrA+Ny9cZJEgxv fZ8N6OmbTwITXDYX9bY70vcE34e7IC+9zwmwI1RHsH2PvXNKByv0ggdzAC+l5nuaSLpt Y+O0h0g7tntpbEYGCMPNfJNoHQo9UpPeY4oD/ZXSHi4T2sH/ZIAbPs0a1mSI8cNV76oK 9x3w== X-Gm-Message-State: AOAM531wFdn97vSRJVlR1gc+v9hk4S628MWTCyaMfmiF5jvJ4nJzzBze ZIvNQvqUkE9cFK6WmuSIR6vJLUlDop9eWfj0 X-Google-Smtp-Source: ABdhPJxXKpu/p8YxFL84YmFKPqGl0cW6iKJ1qWFC0ZEc/e8M0rLNEJNTazW+iaXAMjmtUwfbPVSuMw== X-Received: by 2002:aca:1811:: with SMTP id h17mr113665oih.178.1641858980600; Mon, 10 Jan 2022 15:56:20 -0800 (PST) Received: from mail-oi1-f173.google.com (mail-oi1-f173.google.com. [209.85.167.173]) by smtp.gmail.com with ESMTPSA id l15sm1760695otp.7.2022.01.10.15.56.20 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Jan 2022 15:56:20 -0800 (PST) Received: by mail-oi1-f173.google.com with SMTP id r62so14112169oie.6 for ; Mon, 10 Jan 2022 15:56:20 -0800 (PST) X-Received: by 2002:aca:1a0a:: with SMTP id a10mr131316oia.90.1641858979934; Mon, 10 Jan 2022 15:56:19 -0800 (PST) MIME-Version: 1.0 References: <3ab20eb4c065dc1e5a976dccc593a2c9a6ab853f.1641802855.git.research_trasio@irq.a4lg.com> In-Reply-To: <3ab20eb4c065dc1e5a976dccc593a2c9a6ab853f.1641802855.git.research_trasio@irq.a4lg.com> From: Andrew Waterman Date: Mon, 10 Jan 2022 15:56:09 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/1] RISC-V: Fix mask for some fcvt instructions To: Tsukasa OI Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Jan 2022 23:56:22 -0000 LGTM. Thanks. On Mon, Jan 10, 2022 at 12:23 AM Tsukasa OI via Binutils wrote: > > This commit fixes incorrect uses of mask values in 'fcvt' instruction > family. > > opcodes/ChangeLog: > > * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values > in 'fcvt' instruction family. > --- > opcodes/riscv-opc.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 2da0f7cf0a4..00ee21d783f 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -630,7 +630,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, > {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, > {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, > -{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, > +{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, > {"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, > {"fclass.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, > {"feq.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, > @@ -644,7 +644,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, > {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, > {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, > -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, > +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, > {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, > > /* Double-precision floating-point instruction subset. */ > @@ -705,7 +705,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, > {"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, > {"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, > -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, > +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, > {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, > > /* Quad-precision floating-point instruction subset. */ > @@ -765,7 +765,7 @@ const struct riscv_opcode riscv_opcodes[] = > {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, > -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, > {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, > > /* Compressed instructions. */ > -- > 2.32.0 >