From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x233.google.com (mail-oi1-x233.google.com [IPv6:2607:f8b0:4864:20::233]) by sourceware.org (Postfix) with ESMTPS id 5FD51385840B for ; Tue, 30 Nov 2021 07:12:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5FD51385840B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-oi1-x233.google.com with SMTP id r26so39493257oiw.5 for ; Mon, 29 Nov 2021 23:12:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=S/d2rfb4fjCEWR+fTR/aMdP4wShkdPeLA+T/n68E2E0=; b=eQFN21O5wXH8104ao9e4s9tNFFtd33Y9VZCxVxmu4Dd+JiCnriJOVbY3VNDb/R+MEH qpc03GJw5h2EQlF4ZngC9hhKatPURxB0sH+08EOICYQZR/1RUMtdPuFaIUADdrZPcBhv ZfE4qQWR227VVDayKPiq/TNkycsviq6moTbO+zYD8rg29TckBInHeg7TyK2Wskq+bvjE GhaSVhxVksM3R96GFmLleb5uXd8reL1GNrvZv2gBa3g3iq9w2WEZoxrqqzTCHlVYHytY iXvn9zFAFmCkmTaOz3lrHKgb2GGezc0mlR/4rlxUsLMKDkDn4frQLVCUkiG6LuvBx6oP 12JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=S/d2rfb4fjCEWR+fTR/aMdP4wShkdPeLA+T/n68E2E0=; b=E4nx7n/OolW+jQnvqT0ZQ/xnmsBwdmpHaYOS0wqM9vYdSzEjklhI5WU6H+xvd+0jjd ZuXWALTsGQgT+6Lov7MSe9zWtgeqvMSC8V/aUbMYNIkRZINFU/M35sBOpWHxBThsOeBS KEIzogfhyc6oKSsAk2YGwK0ME+fCEo/w80Z1Z9ayjNtuXsqgbtvNhLAfAboSmovGhBAQ 88k6ol9JVZme/Kzw8CzQurz6mXCKXaS1+uWtzwaPVZIuaKH5yyF3bdjuNLlVRuIKSIj3 fIkIm6/rjM6Nza3poP8AQNvV7KESb1f7pHwUlsYkHc9HCP0gbr+l5O8tBwu93o9YO3HO yQpA== X-Gm-Message-State: AOAM531bc4Vrn1WlyZit7+zAqa/oyhIg/e1XQtr60zQoqeYDV2XJdKQs Ppaho2ZskXAxmyganxcempXoL9J7AKCIbQ== X-Google-Smtp-Source: ABdhPJxP0mCMiMuZGLr+3DAyhNbzAUxEEM6LB5BxG4tIxxl1B5kEazqoB/Zu2/beV8lo1cRu86bjMw== X-Received: by 2002:a05:6808:bc7:: with SMTP id o7mr2588461oik.172.1638256347413; Mon, 29 Nov 2021 23:12:27 -0800 (PST) Received: from mail-ot1-f43.google.com (mail-ot1-f43.google.com. [209.85.210.43]) by smtp.gmail.com with ESMTPSA id c8sm3078019otk.40.2021.11.29.23.12.26 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Nov 2021 23:12:26 -0800 (PST) Received: by mail-ot1-f43.google.com with SMTP id n17-20020a9d64d1000000b00579cf677301so29004125otl.8 for ; Mon, 29 Nov 2021 23:12:26 -0800 (PST) X-Received: by 2002:a05:6830:148c:: with SMTP id s12mr48048180otq.105.1638256346260; Mon, 29 Nov 2021 23:12:26 -0800 (PST) MIME-Version: 1.0 References: <1638250994-21268-1-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1638250994-21268-1-git-send-email-nelson.chu@sifive.com> From: Andrew Waterman Date: Mon, 29 Nov 2021 23:12:13 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved. To: Nelson Chu Cc: Binutils , jim.wilson.gcc@gmail.com, Craig topper Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Nov 2021 07:12:31 -0000 LGTM. Thanks, Nelson. Andrew On Mon, Nov 29, 2021 at 9:43 PM Nelson Chu wrote: > > Consider the following case, > > vsetvli a0, a1, 0x4 # unrecognized vlmul > vsetvli a0, a1, 0x20 # unrecognized vsew > vsetivli a0, 0xb, 0x4 # unrecognized vlmul > vsetivli a0, 0xb, 0x20 # unrecognized vsew > > For the current dis-assembler, we get the result, > > 0000000000000000 <.text>: > 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu > 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu > 8: c045f557 vsetivli a0,11,e8,(null),tu,mu > c: c205f557 vsetivli a0,11,e128,m1,tu,mu > > The vsew e128 and vlmul (null) are preserved according to the spec, > so dump these fields looks wrong. Consider that we are used to dump > the unrecognized csr as csr numbers directly, we should also dump > the whole vset[i]vli immediates as numbers, once the vsew or vlmul > is reserved. Therefore, following is what I expected, > > 0000000000000000 <.text>: > 0: 0045f557 vsetvli a0,a1,4 > 4: 0205f557 vsetvli a0,a1,32 > 8: c045f557 vsetivli a0,11,4 > c: c205f557 vsetivli a0,11,32 > > gas/ > * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli > testcases since we should dump the immediate as numbers once > the vsew or vlmul is reserved. > * testsuite/gas/riscv/vector-insns.s: Likewise. > opcodes/ > * riscv-dis.c (print_insn_args): The reserved vsew and vlmul > are NULL string in the riscv_vsew and riscv_vlmul, so dump the > whole imm as numbers once one of them is NULL. > * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. > (riscv_vlmul): Set the reserved vlmul to NULL. > --- > gas/testsuite/gas/riscv/vector-insns.d | 46 +++++++++---------------------- > gas/testsuite/gas/riscv/vector-insns.s | 50 ++++++++++------------------------ > opcodes/riscv-dis.c | 4 ++- > opcodes/riscv-opc.c | 4 +-- > 4 files changed, 33 insertions(+), 71 deletions(-) > > diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d > index 711f927..6325c74 100644 > --- a/gas/testsuite/gas/riscv/vector-insns.d > +++ b/gas/testsuite/gas/riscv/vector-insns.d > @@ -10,40 +10,20 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2 > [ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu > [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047 > -[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu > -[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu > -[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu > -[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > +[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4 > +[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32 > +[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu > +[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu > +[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu > +[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma > [ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu > -[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma > -[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu > -[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu > -[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu > -[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu > -[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > -[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > +[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023 > +[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4 > +[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32 > +[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu > +[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu > +[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu > +[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s > index 37b6ba4..8370264 100644 > --- a/gas/testsuite/gas/riscv/vector-insns.s > +++ b/gas/testsuite/gas/riscv/vector-insns.s > @@ -1,40 +1,20 @@ > - vsetvl a0, a1, a2 > - vsetvli a0, a1, 0 > - vsetvli a0, a1, 0x7ff > - vsetvli a0, a1, e16, m2 > - vsetvli a0, a1, e256, m8 > - vsetvli a0, a1, e512, m8 > - vsetvli a0, a1, e1024, m8 > - vsetvli a0, a1, e1024, m1 > - vsetvli a0, a1, e1024, mf2 > - vsetvli a0, a1, e512, mf4 > - vsetvli a0, a1, e256, mf8 > - vsetvli a0, a1, e256, m2, ta > - vsetvli a0, a1, e256, m2, ma > - vsetvli a0, a1, e256, m2, tu > - vsetvli a0, a1, e256, m2, mu > - vsetvli a0, a1, e256, m2, ta, ma > - vsetvli a0, a1, e256, m2, tu, ma > - vsetvli a0, a1, e256, m2, ta, mu > - vsetvli a0, a1, e256, m2, tu, mu > + vsetvl a0, a1, a2 > + vsetvli a0, a1, 0 > + vsetvli a0, a1, 0x7ff > + vsetvli a0, a1, 0x4 # unrecognized vlmul > + vsetvli a0, a1, 0x20 # unrecognized vsew > + vsetvli a0, a1, e8, m2 > + vsetvli a0, a1, e16, m4, ta > + vsetvli a0, a1, e32, mf4, mu > + vsetvli a0, a1, e64, mf8, tu, ma > vsetivli a0, 0xb, 0 > vsetivli a0, 0xb, 0x3ff > - vsetivli a0, 0xb, e16, m2 > - vsetivli a0, 0xb, e256, m8 > - vsetivli a0, 0xb, e512, m8 > - vsetivli a0, 0xb, e1024, m8 > - vsetivli a0, 0xb, e1024, m1 > - vsetivli a0, 0xb, e1024, mf2 > - vsetivli a0, 0xb, e512, mf4 > - vsetivli a0, 0xb, e256, mf8 > - vsetivli a0, 0xb, e256, m2, ta > - vsetivli a0, 0xb, e256, m2, ma > - vsetivli a0, 0xb, e256, m2, tu > - vsetivli a0, 0xb, e256, m2, mu > - vsetivli a0, 0xb, e256, m2, ta, ma > - vsetivli a0, 0xb, e256, m2, tu, ma > - vsetivli a0, 0xb, e256, m2, ta, mu > - vsetivli a0, 0xb, e256, m2, tu, mu > + vsetivli a0, 0xb, 0x4 # unrecognized vlmul > + vsetivli a0, 0xb, 0x20 # unrecognized vsew > + vsetivli a0, 0xb, e8, m2 > + vsetivli a0, 0xb, e16, m4, ta > + vsetivli a0, 0xb, e32, mf4, mu > + vsetivli a0, 0xb, e64, mf8, tu, ma > > vlm.v v4, (a0) > vlm.v v4, 0(a0) > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index 18e498a..a3c8506 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -334,7 +334,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > && imm_vlmul < ARRAY_SIZE (riscv_vlmul) > && imm_vta < ARRAY_SIZE (riscv_vta) > && imm_vma < ARRAY_SIZE (riscv_vma) > - && !imm_vtype_res) > + && !imm_vtype_res > + && riscv_vsew[imm_vsew] != NULL > + && riscv_vlmul[imm_vlmul] != NULL) > print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew], > riscv_vlmul[imm_vlmul], riscv_vta[imm_vta], > riscv_vma[imm_vma]); > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index bad77fb..40037db 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -76,13 +76,13 @@ const char * const riscv_vecm_names_numeric[NVECM] = > /* The vsetvli vsew constants. */ > const char * const riscv_vsew[8] = > { > - "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024" > + "e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL > }; > > /* The vsetvli vlmul constants. */ > const char * const riscv_vlmul[8] = > { > - "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2" > + "m1", "m2", "m4", "m8", NULL, "mf8", "mf4", "mf2" > }; > > /* The vsetvli vta constants. */ > -- > 2.7.4 >