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[209.85.166.53]) by smtp.gmail.com with ESMTPSA id m35-20020a05663840a300b0046f02c793a6sm656796jam.52.2024.02.10.16.50.18 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 10 Feb 2024 16:50:18 -0800 (PST) Received: by mail-io1-f53.google.com with SMTP id ca18e2360f4ac-7c45636407bso16678639f.1 for ; Sat, 10 Feb 2024 16:50:18 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXtk8xKHrinc55POOqhj9h0cNavuIjTFADMA8MIig+bGm5OElcvaF7RUeqvMvjN8FkQBHjjEYqF0wvAs6HVxys653hSC47ZMg== X-Received: by 2002:a6b:db09:0:b0:7c3:fa21:b7f8 with SMTP id t9-20020a6bdb09000000b007c3fa21b7f8mr4434123ioc.16.1707612618313; Sat, 10 Feb 2024 16:50:18 -0800 (PST) MIME-Version: 1.0 References: <4EF79A76-0C4A-492C-95E5-F12B338F637D@jacob.remcomp.fr> <6c936101-c79a-40b0-b627-cc6d8e741d43@linux.ibm.com> <80629157-361A-457F-81E1-21D2D23DD99F@jacob.remcomp.fr> In-Reply-To: <80629157-361A-457F-81E1-21D2D23DD99F@jacob.remcomp.fr> From: Andrew Waterman Date: Sat, 10 Feb 2024 16:50:07 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Defined illegal instruction To: jacob navia Cc: Peter Bergner , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, Feb 10, 2024 at 4:56=E2=80=AFAM jacob navia wrote: > > OK. So now we have: > > unimp and > c.unimp > > Both generate 16 bit zeroes if the C extension is present. > > If the C extension is not present, > unimp generates > > csrw cycle, x0 > > If we want to generate the defined unimplemented instruction in 32 bis we= write > > .long 0 > > As in the power PC. Sounds like an accurate summary. > > I am going through each one of the instructions because I am writing a fu= ll documentation for the gas assembler for riscv. It has now approx 200 pag= es, with explanations about the riscv encoding, the software, its history, = etc. > > > Thanks for your help. > Jacob > > > > Le 10 f=C3=A9vr. 2024 =C3=A0 01:03, Andrew Waterman = a =C3=A9crit : > > > > If memory serves, the reason we didn't define unimp to be 0x00000000 > > is that 0x0000 is a 16-bit-long instruction (because the two LSBs are > > zero). When targeting RISC-V variants that lack support for 16-bit > > instructions (via the C extension), the inclusion of a 16-bit-long > > instruction (or, I suppose, a pair of 16-bit-long instructions) can > > confuse both humans and disassemblers. unimp does map to 0x0000 when > > the C extension is provided; it only maps to the > > illegal-write-of-read-only-CSR when the C extension is not provided. > > > > On Fri, Feb 9, 2024 at 9:48=E2=80=AFAM Peter Bergner wrote: > >> > >> On 2/9/24 11:03 AM, jacob navia wrote: > >>> The riscv processor defines an illegal instruction (all zeroes). I do= not > >>> find the mnemonic used by gas for this. As far as I remember, the x86= also > >>> has a defined illegal instruction. > >> > >> I can't speak for riscv or x86, but Power also defines a 32-bit all ze= ro > >> instruction as an illegal instruction. We do not have a mnemonic for = it > >> though. When we want to emit that into the instruction stream, we jus= t > >> emit a ".long 0" assembler directive. Maybe the other architectures d= o > >> the same thing? > >> > >> Peter > >> >