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[209.85.166.175]) by smtp.gmail.com with ESMTPSA id b3-20020a056638150300b00471501f5e1asm130409jat.81.2024.02.09.16.03.52 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Feb 2024 16:03:52 -0800 (PST) Received: by mail-il1-f175.google.com with SMTP id e9e14a558f8ab-363ac28b375so5094595ab.3 for ; Fri, 09 Feb 2024 16:03:52 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUx2Vlvdgagetopt//ZjFF+QChl5eLrHcDx8avspSqbuqLYt/rOOUwKiEKN8dgYCDJstX8pR7p+afJ90yCKIx7uEe7g1W9aWQ== X-Received: by 2002:a05:6e02:dee:b0:363:8249:595 with SMTP id m14-20020a056e020dee00b0036382490595mr888595ilj.5.1707523432528; Fri, 09 Feb 2024 16:03:52 -0800 (PST) MIME-Version: 1.0 References: <4EF79A76-0C4A-492C-95E5-F12B338F637D@jacob.remcomp.fr> <6c936101-c79a-40b0-b627-cc6d8e741d43@linux.ibm.com> In-Reply-To: <6c936101-c79a-40b0-b627-cc6d8e741d43@linux.ibm.com> From: Andrew Waterman Date: Fri, 9 Feb 2024 16:03:41 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: Defined illegal instruction To: Peter Bergner Cc: jacob navia , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: If memory serves, the reason we didn't define unimp to be 0x00000000 is that 0x0000 is a 16-bit-long instruction (because the two LSBs are zero). When targeting RISC-V variants that lack support for 16-bit instructions (via the C extension), the inclusion of a 16-bit-long instruction (or, I suppose, a pair of 16-bit-long instructions) can confuse both humans and disassemblers. unimp does map to 0x0000 when the C extension is provided; it only maps to the illegal-write-of-read-only-CSR when the C extension is not provided. On Fri, Feb 9, 2024 at 9:48=E2=80=AFAM Peter Bergner wrote: > > On 2/9/24 11:03 AM, jacob navia wrote: > > The riscv processor defines an illegal instruction (all zeroes). I do n= ot > > find the mnemonic used by gas for this. As far as I remember, the x86 a= lso > > has a defined illegal instruction. > > I can't speak for riscv or x86, but Power also defines a 32-bit all zero > instruction as an illegal instruction. We do not have a mnemonic for it > though. When we want to emit that into the instruction stream, we just > emit a ".long 0" assembler directive. Maybe the other architectures do > the same thing? > > Peter >