From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id EA1E138A9094 for ; Mon, 12 Dec 2022 12:44:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EA1E138A9094 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-x62a.google.com with SMTP id vv4so27646505ejc.2 for ; Mon, 12 Dec 2022 04:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Vo5rX9zwsDVbZ9n3tMalIsDj/tL5wgSzcTcC9ofZ7K8=; b=WnSOWC5mjA7ATzz7aEbwDpZ/rF9tYAZzGvDmauZWdhdKc7uP2opptw4TWckLlGM5L3 I5DfAzfD46dfIQTI+o9MxBG8laSKBmG3EmXLFaKRpN0uHbOnHQJp+ZiSkdKdvbMlZh/t MGTVu6gzD0y81Fq0xXZ2R7LlKAAuizu83xl0hV+KJyE9swU/IUhaCARBIqvqh29MeoQW f3rGxUJLR3uUsDbDKvkLZIWLhsHWE52Tt6a66Z9LLLXaWFuHzZGyaoftwbUH4b7oCYJz XlZ64UR9lr2jrm21XM7aId9aLn2Fv2u5ErXlFHW1tot+QS9jzW2WkZ9CxT6vWRmXWw/B M/Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Vo5rX9zwsDVbZ9n3tMalIsDj/tL5wgSzcTcC9ofZ7K8=; b=UKS73gFrx2oCTRuhNe13AVS8Jx8OtyQN7ynR2K0wLUOfeBAB56xulsNIJ7DmBjVw8j EiwstU3Hsfqp9uzFVNd2oZDe+gIDgCbuntjbs7H/QyWDg6gzXhGc9Svrp3HMX8HEcYmP R0rSEQx0h39l75npIQsgtScxb1HG7EEnVGAGWdvaAuw+HNhxgINnP5aqSv8CJ8jwYnv8 UOengVDHOlsWz/kPLVh4JZXKScmEGq2cwkatp6BzIslazYOMt/rR4N7eGIUrgr8ji1fw 30/ypDR5YdE3to0yIUIXRmEp5+zByCmiCaa1+T5xTolxpThH6meErdh60ab77UfVAKpk DZxg== X-Gm-Message-State: ANoB5pmTHxqjpSUoPr4TaOqg/dcGX+tAf1UAUWvAujOBD2Lw/xNJPEV8 /NJkDonPoZEPe8jm6Gs+vDaJv8pMRoOkIdYg2sjWYeuSHvHPdg== X-Google-Smtp-Source: AA0mqf6q+G3V6C1NtaK+NhPf3i+fYm+Vz1dXxX8KLIoR5R+gSq7gOhoyCs/CKp3vxkg+/eJcZDHIs3GGoGCp79xA54s= X-Received: by 2002:a17:906:5156:b0:7c0:efb6:8744 with SMTP id jr22-20020a170906515600b007c0efb68744mr16355200ejc.267.1670849056671; Mon, 12 Dec 2022 04:44:16 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: "Lad, Prabhakar" Date: Mon, 12 Dec 2022 12:43:50 +0000 Message-ID: Subject: Re: [QUERY]: Adding support for a platform To: Palmer Dabbelt Cc: Andrew Waterman , jrtc27@jrtc27.com, binutils@sourceware.org, linux-riscv@lists.infradead.org, Chris Paterson Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Palmer, Sorry for the late reply. On Tue, Nov 29, 2022 at 9:54 PM Palmer Dabbelt wrote: > > On Tue, 29 Nov 2022 13:40:53 PST (-0800), prabhakar.csengg@gmail.com wrote: > > Hi Palmer, > > > > On Tue, Nov 29, 2022 at 8:57 PM Palmer Dabbelt wrote: > >> > >> On Tue, 29 Nov 2022 12:21:31 PST (-0800), Andrew Waterman wrote: > >> > On Tue, Nov 29, 2022 at 12:12 PM Jessica Clarke wrote: > >> >> > >> >> On 29 Nov 2022, at 19:28, Lad, Prabhakar wrote: > >> >> > > >> >> > Hi Palmer, > >> >> > > >> >> > Oops I should have included linux-riscv to the CC list here (doing it now) > >> >> > > >> >> > On Tue, Nov 29, 2022 at 7:20 PM Palmer Dabbelt wrote: > >> >> >> > >> >> >> On Tue, 29 Nov 2022 11:16:29 PST (-0800), binutils@sourceware.org wrote: > >> >> >>> Hi All, > >> >> >>> > >> >> >>> If this is not the right place to ask this question please let me know. > >> >> >>> > >> >> >>> So we have a RISCV platform (Renesas RZ/Five) for which we need to > >> >> >>> adjust the TEXT_START_ADDR. So below are my queries: > >> >> >>> * What is the procedure for upstreaming? > >> >> >>> * Are patches accepted for individual platforms (for adjusting TEXT_START_ADDR)? > > Enabling the local memory (ILM/DLM) on the core is a specification > > option and is enabled on RZ/Five SoC. I'm checking with Andes if this > > can be forcefully disabled. > > The only use case would be to speed up things for some slower block > > (but said that its user application specific) > > If it's possible to disable this somehow that'd be great, but after > writing up the "maybe we can context switch this" bit I think we could > probably get away with some sort of compatibility mode here. > Essentially: Don't allocate out of this region by default, but if > userspace explicitly maps this region (as happens with static binaries) > then allow it, but track those allocations and begin swapping it on > context switches. > Do you think even with TEXT_START_ADDR change user space can map into LM? > That might be a lot of work and would definitely be slow, but as long as > other VAs can map to these PAs then I think we'd be pretty much safe -- > we'd lose read-only and execute-only permission tracking, but existing > binaries would still run. That would allow this TEXT_START_ADDR change > to be just a performance thing, and we might want that as a tunable for > distros anyway (for huge page alignment, for example). > Okay, I'll create a patch for the TEXT_START_ADDR change. > A lot of that would depend on exactly how the hardware treats these > special VAs, though. Probably best if you just dig through the docs, > see how this all works, and then propose some rough patches? I checked with Andes and it looks like we cannot disable the local memory by registers. As per Andes [0] (page 30) if the VA is Local memory (LM) it straight aways treats it as PA and it never searches through TLB (note there is a arrow missing in the diagram VA->PA if LM) [0] http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf Cheers, Prabhakar