> Is the following expected? Yes. > Seems "vd is any" also has the same issue. I rechecked the spec, for every masked vmsge{u}.vx, the lowered instruction is only masked when `vd != v0`. So your patch does fix these two problems. Thank you for clarifying. Best Regards, Kiva Oyama On Wed, Aug 30, 2023 at 1:51 PM Jan Beulich wrote: > On 30.08.2023 04:51, Nelson Chu wrote: > > Hi Jan, > > Thanks for pointing that out. > > > > Hi Kiva, > > Maybe you can send a better patch for this issue if you are interested, > > including what Jan suggested. Thanks :-) > > Hmm, both of your replies above make me suspect a misunderstanding: I > think your patch does exactly what is needed. > > Jan > > > On Tue, Aug 29, 2023 at 4:52 PM Jan Beulich wrote: > > > >> On 29.08.2023 09:59, Nelson Chu wrote: > >>> Is the following expected? > >> > >> I think so, but Kiva - please confirm. > >> > >>> Seems "vd is any" also has the same issue. > >> > >> Right, that's what ... > >> > >>>> I think this wants fixing alike in binutils: From looking at > >>>> vector_macro(), > >>>> it appears that emitting the masked form is merely an accident > resulting > >>>> from the inverted encoding of "masking". In particular, if masking was > >>>> indeed meant, I expect code there would be > >>>> > >>>> if (vd == vm) > >>>> { > >>>> macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", > vtemp, > >>>> vs2, vs1, vm); > >>>> macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", > vd, > >>>> vm, vtemp); > >>>> } > >>>> else > >>>> ... > >>>> > >>>> much like it is a few lines down from there. (Apparently the "else" > path > >>>> omitted above is similarly affected.) > >> > >> ... I was referring to with the parenthesized sentence. > >> > >> Jan > >> > > > >