[RISCV] [GNU AS] Possible `vmsge{u}.vx` instruction lowering bug?

[im Kiva <libkernelpanic@gmail.com>]

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Hi maintainers,

I discovered that GNU Assembler (as) lowers `vmsge.vx` and `vmsgeu.vx` (pseudo
instructions from RISC-V Vector Extension [1]) when the destination
register is v0 as follows:

vmsge{u}.vx v0, v4, a0, v0.t, v2

will be expanded to:

vmslt{u}.vx v2, v4, a0, v0.t
vmandn.mm v0, v0, v2

You can inspect the lowering result with Godbolt [2].
However, according to the Vector specification [1] page 52. The "desugared"
`vmslt{u}.vx` is not masked:

> masked va >= x, vd == v0
>   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
>   expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt

So the spec-expected result of the example above should be:
vmslt{u}.vx v2, v4, a0 <-- no v0.t here
vmandn.mm v0, v0, v2

I thus submitted a patch to the LLVM [3], and it was accepted recently.

I am wondering if binutils considers it a bug, or if it is just intentional
because of some historical and compatibility reasons.
Thanks.

Best regards
Kiva Oyama

[1]: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
[2]: https://godbolt.org/z/aszc5d8sh
[3]: https://reviews.llvm.org/D158392