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From: im Kiva <>
Subject: [RISCV] [GNU AS] Possible `vmsge{u}.vx` instruction lowering bug?
Date: Tue, 29 Aug 2023 14:52:36 +0800	[thread overview]
Message-ID: <> (raw)

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Hi maintainers,

I discovered that GNU Assembler (as) lowers `vmsge.vx` and `vmsgeu.vx` (pseudo
instructions from RISC-V Vector Extension [1]) when the destination
register is v0 as follows:

vmsge{u}.vx v0, v4, a0, v0.t, v2

will be expanded to:

vmslt{u}.vx v2, v4, a0, v0.t v0, v0, v2

You can inspect the lowering result with Godbolt [2].
However, according to the Vector specification [1] page 52. The "desugared"
`vmslt{u}.vx` is not masked:

> masked va >= x, vd == v0
>   pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
>   expansion: vmslt{u}.vx vt, va, x; vd, vd, vt

So the spec-expected result of the example above should be:
vmslt{u}.vx v2, v4, a0 <-- no v0.t here v0, v0, v2

I thus submitted a patch to the LLVM [3], and it was accepted recently.

I am wondering if binutils considers it a bug, or if it is just intentional
because of some historical and compatibility reasons.

Best regards
Kiva Oyama


             reply	other threads:[~2023-08-29  6:52 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29  6:52 im Kiva [this message]
2023-08-29  7:43 ` Jan Beulich
2023-08-29  7:59   ` Nelson Chu
2023-08-29  8:52     ` Jan Beulich
2023-08-30  2:51       ` Nelson Chu
2023-08-30  5:50         ` Jan Beulich
2023-09-01  6:37           ` Kiva Oyama
2023-09-01  8:03             ` Nelson Chu

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