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To: Jiawei Cc: binutils@sourceware.org, nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, research_trasio@irq.a4lg.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, nandni.jamnadas@embecosm.com, mary.bennett@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, sinan.lin@linux.alibaba.com, gaofei@eswincomputing.com, fujin.zhao@foxmail.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: objdump support for print_jvt_entry_value/print_jvt_index seems incomplete? nobody initializes jvt_base and jvt_end, also not testcase for that. I would suggest just splitting that part into a separated patch. On Wed, Jan 24, 2024 at 9:52=E2=80=AFPM Jiawei wrote: > > This patch supports Zcmt instruction 'cm.jt' and 'cm.jalt'. > Add new CSR jvt for tablejump using. > > Co-Authored by: Charlie Keaney > Co-Authored by: Mary Bennett > Co-Authored by: Nandni Jamnadas > Co-Authored by: Sinan Lin > Co-Authored by: Simon Cook > Co-Authored by: Shihua Liao > Co-Authored by: Yulong Shi > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): New extension. > (riscv_multi_subset_supports_ext): Ditto. > > gas/ChangeLog: > > * config/tc-riscv.c (enum riscv_csr_class): New CSR. > (riscv_csr_address): Ditto. > (validate_riscv_insn): New operand. > (riscv_ip): Ditto. > * testsuite/gas/riscv/csr-version-1p10.d: New CSR case. > * testsuite/gas/riscv/csr-version-1p10.l: Ditto. > * testsuite/gas/riscv/csr-version-1p11.d: Ditto. > * testsuite/gas/riscv/csr-version-1p11.l: Ditto. > * testsuite/gas/riscv/csr-version-1p12.d: Ditto. > * testsuite/gas/riscv/csr-version-1p12.l: Ditto. > * testsuite/gas/riscv/csr-version-1p9p1.d: Ditto. > * testsuite/gas/riscv/csr-version-1p9p1.l: Ditto. > * testsuite/gas/riscv/csr.s: Ditto. > * testsuite/gas/riscv/zcmt.d: New test. > * testsuite/gas/riscv/zcmt.s: New test. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_TABLE_JUMP): New opcode. > (MASK_CM_JT): New mask. > (MASK_CM_JALT): Ditto. > (CSR_JVT): New CSR. > (DECLARE_CSR): New declaration. > * opcode/riscv.h (EXTRACT_ZCMT_TABLE_JUMP_INDEX): New marco. > (ENCODE_ZCMT_TABLE_JUMP_INDEX): Ditto. > (enum riscv_insn_class): New class. > > opcodes/ChangeLog: > > * riscv-dis.c (struct riscv_private_data): New data. > (print_jvt_index): New function. > (print_jvt_entry_value): Ditto. > (print_insn_args): New operand. > * riscv-opc.c (match_cm_jt): New function. > (match_cm_jalt): Ditto. > > --- > bfd/elfxx-riscv.c | 7 +++ > gas/config/tc-riscv.c | 28 +++++++++++ > gas/testsuite/gas/riscv/csr-version-1p10.d | 2 + > gas/testsuite/gas/riscv/csr-version-1p10.l | 4 ++ > gas/testsuite/gas/riscv/csr-version-1p11.d | 2 + > gas/testsuite/gas/riscv/csr-version-1p11.l | 4 ++ > gas/testsuite/gas/riscv/csr-version-1p12.d | 2 + > gas/testsuite/gas/riscv/csr-version-1p12.l | 4 ++ > gas/testsuite/gas/riscv/csr-version-1p9p1.d | 2 + > gas/testsuite/gas/riscv/csr-version-1p9p1.l | 4 ++ > gas/testsuite/gas/riscv/csr.s | 3 ++ > gas/testsuite/gas/riscv/zcmt.d | 14 ++++++ > gas/testsuite/gas/riscv/zcmt.s | 5 ++ > include/opcode/riscv-opc.h | 8 +++ > include/opcode/riscv.h | 5 ++ > opcodes/riscv-dis.c | 56 +++++++++++++++++++++ > opcodes/riscv-opc.c | 23 +++++++++ > 17 files changed, 173 insertions(+) > create mode 100644 gas/testsuite/gas/riscv/zcmt.d > create mode 100644 gas/testsuite/gas/riscv/zcmt.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 2ad4682f19f..cc1d66cb3a7 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1194,6 +1194,8 @@ static struct riscv_implicit_subset riscv_implicit_= subsets[] =3D > {"zcd", "zca", check_implicit_always}, > {"zcb", "zca", check_implicit_always}, > {"zcmp", "zca", check_implicit_always}, > + {"zcmt", "zca", check_implicit_always}, > + {"zcmt", "zicsr", check_implicit_always}, > {"smaia", "ssaia", check_implicit_always}, > {"smcntrpmf", "zicsr", check_implicit_always}, > {"smstateen", "ssstateen", check_implicit_always}, > @@ -1342,6 +1344,7 @@ static struct riscv_supported_ext riscv_supported_s= td_z_ext[] =3D > {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zcmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {NULL, 0, 0, 0, 0} > }; > > @@ -2579,6 +2582,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *= rps, > && riscv_subset_supports (rps, "zmmul")); > case INSN_CLASS_ZCMP: > return riscv_subset_supports (rps, "zcmp"); > + case INSN_CLASS_ZCMT: > + return riscv_subset_supports (rps, "zcmt"); > case INSN_CLASS_SVINVAL: > return riscv_subset_supports (rps, "svinval"); > case INSN_CLASS_H: > @@ -2833,6 +2838,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset= _t *rps, > return _("zcb' and `zmmul', or `zcb' and `m"); > case INSN_CLASS_ZCMP: > return "zcmp"; > + case INSN_CLASS_ZCMT: > + return "zcmt"; > case INSN_CLASS_SVINVAL: > return "svinval"; > case INSN_CLASS_H: > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 569bbbac3fd..97285332e65 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -72,6 +72,7 @@ enum riscv_csr_class > CSR_CLASS_F, /* f-ext only */ > CSR_CLASS_ZKR, /* zkr only */ > CSR_CLASS_V, /* rvv only */ > + CSR_CLASS_ZCMT, /* zcmt only */ > CSR_CLASS_DEBUG, /* debug CSR */ > CSR_CLASS_H, /* hypervisor */ > CSR_CLASS_H_32, /* hypervisor, rv32 only */ > @@ -1052,6 +1053,9 @@ riscv_csr_address (const char *csr_name, > case CSR_CLASS_V: > extension =3D "zve32x"; > break; > + case CSR_CLASS_ZCMT: > + extension =3D "zcmt"; > + break; > case CSR_CLASS_SMAIA_32: > is_rv32_only =3D true; > /* Fall through. */ > @@ -1577,6 +1581,8 @@ validate_riscv_insn (const struct riscv_opcode *opc= , int length) > case 'p': used_bits |=3D ENCODE_ZCMP_SPIMM (-1U); break; > /* register list operand for cm.push and cm.pop. */ > case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); br= eak; > + case 'i': > + case 'I': used_bits |=3D ENCODE_ZCMT_TABLE_JUMP_INDEX (-1= U); break; > case 'f': break; > default: > goto unknown_validate_operand; > @@ -3829,6 +3835,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, exp= ressionS *imm_expr, > break; > INSERT_OPERAND (SREG2, *ip, regno % 8); > continue; > + case 'I': /* index operand of cm.jt. The range is fro= m 0 to 31. */ > + my_getExpression (imm_expr, asarg); > + if (imm_expr->X_op !=3D O_constant > + || imm_expr->X_add_number < 0 > + || imm_expr->X_add_number > 31) > + { > + as_bad ("bad index value for cm.jt, range: [0, = 31]"); > + break; > + } > + ip->insn_opcode |=3D ENCODE_ZCMT_TABLE_JUMP_INDEX (= imm_expr->X_add_number); > + goto rvc_imm_done; > + case 'i': /* index operand of cm.jalt. The range is f= rom 32 to 255. */ > + my_getExpression (imm_expr, asarg); > + if (imm_expr->X_op !=3D O_constant > + || imm_expr->X_add_number < 32 > + || imm_expr->X_add_number > 255) > + { > + as_bad ("bad index value for cm.jalt, range: [3= 2, 255]"); > + break; > + } > + ip->insn_opcode |=3D ENCODE_ZCMT_TABLE_JUMP_INDEX (= imm_expr->X_add_number); > + goto rvc_imm_done; > default: > goto unknown_riscv_ip_operand; > } > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/g= as/riscv/csr-version-1p10.d > index dbdc077adac..b42331338fa 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d > @@ -895,3 +895,5 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 > [ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 > +[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt > +[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/g= as/riscv/csr-version-1p10.l > index 054179a416d..44ef6ff53ce 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p10.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p10.l > @@ -1613,3 +1613,7 @@ > .*Info: macro .* > .*Warning: read-only CSR is written `csrw vlenb,a1' > .*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/g= as/riscv/csr-version-1p11.d > index 7ba88b6d1d5..b9eb5235fa2 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d > @@ -895,3 +895,5 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 > [ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 > +[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt > +[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/g= as/riscv/csr-version-1p11.l > index cc365f1df41..a2dcc24ffb7 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p11.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p11.l > @@ -1609,3 +1609,7 @@ > .*Info: macro .* > .*Warning: read-only CSR is written `csrw vlenb,a1' > .*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/g= as/riscv/csr-version-1p12.d > index 677820b9526..fcd48003ef9 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d > @@ -895,3 +895,5 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 > [ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 > +[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt > +[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/g= as/riscv/csr-version-1p12.l > index 7a7f5f717c5..f6533672805 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p12.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p12.l > @@ -1373,3 +1373,7 @@ > .*Info: macro .* > .*Warning: read-only CSR is written `csrw vlenb,a1' > .*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/= gas/riscv/csr-version-1p9p1.d > index f4d2b04ca6a..d3540c1690c 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d > @@ -895,3 +895,5 @@ Disassembly of section .text: > [ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1 > [ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb > [ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1 > +[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt > +[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1 > diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/= gas/riscv/csr-version-1p9p1.l > index 7fcd73ab7dd..bfd8111508f 100644 > --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l > +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l > @@ -1681,3 +1681,7 @@ > .*Info: macro .* > .*Warning: read-only CSR is written `csrw vlenb,a1' > .*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > +.*Warning: invalid CSR `jvt', needs `zcmt' extension > +.*Info: macro .* > diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.= s > index 3d8da5488a0..c542cd9243c 100644 > --- a/gas/testsuite/gas/riscv/csr.s > +++ b/gas/testsuite/gas/riscv/csr.s > @@ -510,3 +510,6 @@ > csr vl > csr vtype > csr vlenb > + > + # Zcmt > + csr jvt > diff --git a/gas/testsuite/gas/riscv/zcmt.d b/gas/testsuite/gas/riscv/zcm= t.d > new file mode 100644 > index 00000000000..d37e4644869 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zcmt.d > @@ -0,0 +1,14 @@ > +#as: -march=3Drv32i_zcmt > +#source: zcmt.s > +#objdump: -dr -Mno-aliases > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 : > +[ ]*[0-9a-f]+:[ ]+a002[ ]+cm.jt[ ]+0 # a07ea002 <= target\+0xa07ea002> > +[ ]*[0-9a-f]+:[ ]+a07e[ ]+cm.jt[ ]+31 > +[ ]*[0-9a-f]+:[ ]+a102[ ]+cm.jalt[ ]+64 > +[ ]*[0-9a-f]+:[ ]+a3fe[ ]+cm.jalt[ ]+255 > diff --git a/gas/testsuite/gas/riscv/zcmt.s b/gas/testsuite/gas/riscv/zcm= t.s > new file mode 100644 > index 00000000000..0392eea9846 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zcmt.s > @@ -0,0 +1,5 @@ > +target: > + cm.jt 0 > + cm.jt 31 > + cm.jalt 64 > + cm.jalt 255 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 606982d7bb7..27223946aff 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2248,6 +2248,10 @@ > #define MASK_CM_MVA01S 0xfc63 > #define MATCH_CM_MVSA01 0xac22 > #define MASK_CM_MVSA01 0xfc63 > +/* Zcmt instructions. */ > +#define MATCH_TABLE_JUMP 0xa002 > +#define MASK_CM_JT 0xff03 > +#define MASK_CM_JALT 0xfc03 > /* Svinval instruction. */ > #define MATCH_SINVAL_VMA 0x16000073 > #define MASK_SINVAL_VMA 0xfe007fff > @@ -3478,6 +3482,8 @@ > #define CSR_MSCONTEXT 0x7aa > /* Unprivileged Scalar Crypto CSR addresses. */ > #define CSR_SEED 0x015 > +/* Unprivileged Zcmt CSR addresses. */ > +#define CSR_JVT 0x017 > /* Unprivileged Vector CSR addresses. */ > #define CSR_VSTART 0x008 > #define CSR_VXSAT 0x009 > @@ -4493,6 +4499,8 @@ DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG= , PRIV_SPEC_CLASS_NONE, PRIV_ > DECLARE_CSR(mscontext, CSR_MSCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_N= ONE, PRIV_SPEC_CLASS_NONE) > /* Unprivileged Scalar Crypto CSRs. */ > DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SP= EC_CLASS_NONE) > +/* Unprivileged Zcmt CSRs. */ > +DECLARE_CSR(jvt, CSR_JVT, CSR_CLASS_ZCMT, PRIV_SPEC_CLASS_NONE, PRIV_SPE= C_CLASS_NONE) > /* Unprivileged Vector CSRs. */ > DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_= SPEC_CLASS_NONE) > DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SP= EC_CLASS_NONE) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index a12c6cc3b1e..10f9c710de3 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -114,6 +114,8 @@ static inline unsigned int riscv_insn_length (insn_t = insn) > (RV_X(x, 5, 1) << 1) > #define EXTRACT_ZCMP_SPIMM(x) \ > (RV_X(x, 2, 2) << 4) > +#define EXTRACT_ZCMT_TABLE_JUMP_INDEX(x) \ > + (RV_X(x, 2, 8)) > /* Vendor-specific (CORE-V) extract macros. */ > #define EXTRACT_CV_IS2_UIMM5(x) \ > (RV_X(x, 20, 5)) > @@ -172,6 +174,8 @@ static inline unsigned int riscv_insn_length (insn_t = insn) > (RV_X(x, 1, 1) << 5) > #define ENCODE_ZCMP_SPIMM(x) \ > (RV_X(x, 4, 2) << 2) > +#define ENCODE_ZCMT_TABLE_JUMP_INDEX(x) \ > + (RV_X(x, 0, 8) << 2) > /* Vendor-specific (CORE-V) encode macros. */ > #define ENCODE_CV_IS2_UIMM5(x) \ > (RV_X(x, 0, 5) << 20) > @@ -492,6 +496,7 @@ enum riscv_insn_class > INSN_CLASS_ZCB_AND_ZBB, > INSN_CLASS_ZCB_AND_ZMMUL, > INSN_CLASS_ZCMP, > + INSN_CLASS_ZCMT, > INSN_CLASS_SVINVAL, > INSN_CLASS_ZICBOM, > INSN_CLASS_ZICBOP, > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index c3be451ba4d..3c51ac3a2a1 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -56,6 +56,8 @@ struct riscv_private_data > { > bfd_vma gp; > bfd_vma print_addr; > + bfd_vma jvt_base; > + bfd_vma jvt_end; > bfd_vma hi_addr[OP_MASK_RD + 1]; > bool to_print_addr; > bool has_gp; > @@ -219,6 +221,54 @@ maybe_print_address (struct riscv_private_data *pd, = int base_reg, int offset, > pd->print_addr =3D (bfd_vma)(uint32_t)pd->print_addr; > } > > +/* Print table jump index. */ > + > +static bool > +print_jvt_index (disassemble_info *info, unsigned int index) > +{ > + bfd_vma entry_value; > + bfd_vma memaddr; > + int status; > + > + bfd_byte packet[8] =3D {0}; > + struct riscv_private_data *pd =3D info->private_data; > + > + memaddr =3D pd->jvt_base + index * (xlen/8); > + status =3D (*info->read_memory_func) (memaddr, packet, xlen / 8, info)= ; > + if (status !=3D 0) > + return false; > + > + entry_value =3D xlen =3D=3D 32 ? bfd_getl32 (packet) > + : bfd_getl64 (packet); > + > + maybe_print_address (pd, 0, entry_value, 0); > + return true; > +} > + > +/* Print table jump entry value. */ > + > +static bool > +print_jvt_entry_value (disassemble_info *info, bfd_vma memaddr) > +{ > + bfd_vma entry_value; > + int status; > + struct riscv_private_data *pd =3D info->private_data; > + bfd_byte packet[8] =3D {0}; > + unsigned index =3D (memaddr - pd->jvt_base) / (xlen / 8); > + > + status =3D (*info->read_memory_func) (memaddr, packet, xlen / 8, info)= ; > + if (status !=3D 0) > + return false; > + > + entry_value =3D xlen =3D=3D 32 ? bfd_getl32 (packet) > + : bfd_getl64 (packet); > + > + info->target =3D entry_value; > + (*info->fprintf_func) (info->stream, "index %u # ", index); > + (*info->print_address_func) (info->target, info); > + return true; > +} > + > /* Get Zcmp reg_list field. */ > > static void > @@ -710,6 +760,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vm= a pc, disassemble_info *info > print (info->stream, dis_style_immediate, "%d", > riscv_get_spimm (l)); > break; > + case 'i': > + case 'I': > + print (info->stream, dis_style_address_offset, > + "%lu", EXTRACT_ZCMT_TABLE_JUMP_INDEX (l)); > + print_jvt_index (info, EXTRACT_ZCMT_TABLE_JUMP_INDEX (l= )); > + break; > default: > goto undefined_modifier; > } > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 9d61ce95433..6c55c68a52d 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -340,6 +340,25 @@ match_sreg1_not_eq_sreg2 (const struct riscv_opcode = *op, insn_t insn) > && (EXTRACT_OPERAND (SREG1, insn) !=3D EXTRACT_OPERAND (SREG2, ins= n)); > } > > +/* This is used for cm.jt. This requires index operand to be less than 3= 2. */ > + > +static int > +match_cm_jt (const struct riscv_opcode *op, insn_t insn) > +{ > + return match_opcode (op, insn) > + && EXTRACT_ZCMT_TABLE_JUMP_INDEX (insn) < 32; > +} > + > +/* This is used for cm.jalt. This requires index operand to be in 32 to = 255. */ > + > +static int > +match_cm_jalt (const struct riscv_opcode *op, insn_t insn) > +{ > + return match_opcode (op, insn) > + && EXTRACT_ZCMT_TABLE_JUMP_INDEX (insn) >=3D 32 > + && EXTRACT_ZCMT_TABLE_JUMP_INDEX (insn) < 256; > +} > + > /* The order of overloaded instructions matters. Label arguments and > register arguments look the same. Instructions that can have either > for arguments must apear in the correct order in this table for the > @@ -2008,6 +2027,10 @@ const struct riscv_opcode riscv_opcodes[] =3D > {"cm.mva01s", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVA01S, MASK_= CM_MVA01S, match_opcode, 0 }, > {"cm.mvsa01", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVSA01, MASK_= CM_MVSA01, match_sreg1_not_eq_sreg2, 0 }, > > +/* Zcmt instructions */ > +{"cm.jt", 0, INSN_CLASS_ZCMT, "WcI", MATCH_TABLE_JUMP, MASK= _CM_JT, match_cm_jt, 0 }, > +{"cm.jalt", 0, INSN_CLASS_ZCMT, "Wci", MATCH_TABLE_JUMP, MASK= _CM_JALT, match_cm_jalt, 0 }, > + > /* Supervisor instructions. */ > {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MAS= K_RS1, match_opcode, INSN_ALIAS }, > {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|M= ASK_RD, match_opcode, INSN_ALIAS }, > -- > 2.25.1 >