From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 8E01B385696D for ; Thu, 7 Jul 2022 02:58:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E01B385696D Received: by mail-ej1-x635.google.com with SMTP id q6so30058960eji.13 for ; Wed, 06 Jul 2022 19:58:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yY5zaxmpOFyT5ETzCSwLblq0u5m8bVbMWAnSa7XSZ7M=; b=Pf0iWFXQo1+iPJJm+DMenAwQqPl4Fzg/eMj/TvGV+4wp8uM7M9CPjjnhTa2+xTOkyg dAg5QzHrh038K10//HS/EHE94GlGSMTxOUI2BXyQwzwwUW+heP5pRkVTqeji/kLuE7wE tzBjukpegZxrxPENI50SfhYcunyMCDTZ2JyjaFXMtG1inzupI1ivAvNBEWe1jWQgTfgV +LnfJFvF3q7/GkhKBEYLqX3L2hEGMZUyHG2P77fp/pch2wuLPKOLOL4zffAE3R2VP3Nj 0duFFC119kPi6rqISedAFkOvEYGt1UwOCmouAJ/wXIqJT3cic5my0uyutLu6ChqUgLAC Jb2Q== X-Gm-Message-State: AJIora/UqouVdayAhlFzDl6mWsATKILyHV6vUqnxK6geenx6r9hqVM4Q xd3/O/wIAYrUm6/n2qk8VMG2O1FgHmmE7/nlgq6dAxqM X-Google-Smtp-Source: AGRyM1sGvP9aFIk0Dg//+RGYoFviAvIk3gkoWeyZvVJUJDdxsIT3Xv5XGkbBQB+QOpc7+7I5bXM88dsaiXWaGVBQr3w= X-Received: by 2002:a17:906:8444:b0:72a:7dda:5d71 with SMTP id e4-20020a170906844400b0072a7dda5d71mr32396478ejy.94.1657162731138; Wed, 06 Jul 2022 19:58:51 -0700 (PDT) MIME-Version: 1.0 References: <20220627020348.11920-1-research_trasio@irq.a4lg.com> <20220627020348.11920-5-research_trasio@irq.a4lg.com> In-Reply-To: <20220627020348.11920-5-research_trasio@irq.a4lg.com> From: Kito Cheng Date: Thu, 7 Jul 2022 10:58:39 +0800 Message-ID: Subject: Re: [PATCH v2 4/8] RISC-V: Fix disassembling Zfinx with -M numeric To: Tsukasa OI Cc: Weiwei Li , Nelson Chu , Kito Cheng , Palmer Dabbelt , Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jul 2022 02:58:55 -0000 LGTM On Mon, Jun 27, 2022 at 10:08 AM Tsukasa OI via Binutils wrote: > > This commit fixes floating point operand register names from ABI ones > to dynamically set ones. > > gas/ChangeLog: > > * testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of > Zfinx extension and -M numeric disassembler option. > * testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise. > > opcodes/ChangeLog: > > * riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR > names to disassemble Zfinx instructions. > --- > gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++ > gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++ > opcodes/riscv-dis.c | 2 +- > 3 files changed, 13 insertions(+), 1 deletion(-) > create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d > create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s > > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d > new file mode 100644 > index 00000000000..ba3f62295eb > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d > @@ -0,0 +1,10 @@ > +#as: -march=rv64ima_zfinx > +#source: zfinx-dis-numeric.s > +#objdump: -dr -Mnumeric > + > +.*:[ ]+file format .* > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12 > diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s > new file mode 100644 > index 00000000000..b55cbd56b21 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s > @@ -0,0 +1,2 @@ > +target: > + feq.s a0, a1, a2 > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index 9ff31167775..164fd209dbd 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -639,7 +639,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) > > /* If arch has ZFINX flags, use gpr for disassemble. */ > if(riscv_subset_supports (&riscv_rps_dis, "zfinx")) > - riscv_fpr_names = riscv_gpr_names_abi; > + riscv_fpr_names = riscv_gpr_names; > > for (; op->name; op++) > { > -- > 2.25.1 >