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From: Kito Cheng <kito.cheng@gmail.com>
Date: Tue, 5 Jul 2022 22:21:35 +0800
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Subject: Re: [PATCH v2 3/8] RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
To: Tsukasa OI <research_trasio@irq.a4lg.com>
Cc: Weiwei Li <liweiwei@iscas.ac.cn>, Nelson Chu <nelson.chu@sifive.com>, 
 Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
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> +{"fmv.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
Maybe we need one more alias for ZFHMIN? like this: {"fmv.h",      0,
INSN_CLASS_ZFHMIN,   "D,U",       MATCH_FSGNJ_S, MASK_FSGNJ_S,
match_rs1_eq_rs2, INSN_ALIAS },

---
Spec say:
Zfhmin does not include the FSGNJ.H instruction, because it suffices to
instead use the FSGNJ.S instruction to move half-precision values between
floating-point registers.