I have write access and will do the push, after approval. Thanks, Philipp. On Sun 18. Sep 2022 at 08:51, Christoph Müllner wrote: > > > On Fri, Sep 16, 2022 at 11:36 AM Nelson Chu wrote: > >> Hi Christoph, >> >> >> On Tue, Sep 6, 2022 at 8:22 PM Christoph Muellner >> wrote: >> > >> > From: Christoph Müllner >> > >> > This series introduces support for the T-Head vendor extensions, >> > which are implemented e.g. in the XuanTie C906 and XuanTie C910 >> > processors: >> > * XTheadBa >> > * XTheadBb >> > * XTheadBs >> > * XTheadCmo >> > * XTheadCondMov >> > * XTheadFMemIdx >> > * XTheadMac >> > * XTheadMemIdx >> > * XTheadMemPair >> > * XTheadSync >> > >> > The xthead* extensions are documented here: >> > >> https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf >> > >> > The "th." instruction prefix prevents future conflicts with standard >> > extensions and has been documentented in a PR for the RISC-V toolchain >> > conventions: >> > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 >> > >> > The goal of this patchset is to provide access to these instruction >> > so that compilers/users can optimize SW accordingly. >> > >> > Note, that the T-Head vendor extensions do not contain all >> > vendor-specific >> > functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are >> > included). >> > Instead the extensions cover coherent functionality, that is exposed to >> > S and U mode. >> > >> > To enable the extensions above, the following two methods are possible: >> > * add the extension to the arch string (e.g. >> > * -march=rv64gc_xtheadcmo_xtheadsync) >> > * implicitly select the extensions via CPU selection (e.g. >> > * -mcpu=thead-c910) >> > >> > The patchset attempts to minimize code changes in generic/infrastructure >> > code. All patches in this series come with tests to avoid future >> regressions. >> > >> > Christoph Müllner (13): >> > RISC-V: Add generic support for vendor extensions >> > RISC-V: Add T-Head CMO vendor extension >> > RISC-V: Add T-Head SYNC vendor extension >> > RISC-V: Add support for arbitrary immediate encoding formats >> > RISC-V: Add T-Head Bitmanip vendor extension >> > RISC-V: Add T-Head CondMov vendor extension >> > RISC-V: Add T-Head MAC vendor extension >> > RISC-V: Add T-Head FMemIdx vendor extension >> > RISC-V: Add T-Head MemIdx vendor extension >> > RISC-V: Add support for literal instruction arguments >> > RISC-V: Add T-Head MemPair vendor extension >> >> There are three minor issues, >> >> 1. Probably need to add new extension support in >> riscv_multi_subset_supports_ext, although it is just used for >> reporting better error messages. >> > > OK, will do. > > >> 2. The operand L seems only to be used for t-head for now, so it >> should be still a vendor operand, named with the X prefix probably >> better. >> > > You mean Xl (additionally to Xs and Xu)? > > >> 3. I remember Lifang mentioned before that we should add these vendor >> stuff based on the vendor infra in the integration branch, and that's >> what I asked him to rebase his patches to there before, since the >> previous policy cannot accept vendor stuff on master branch. But now >> I think most of us agree to accept t-head extensions on mainline >> directly, so I figured these things cannot be blocked by the vendor >> infra and cannot be committed. That doesn't mean we don't need the >> vendor infra, that means we can support the vendor infra later if me >> or someone have time to move them back to mainline. >> >> Therefore, these patches look good to me for now, thank you very much >> for spending so much time to implement these. But personally, I think >> we should get the approval from the T-Head guys at least. Btw, If >> these implementations are referred to and based on the integration >> branch, then I think it would be better to keep at least the >> co-authors there in the commit message here; if these patches are >> re-write without referring to the implementation from the integration >> branch, then I need to apologize to them, because I asked them to >> rewrite their patches over there, and cannot be committed to mainline >> at that time... >> > > The patches were written from scratch. > Note, that before writing this series, we (T-Head and Vrull) worked > together > on grouping the instructions into individual extensions (and dropping less > important parts like the vendor-specific CSRs). > I'll add a Co-developed-by to the Xs/Xu patch as this was Lifang's idea. > Also note, that the patches have been reviewed by T-Head (Lifang) > before sending them to the list. > > >> >> > riscv: gas: Add command line option '-mcpu=' to specify the CPU >> > riscv: Add T-Head entries for the -mcpu= flag >> >> Not sure if it is necessary to add -mcpu in assembler, since the >> compiler should recognize -mcpu, and will expand it to the correct >> extensions to assembler. If there are no objections for a period of >> time, then please go ahead and commit these. >> > > I won't be able to push as I don't have write access. > I'll send a v2 with the requested changes. > > Thank you for the review! > > >> >> Thank you very much >> Nelson >> >> > bfd/elfxx-riscv.c | 39 ++- >> > gas/config/tc-riscv.c | 127 +++++++ >> > gas/doc/c-riscv.texi | 70 ++++ >> > gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 + >> > gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 + >> > gas/testsuite/gas/riscv/mcpu-ok-c906.d | 6 + >> > gas/testsuite/gas/riscv/mcpu-ok-c910.d | 6 + >> > gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + >> > gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + >> > gas/testsuite/gas/riscv/x-thead-ba.d | 13 + >> > gas/testsuite/gas/riscv/x-thead-ba.s | 6 + >> > gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + >> > gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + >> > gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ >> > gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ >> > gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + >> > gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + >> > gas/testsuite/gas/riscv/x-thead-bs.d | 14 + >> > gas/testsuite/gas/riscv/x-thead-bs.s | 6 + >> > gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ >> > gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ >> > gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ >> > gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ >> > gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + >> > gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + >> > .../gas/riscv/x-thead-fmemidx-fail.d | 3 + >> > .../gas/riscv/x-thead-fmemidx-fail.l | 18 + >> > .../gas/riscv/x-thead-fmemidx-fail.s | 17 + >> > gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ >> > gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + >> > gas/testsuite/gas/riscv/x-thead-mac.d | 15 + >> > gas/testsuite/gas/riscv/x-thead-mac.s | 7 + >> > gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + >> > gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + >> > gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ >> > gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ >> > .../gas/riscv/x-thead-mempair-fail.d | 3 + >> > .../gas/riscv/x-thead-mempair-fail.l | 30 ++ >> > .../gas/riscv/x-thead-mempair-fail.s | 30 ++ >> > gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + >> > gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + >> > gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + >> > gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + >> > gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + >> > gas/testsuite/gas/riscv/x-thead-sync.d | 14 + >> > gas/testsuite/gas/riscv/x-thead-sync.s | 6 + >> > include/opcode/riscv-opc.h | 326 ++++++++++++++++++ >> > include/opcode/riscv.h | 27 ++ >> > opcodes/riscv-dis.c | 44 +++ >> > opcodes/riscv-opc.c | 155 +++++++++ >> > 55 files changed, 1394 insertions(+), 2 deletions(-) >> > create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d >> > create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l >> > create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c906.d >> > create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c910.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d >> > create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s >> > >> > -- >> > 2.37.2 >> > >> >