From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 08D743858D3C for ; Wed, 22 Mar 2023 16:01:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 08D743858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x532.google.com with SMTP id y4so75047213edo.2 for ; Wed, 22 Mar 2023 09:01:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1679500890; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=W4MiWTL9ZE0rxqaCkxzyZeqbupwtmhUuFBU6xpJsoxk=; b=gUrJ7Qj1SjnoxSJInrkwmYUTRRGsrciXnHUGJle4gnVmEnFi/ZCFb6c2bjdZoYTJjF EhIW0NBV4GGNEstlGg/JQGLAFvo4wwk/4/hQ5X7sSCmETJIRi0njz552R2fVEnWpVt0l JOncEK6TI8o8Cd0KLqa/bJQu8GEzVBBalOS+8+FKZffalaN2hJLrYAKS8Lobtbw1oNM5 In4yif+cAZgRBeNjQrGHs00kmGRhCA+gsC+p6v4FzuD1aXiGyG+eox0kr87vZndbiYKe XpdS9Fpp4JBsHDr8buXbxmwRGt1wDPfqedd1873ayehqjsBo1wGD8EWEED2rppOd06Ua eINQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679500890; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W4MiWTL9ZE0rxqaCkxzyZeqbupwtmhUuFBU6xpJsoxk=; b=5y9USZXzPBgjbg3BehnyZHx99PGtx+i1/4oro3g9K3Svwz3jKmX60QttCDOwEJp8Ga qsMT/+AgOoQKSxXoU3s+apdV1xEWQTCY5HlZu6jgSWsLNHdE+q6wPOjnII42+UmSvvgs g+mtdSPAjNkOav6w0V3uSZ1MMh5xre795P5WTOg+W1sGGJLzS/6DUEfO4x2qp9sx5Ijg TnDNbBcWw0ZRNW0oz6aL/ucf20xgbQB1Ao2t8A39bykDMPOzwpRWGhKB5cP9q6285h1F aaoSI1vmNS6aNNhrR+3wgYwxGrjAkJ+oRKa+6yLZDdnnWbH6HKD5NMXunthzeJ8phvZD srow== X-Gm-Message-State: AO0yUKWLgdkvl9NeZxBY5E94TjLv+BgiIQSnCJDK50IY5b6MuS0uk5Zu ok5fJ2H3m8ejQKSex94KRburAMwnwcaKaYyDX08ykiH6FoKLzfdIBCVfH9oN X-Google-Smtp-Source: AK7set+4nfA+tOqoGKRwca4E2fBOOjQyJXbsdQCge4nTae+TZO5mbuEDezCMbFPXOUKLsrNtePYlXUAMEQV0G87QTAs= X-Received: by 2002:a17:906:9bfa:b0:930:af80:5ba6 with SMTP id de58-20020a1709069bfa00b00930af805ba6mr3432542ejc.1.1679500889424; Wed, 22 Mar 2023 09:01:29 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Philipp Tomsich Date: Thu, 23 Mar 2023 00:01:16 +0800 Message-ID: Subject: Re: [REVIEW ONLY 1/1] UNRATIFIED RISC-V: Add 'Zfa' extension To: =?UTF-8?Q?Christoph_M=C3=BCllner?= Cc: Tsukasa OI , binutils@sourceware.org, Andrew Waterman Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 22 Mar 2023 at 23:47, Christoph M=C3=BCllner wrote: > > On Sun, Sep 18, 2022 at 12:13=E2=80=AFPM Tsukasa OI via Binutils > wrote: > > > > [DO NOT MERGE] > > Until 'Zfa' extension is frozen/ratified and final version number is > > determined, this patch should not merged upstream. This commit uses > > unratified version 0.1 as in documentation (instead of possible 1.0 > > after ratification). > > > > This commit adds the 'Zfa' extension (its instructions and new operand > > type for FLI instructions). > > > > This is based on: > > > > (latest commit of the 'zfb' branch as of this writing) > > > > Note: the author is calling FLI instructions' RS1 encoded field as > > "value". It must be reviewed before the specification is frozen. > > > > bfd/ChangeLog: > > > > * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction > > class support for 'Zfa' extension. > > (riscv_multi_subset_supports_ext): Likewise. > > (riscv_implicit_subsets): Add 'Zfa' -> 'F' dependency. > > > > gas/ChangeLog: > > > > * testsuite/gas/riscv/zfa.s: New test. > > * testsuite/gas/riscv/zfa.d: Likewise. > > * testsuite/gas/riscv/zfa-32.s: New test. > > * testsuite/gas/riscv/zfa-32.d: Likewise. > > * testsuite/gas/riscv/zfa-64.s: New test. > > * testsuite/gas/riscv/zfa-64.d: Likewise. > > * testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s: New failure test = for > > the "fcvtmod.w.d" instruction. > > * testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d: Likewise. > > * testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l: Likewise. > > * testsuite/gas/riscv/zfa-fail-fli.s: New failure test for "fli= " > > instructions. > > * testsuite/gas/riscv/zfa-fail-fli.d: Likewise. > > * testsuite/gas/riscv/zfa-fail-fli.l: Likewise. > > > > include/ChangeLog: > > > > * opcode/riscv-opc.h (MATCH_FLI_H, MASK_FLI_H, MATCH_FMINI_H, > > MASK_FMINI_H, MATCH_FMAXI_H, MASK_FMAXI_H, MATCH_FROUND_H, > > MASK_FROUND_H, MATCH_FROUNDNX_H, MASK_FROUNDNX_H, MATCH_FLTQ_H, > > MASK_FLTQ_H, MATCH_FLEQ_H, MASK_FLEQ_H, MATCH_FLI_S, MASK_FLI_S= , > > MATCH_FMINI_S, MASK_FMINI_S, MATCH_FMAXI_S, MASK_FMAXI_S, > > MATCH_FROUND_S, MASK_FROUND_S, MATCH_FROUNDNX_S, MASK_FROUNDNX_= S, > > MATCH_FLTQ_S, MASK_FLTQ_S, MATCH_FLEQ_S, MASK_FLEQ_S, MATCH_FLI= _D, > > MASK_FLI_D, MATCH_FMINI_D, MASK_FMINI_D, MATCH_FMAXI_D, > > MASK_FMAXI_D, MATCH_FROUND_D, MASK_FROUND_D, MATCH_FROUNDNX_D, > > MASK_FROUNDNX_D, MATCH_FLTQ_D, MASK_FLTQ_D, MATCH_FLEQ_D, > > MASK_FLEQ_D, MATCH_FLI_Q, MASK_FLI_Q, MATCH_FMINI_Q, MASK_FMINI= _Q, > > MATCH_FMAXI_Q, MASK_FMAXI_Q, MATCH_FROUND_Q, MASK_FROUND_Q, > > MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, MATCH_FLTQ_Q, MASK_FLTQ_Q, > > MATCH_FLEQ_Q, MASK_FLEQ_Q, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, > > MATCH_FMVH_X_D, MASK_FMVH_X_D, MATCH_FMVH_X_Q, MASK_FMVH_X_Q, > > MATCH_FMVP_D_X, MASK_FMVP_D_X, MATCH_FMVP_Q_X, MASK_FMVP_Q_X): = New. > > * opcode/riscv.h (enum riscv_insn_class): Add instruction > > classes for 'Zfa' extension. > > > > opcodes/ChangeLog: > > > > * riscv-opc.c (riscv_opcodes): Add 'Zfa' instructions. > > --- > > bfd/elfxx-riscv.c | 39 ++++++++ > > gas/config/tc-riscv.c | 21 ++++ > > gas/testsuite/gas/riscv/zfa-32.d | 10 ++ > > gas/testsuite/gas/riscv/zfa-32.s | 3 + > > gas/testsuite/gas/riscv/zfa-64.d | 10 ++ > > gas/testsuite/gas/riscv/zfa-64.s | 3 + > > .../gas/riscv/zfa-fail-fcvtmod.w.d.d | 3 + > > .../gas/riscv/zfa-fail-fcvtmod.w.d.l | 8 ++ > > .../gas/riscv/zfa-fail-fcvtmod.w.d.s | 11 +++ > > gas/testsuite/gas/riscv/zfa-fail-fli.d | 3 + > > gas/testsuite/gas/riscv/zfa-fail-fli.l | 21 ++++ > > gas/testsuite/gas/riscv/zfa-fail-fli.s | 21 ++++ > > gas/testsuite/gas/riscv/zfa.d | 93 +++++++++++++++++ > > gas/testsuite/gas/riscv/zfa.s | 92 +++++++++++++++++ > > include/opcode/riscv-opc.h | 99 +++++++++++++++++++ > > include/opcode/riscv.h | 5 + > > opcodes/riscv-dis.c | 7 ++ > > opcodes/riscv-opc.c | 52 +++++++++- > > 18 files changed, 500 insertions(+), 1 deletion(-) > > create mode 100644 gas/testsuite/gas/riscv/zfa-32.d > > create mode 100644 gas/testsuite/gas/riscv/zfa-32.s > > create mode 100644 gas/testsuite/gas/riscv/zfa-64.d > > create mode 100644 gas/testsuite/gas/riscv/zfa-64.s > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.d > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.l > > create mode 100644 gas/testsuite/gas/riscv/zfa-fail-fli.s > > create mode 100644 gas/testsuite/gas/riscv/zfa.d > > create mode 100644 gas/testsuite/gas/riscv/zfa.s > > > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > > index e03b312a381..1c6d1505d54 100644 > > --- a/bfd/elfxx-riscv.c > > +++ b/bfd/elfxx-riscv.c > > @@ -1073,6 +1073,7 @@ static struct riscv_implicit_subset riscv_implici= t_subsets[] =3D > > {"zvl256b", "zvl128b", check_implicit_always}, > > {"zvl128b", "zvl64b", check_implicit_always}, > > {"zvl64b", "zvl32b", check_implicit_always}, > > + {"zfa", "f", check_implicit_always}, > > {"d", "f", check_implicit_always}, > > {"zfh", "zfhmin", check_implicit_always}, > > {"zfhmin", "f", check_implicit_always}, > > @@ -1162,6 +1163,7 @@ static struct riscv_supported_ext riscv_supported= _std_z_ext[] =3D > > {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, > > {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, > > {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > + {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, > > {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > @@ -2334,6 +2336,17 @@ riscv_multi_subset_supports (riscv_parse_subset_= t *rps, > > && riscv_subset_supports (rps, "q")) > > || (riscv_subset_supports (rps, "zhinxmin") > > && riscv_subset_supports (rps, "zqinx"))); > > + case INSN_CLASS_ZFA: > > + return riscv_subset_supports (rps, "zfa"); > > + case INSN_CLASS_D_AND_ZFA: > > + return riscv_subset_supports (rps, "d") > > + && riscv_subset_supports (rps, "zfa"); > > + case INSN_CLASS_Q_AND_ZFA: > > + return riscv_subset_supports (rps, "q") > > + && riscv_subset_supports (rps, "zfa"); > > + case INSN_CLASS_ZFH_AND_ZFA: > > + return riscv_subset_supports (rps, "zfh") > > + && riscv_subset_supports (rps, "zfa"); > > case INSN_CLASS_ZBA: > > return riscv_subset_supports (rps, "zba"); > > case INSN_CLASS_ZBB: > > @@ -2469,6 +2482,32 @@ riscv_multi_subset_supports_ext (riscv_parse_sub= set_t *rps, > > return "zhinxmin"; > > else > > return _("zfhmin' and `q', or `zhinxmin' and `zqinx"); > > + case INSN_CLASS_ZFA: > > + return "zfa"; > > + case INSN_CLASS_D_AND_ZFA: > > + if (!riscv_subset_supports (rps, "d") > > + && !riscv_subset_supports (rps, "zfa")) > > + return _("d' and `zfa"); > > + else if (!riscv_subset_supports (rps, "d")) > > + return "d"; > > + else > > + return "zfa"; > > + case INSN_CLASS_Q_AND_ZFA: > > + if (!riscv_subset_supports (rps, "q") > > + && !riscv_subset_supports (rps, "zfa")) > > + return _("q' and `zfa"); > > + else if (!riscv_subset_supports (rps, "q")) > > + return "q"; > > + else > > + return "zfa"; > > + case INSN_CLASS_ZFH_AND_ZFA: > > + if (!riscv_subset_supports (rps, "zfh") > > + && !riscv_subset_supports (rps, "zfa")) > > + return _("zfh' and `zfa"); > > + else if (!riscv_subset_supports (rps, "zfh")) > > + return "zfh"; > > + else > > + return "zfa"; > > case INSN_CLASS_ZBA: > > return "zba"; > > case INSN_CLASS_ZBB: > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > > index 2f5ee18e451..ffbc7fbdda2 100644 > > --- a/gas/config/tc-riscv.c > > +++ b/gas/config/tc-riscv.c > > @@ -1208,6 +1208,7 @@ validate_riscv_insn (const struct riscv_opcode *o= pc, int length) > > case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; > > case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; > > case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; > > + case 'i': /* RS1, FLI.[HSDQ] value field. */ > > case 'Z': /* RS1, CSR number. */ > > case 'S': /* RS1, floating point. */ > > case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; > > @@ -3262,6 +3263,26 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, e= xpressionS *imm_expr, > > asarg =3D expr_end; > > continue; > > > > + case 'i': /* FLI.[HSDQ] constant immediate. */ > > + if (arg_lookup (&asarg, riscv_fli_value, > > + ARRAY_SIZE (riscv_fli_value), ®no)) > > + INSERT_OPERAND (RS1, *ip, regno); > > + else > > + { > > + if (my_getSmallExpression (imm_expr, imm_reloc, asarg= , p) > > + || imm_expr->X_op !=3D O_constant) > > + break; > > + if (imm_expr->X_add_number < 0 > > + || imm_expr->X_add_number > 29) > > + as_bad (_ ("improper fli value field (%ld), " > > + "value must be 0...29 or min, inf or nan= "), > > + (long) imm_expr->X_add_number); > > + INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); > > + imm_expr->X_op =3D O_absent; > > + asarg =3D expr_end; > > + } > > + continue; > > + > > default: > > unknown_riscv_ip_operand: > > as_fatal (_("internal: unknown argument type `%s'"), > > diff --git a/gas/testsuite/gas/riscv/zfa-32.d b/gas/testsuite/gas/riscv= /zfa-32.d > > new file mode 100644 > > index 00000000000..0f0cbfcdc70 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-32.d > > @@ -0,0 +1,10 @@ > > +#as: -march=3Drv32id_zfa > > +#objdump: -dr > > + > > +.*:[ ]+file format .* > > + > > +Disassembly of section .text: > > + > > +0+000 : > > +[ ]+[0-9a-f]+:[ ]+e2108553[ ]+fmvh\.x\.d[ ]+a0,ft1 > > +[ ]+[0-9a-f]+:[ ]+b2b500d3[ ]+fmvp\.d\.x[ ]+ft1,a0,a1 > > diff --git a/gas/testsuite/gas/riscv/zfa-32.s b/gas/testsuite/gas/riscv= /zfa-32.s > > new file mode 100644 > > index 00000000000..da95441cdc7 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-32.s > > @@ -0,0 +1,3 @@ > > +target: > > + fmvh.x.d a0, ft1 > > + fmvp.d.x ft1, a0, a1 > > diff --git a/gas/testsuite/gas/riscv/zfa-64.d b/gas/testsuite/gas/riscv= /zfa-64.d > > new file mode 100644 > > index 00000000000..f942d616959 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-64.d > > @@ -0,0 +1,10 @@ > > +#as: -march=3Drv64iq_zfa > > +#objdump: -dr > > + > > +.*:[ ]+file format .* > > + > > +Disassembly of section .text: > > + > > +0+000 : > > +[ ]+[0-9a-f]+:[ ]+e6108553[ ]+fmvh\.x\.q[ ]+a0,ft1 > > +[ ]+[0-9a-f]+:[ ]+b6b500d3[ ]+fmvp\.q\.x[ ]+ft1,a0,a1 > > diff --git a/gas/testsuite/gas/riscv/zfa-64.s b/gas/testsuite/gas/riscv= /zfa-64.s > > new file mode 100644 > > index 00000000000..dc8129dae3e > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-64.s > > @@ -0,0 +1,3 @@ > > +target: > > + fmvh.x.q a0, ft1 > > + fmvp.q.x ft1, a0, a1 > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d b/gas/tests= uite/gas/riscv/zfa-fail-fcvtmod.w.d.d > > new file mode 100644 > > index 00000000000..5234c49de75 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.d > > @@ -0,0 +1,3 @@ > > +#as: -march=3Drv64id_zfa > > +#objdump: -dr > > +#error_output: zfa-fail-fcvtmod.w.d.l > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l b/gas/tests= uite/gas/riscv/zfa-fail-fcvtmod.w.d.l > > new file mode 100644 > > index 00000000000..4ea048a3356 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.l > > @@ -0,0 +1,8 @@ > > +.*: Assembler messages: > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rne' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rdn' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rup' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,rmm' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,dyn' > > +.*: Error: illegal operands `fcvtmod\.w\.d a0,ft1,invalid' > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s b/gas/tests= uite/gas/riscv/zfa-fail-fcvtmod.w.d.s > > new file mode 100644 > > index 00000000000..5984f6676d8 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fcvtmod.w.d.s > > @@ -0,0 +1,11 @@ > > +target: > > + # fcvtmod.w.d requires explicit rounding mode. > > + fcvtmod.w.d a0, ft1 > > + # Rounding mode other than rtz are reserved. > > + fcvtmod.w.d a0, ft1, rne > > + fcvtmod.w.d a0, ft1, rdn > > + fcvtmod.w.d a0, ft1, rup > > + fcvtmod.w.d a0, ft1, rmm > > + fcvtmod.w.d a0, ft1, dyn > > + # Invalid rounding mode is invalid. > > + fcvtmod.w.d a0, ft1, invalid > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fli.d b/gas/testsuite/gas= /riscv/zfa-fail-fli.d > > new file mode 100644 > > index 00000000000..3753a4d185e > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fli.d > > @@ -0,0 +1,3 @@ > > +#as: -march=3Drv64iq_zfa_zfh > > +#objdump: -dr > > +#error_output: zfa-fail-fli.l > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fli.l b/gas/testsuite/gas= /riscv/zfa-fail-fli.l > > new file mode 100644 > > index 00000000000..b7532f80fd4 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fli.l > > @@ -0,0 +1,21 @@ > > +.*: Assembler messages: > > +.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-1\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(-2\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(30\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: improper fli value field \(32\), value must be 0\.\.\.29 or= min, inf or nan > > +.*: Error: illegal operands `fli\.h ft1,invalid' > > +.*: Error: illegal operands `fli\.s ft1,invalid' > > +.*: Error: illegal operands `fli\.d ft1,invalid' > > +.*: Error: illegal operands `fli\.q ft1,invalid' > > diff --git a/gas/testsuite/gas/riscv/zfa-fail-fli.s b/gas/testsuite/gas= /riscv/zfa-fail-fli.s > > new file mode 100644 > > index 00000000000..4c600b5d578 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa-fail-fli.s > > @@ -0,0 +1,21 @@ > > +target: > > + fli.h ft1, -1 > > + fli.s ft1, -1 > > + fli.d ft1, -1 > > + fli.q ft1, -1 > > + fli.h ft1, -2 > > + fli.s ft1, -2 > > + fli.d ft1, -2 > > + fli.q ft1, -2 > > + fli.h ft1, 30 > > + fli.s ft1, 30 > > + fli.d ft1, 30 > > + fli.q ft1, 30 > > + fli.h ft1, 32 > > + fli.s ft1, 32 > > + fli.d ft1, 32 > > + fli.q ft1, 32 > > + fli.h ft1, invalid > > + fli.s ft1, invalid > > + fli.d ft1, invalid > > + fli.q ft1, invalid > > diff --git a/gas/testsuite/gas/riscv/zfa.d b/gas/testsuite/gas/riscv/zf= a.d > > new file mode 100644 > > index 00000000000..3701a41e485 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa.d > > @@ -0,0 +1,93 @@ > > +#as: -march=3Drv64iq_zfa_zfh > > +#objdump: -dr > > + > > +.*:[ ]+file format .* > > + > > +Disassembly of section .text: > > + > > +0+000 : > > Hi Tsukasa, > > There seems to be a misunderstanding of the spec. > The second operand of the fli should be the constant itself ("Value" > column of the specification) in C-like syntax. > E.g.: > fli.h ft1, -1.0 # encoding rs1=3D0 > fli.h ft1, min # encoding rs1=3D1 > fli.h ft1, 0.0000152587890625 # encoding rs1=3D2 > ... > fli.h ft1, 16 # encoding rs1=3D25 > ... > fli.h ft1, nan # encoding rs1=3D31 > > So we have 3 strings ("min", "inf", "nan") and 29 constants. Note that value #29 is not representable for fli.h (i.e., 65536.0 is not representable and will also encode +inf). So "fli.h ft1, 65536.0" should either be rejected or generate a warning. --Philipp. > > BR > Christoph > > > +[ ]+[0-9a-f]+:[ ]+f41000d3[ ]+fli\.h[ ]+ft1,0 > > +[ ]+[0-9a-f]+:[ ]+f41080d3[ ]+fli\.h[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f41100d3[ ]+fli\.h[ ]+ft1,2 > > +[ ]+[0-9a-f]+:[ ]+f41d80d3[ ]+fli\.h[ ]+ft1,2= 7 > > +[ ]+[0-9a-f]+:[ ]+f41e00d3[ ]+fli\.h[ ]+ft1,2= 8 > > +[ ]+[0-9a-f]+:[ ]+f41e80d3[ ]+fli\.h[ ]+ft1,2= 9 > > +[ ]+[0-9a-f]+:[ ]+f41080d3[ ]+fli\.h[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f41f00d3[ ]+fli\.h[ ]+ft1,i= nf > > +[ ]+[0-9a-f]+:[ ]+f41f80d3[ ]+fli\.h[ ]+ft1,n= an > > +[ ]+[0-9a-f]+:[ ]+f01000d3[ ]+fli\.s[ ]+ft1,0 > > +[ ]+[0-9a-f]+:[ ]+f01080d3[ ]+fli\.s[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f01100d3[ ]+fli\.s[ ]+ft1,2 > > +[ ]+[0-9a-f]+:[ ]+f01d80d3[ ]+fli\.s[ ]+ft1,2= 7 > > +[ ]+[0-9a-f]+:[ ]+f01e00d3[ ]+fli\.s[ ]+ft1,2= 8 > > +[ ]+[0-9a-f]+:[ ]+f01e80d3[ ]+fli\.s[ ]+ft1,2= 9 > > +[ ]+[0-9a-f]+:[ ]+f01080d3[ ]+fli\.s[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f01f00d3[ ]+fli\.s[ ]+ft1,i= nf > > +[ ]+[0-9a-f]+:[ ]+f01f80d3[ ]+fli\.s[ ]+ft1,n= an > > +[ ]+[0-9a-f]+:[ ]+f21000d3[ ]+fli\.d[ ]+ft1,0 > > +[ ]+[0-9a-f]+:[ ]+f21080d3[ ]+fli\.d[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f21100d3[ ]+fli\.d[ ]+ft1,2 > > +[ ]+[0-9a-f]+:[ ]+f21d80d3[ ]+fli\.d[ ]+ft1,2= 7 > > +[ ]+[0-9a-f]+:[ ]+f21e00d3[ ]+fli\.d[ ]+ft1,2= 8 > > +[ ]+[0-9a-f]+:[ ]+f21e80d3[ ]+fli\.d[ ]+ft1,2= 9 > > +[ ]+[0-9a-f]+:[ ]+f21080d3[ ]+fli\.d[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f21f00d3[ ]+fli\.d[ ]+ft1,i= nf > > +[ ]+[0-9a-f]+:[ ]+f21f80d3[ ]+fli\.d[ ]+ft1,n= an > > +[ ]+[0-9a-f]+:[ ]+f61000d3[ ]+fli\.q[ ]+ft1,0 > > +[ ]+[0-9a-f]+:[ ]+f61080d3[ ]+fli\.q[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f61100d3[ ]+fli\.q[ ]+ft1,2 > > +[ ]+[0-9a-f]+:[ ]+f61d80d3[ ]+fli\.q[ ]+ft1,2= 7 > > +[ ]+[0-9a-f]+:[ ]+f61e00d3[ ]+fli\.q[ ]+ft1,2= 8 > > +[ ]+[0-9a-f]+:[ ]+f61e80d3[ ]+fli\.q[ ]+ft1,2= 9 > > +[ ]+[0-9a-f]+:[ ]+f61080d3[ ]+fli\.q[ ]+ft1,m= in > > +[ ]+[0-9a-f]+:[ ]+f61f00d3[ ]+fli\.q[ ]+ft1,i= nf > > +[ ]+[0-9a-f]+:[ ]+f61f80d3[ ]+fli\.q[ ]+ft1,n= an > > +[ ]+[0-9a-f]+:[ ]+2c3100d3[ ]+fmin\.h[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2c3120d3[ ]+fmini\.h[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+283100d3[ ]+fmin\.s[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+283120d3[ ]+fmini\.s[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2a3100d3[ ]+fmin\.d[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2a3120d3[ ]+fmini\.d[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2e3100d3[ ]+fmin\.q[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2e3120d3[ ]+fmini\.q[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2c3110d3[ ]+fmax\.h[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2c3130d3[ ]+fmaxi\.h[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+283110d3[ ]+fmax\.s[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+283130d3[ ]+fmaxi\.s[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2a3110d3[ ]+fmax\.d[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2a3130d3[ ]+fmaxi\.d[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2e3110d3[ ]+fmax\.q[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+2e3130d3[ ]+fmaxi\.q[ ]+ft1,f= t2,ft3 > > +[ ]+[0-9a-f]+:[ ]+4445f553[ ]+fround\.h[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+44459553[ ]+fround\.h[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4045f553[ ]+fround\.s[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+40459553[ ]+fround\.s[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4245f553[ ]+fround\.d[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+42459553[ ]+fround\.d[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4645f553[ ]+fround\.q[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+46459553[ ]+fround\.q[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4455f553[ ]+froundnx\.h[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+44559553[ ]+froundnx\.h[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4055f553[ ]+froundnx\.s[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+40559553[ ]+froundnx\.s[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4255f553[ ]+froundnx\.d[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+42559553[ ]+froundnx\.d[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+4655f553[ ]+froundnx\.q[ ]+fa0,f= a1 > > +[ ]+[0-9a-f]+:[ ]+46559553[ ]+froundnx\.q[ ]+fa0,f= a1,rtz > > +[ ]+[0-9a-f]+:[ ]+c2809553[ ]+fcvtmod\.w\.d[ ]+a0,ft= 1,rtz > > +[ ]+[0-9a-f]+:[ ]+a4209553[ ]+flt\.h[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a420d553[ ]+fltq\.h[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a0209553[ ]+flt\.s[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a020d553[ ]+fltq\.s[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a2209553[ ]+flt\.d[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a220d553[ ]+fltq\.d[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a6209553[ ]+flt\.q[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a620d553[ ]+fltq\.q[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a4208553[ ]+fle\.h[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a420c553[ ]+fleq\.h[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a0208553[ ]+fle\.s[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a020c553[ ]+fleq\.s[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a2208553[ ]+fle\.d[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a220c553[ ]+fleq\.d[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a6208553[ ]+fle\.q[ ]+a0,ft= 1,ft2 > > +[ ]+[0-9a-f]+:[ ]+a620c553[ ]+fleq\.q[ ]+a0,ft= 1,ft2 > > diff --git a/gas/testsuite/gas/riscv/zfa.s b/gas/testsuite/gas/riscv/zf= a.s > > new file mode 100644 > > index 00000000000..fb79792bf10 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zfa.s > > @@ -0,0 +1,92 @@ > > +target: > > + # fli: test both decimal and symbol representations > > + # (0..29, min=3D=3D1, inf=3D=3D(30), nan=3D=3D(31)) > > + fli.h ft1, 0 > > + fli.h ft1, 1 > > + fli.h ft1, 2 > > + fli.h ft1, 27 > > + fli.h ft1, 28 > > + fli.h ft1, 29 > > + fli.h ft1, min > > + fli.h ft1, inf > > + fli.h ft1, nan > > + fli.s ft1, 0 > > + fli.s ft1, 1 > > + fli.s ft1, 2 > > + fli.s ft1, 27 > > + fli.s ft1, 28 > > + fli.s ft1, 29 > > + fli.s ft1, min > > + fli.s ft1, inf > > + fli.s ft1, nan > > + fli.d ft1, 0 > > + fli.d ft1, 1 > > + fli.d ft1, 2 > > + fli.d ft1, 27 > > + fli.d ft1, 28 > > + fli.d ft1, 29 > > + fli.d ft1, min > > + fli.d ft1, inf > > + fli.d ft1, nan > > + fli.q ft1, 0 > > + fli.q ft1, 1 > > + fli.q ft1, 2 > > + fli.q ft1, 27 > > + fli.q ft1, 28 > > + fli.q ft1, 29 > > + fli.q ft1, min > > + fli.q ft1, inf > > + fli.q ft1, nan > > + # fmini/fmaxi (Zfa): same as fmin/fmax (Zfh/F/D/Q) except bit 1= 3 set > > + fmin.h ft1, ft2, ft3 > > + fmini.h ft1, ft2, ft3 > > + fmin.s ft1, ft2, ft3 > > + fmini.s ft1, ft2, ft3 > > + fmin.d ft1, ft2, ft3 > > + fmini.d ft1, ft2, ft3 > > + fmin.q ft1, ft2, ft3 > > + fmini.q ft1, ft2, ft3 > > + fmax.h ft1, ft2, ft3 > > + fmaxi.h ft1, ft2, ft3 > > + fmax.s ft1, ft2, ft3 > > + fmaxi.s ft1, ft2, ft3 > > + fmax.d ft1, ft2, ft3 > > + fmaxi.d ft1, ft2, ft3 > > + fmax.q ft1, ft2, ft3 > > + fmaxi.q ft1, ft2, ft3 > > + # fround/froundnx > > + fround.h fa0, fa1 > > + fround.h fa0, fa1, rtz > > + fround.s fa0, fa1 > > + fround.s fa0, fa1, rtz > > + fround.d fa0, fa1 > > + fround.d fa0, fa1, rtz > > + fround.q fa0, fa1 > > + fround.q fa0, fa1, rtz > > + froundnx.h fa0, fa1 > > + froundnx.h fa0, fa1, rtz > > + froundnx.s fa0, fa1 > > + froundnx.s fa0, fa1, rtz > > + froundnx.d fa0, fa1 > > + froundnx.d fa0, fa1, rtz > > + froundnx.q fa0, fa1 > > + froundnx.q fa0, fa1, rtz > > + # fcvtmod.w.d > > + fcvtmod.w.d a0, ft1, rtz > > + # fltq/fleq (Zfa): same as flt/fle (Zfh/F/D/Q) except bit 14 se= t > > + flt.h a0, ft1, ft2 > > + fltq.h a0, ft1, ft2 > > + flt.s a0, ft1, ft2 > > + fltq.s a0, ft1, ft2 > > + flt.d a0, ft1, ft2 > > + fltq.d a0, ft1, ft2 > > + flt.q a0, ft1, ft2 > > + fltq.q a0, ft1, ft2 > > + fle.h a0, ft1, ft2 > > + fleq.h a0, ft1, ft2 > > + fle.s a0, ft1, ft2 > > + fleq.s a0, ft1, ft2 > > + fle.d a0, ft1, ft2 > > + fleq.d a0, ft1, ft2 > > + fle.q a0, ft1, ft2 > > + fleq.q a0, ft1, ft2 > > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > > index 88b8d7ff595..9739ad24538 100644 > > --- a/include/opcode/riscv-opc.h > > +++ b/include/opcode/riscv-opc.h > > @@ -419,6 +419,72 @@ > > #define MASK_FCVT_Q_L 0xfff0007f > > #define MATCH_FCVT_Q_LU 0xd6300053 > > #define MASK_FCVT_Q_LU 0xfff0007f > > +#define MATCH_FLI_H 0xf4100053 > > +#define MASK_FLI_H 0xfff0707f > > +#define MATCH_FMINI_H 0x2c002053 > > +#define MASK_FMINI_H 0xfe00707f > > +#define MATCH_FMAXI_H 0x2c003053 > > +#define MASK_FMAXI_H 0xfe00707f > > +#define MATCH_FROUND_H 0x44400053 > > +#define MASK_FROUND_H 0xfff0007f > > +#define MATCH_FROUNDNX_H 0x44500053 > > +#define MASK_FROUNDNX_H 0xfff0007f > > +#define MATCH_FLTQ_H 0xa4005053 > > +#define MASK_FLTQ_H 0xfe00707f > > +#define MATCH_FLEQ_H 0xa4004053 > > +#define MASK_FLEQ_H 0xfe00707f > > +#define MATCH_FLI_S 0xf0100053 > > +#define MASK_FLI_S 0xfff0707f > > +#define MATCH_FMINI_S 0x28002053 > > +#define MASK_FMINI_S 0xfe00707f > > +#define MATCH_FMAXI_S 0x28003053 > > +#define MASK_FMAXI_S 0xfe00707f > > +#define MATCH_FROUND_S 0x40400053 > > +#define MASK_FROUND_S 0xfff0007f > > +#define MATCH_FROUNDNX_S 0x40500053 > > +#define MASK_FROUNDNX_S 0xfff0007f > > +#define MATCH_FLTQ_S 0xa0005053 > > +#define MASK_FLTQ_S 0xfe00707f > > +#define MATCH_FLEQ_S 0xa0004053 > > +#define MASK_FLEQ_S 0xfe00707f > > +#define MATCH_FLI_D 0xf2100053 > > +#define MASK_FLI_D 0xfff0707f > > +#define MATCH_FMINI_D 0x2a002053 > > +#define MASK_FMINI_D 0xfe00707f > > +#define MATCH_FMAXI_D 0x2a003053 > > +#define MASK_FMAXI_D 0xfe00707f > > +#define MATCH_FROUND_D 0x42400053 > > +#define MASK_FROUND_D 0xfff0007f > > +#define MATCH_FROUNDNX_D 0x42500053 > > +#define MASK_FROUNDNX_D 0xfff0007f > > +#define MATCH_FLTQ_D 0xa2005053 > > +#define MASK_FLTQ_D 0xfe00707f > > +#define MATCH_FLEQ_D 0xa2004053 > > +#define MASK_FLEQ_D 0xfe00707f > > +#define MATCH_FLI_Q 0xf6100053 > > +#define MASK_FLI_Q 0xfff0707f > > +#define MATCH_FMINI_Q 0x2e002053 > > +#define MASK_FMINI_Q 0xfe00707f > > +#define MATCH_FMAXI_Q 0x2e003053 > > +#define MASK_FMAXI_Q 0xfe00707f > > +#define MATCH_FROUND_Q 0x46400053 > > +#define MASK_FROUND_Q 0xfff0007f > > +#define MATCH_FROUNDNX_Q 0x46500053 > > +#define MASK_FROUNDNX_Q 0xfff0007f > > +#define MATCH_FLTQ_Q 0xa6005053 > > +#define MASK_FLTQ_Q 0xfe00707f > > +#define MATCH_FLEQ_Q 0xa6004053 > > +#define MASK_FLEQ_Q 0xfe00707f > > +#define MATCH_FCVTMOD_W_D 0xc2801053 > > +#define MASK_FCVTMOD_W_D 0xfff0707f > > +#define MATCH_FMVH_X_D 0xe2100053 > > +#define MASK_FMVH_X_D 0xfff0707f > > +#define MATCH_FMVH_X_Q 0xe6100053 > > +#define MASK_FMVH_X_Q 0xfff0707f > > +#define MATCH_FMVP_D_X 0xb2000053 > > +#define MASK_FMVP_D_X 0xfe00707f > > +#define MATCH_FMVP_Q_X 0xb6000053 > > +#define MASK_FMVP_Q_X 0xfe00707f > > #define MATCH_CLZ 0x60001013 > > #define MASK_CLZ 0xfff0707f > > #define MATCH_CTZ 0x60101013 > > @@ -2718,6 +2784,39 @@ DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT= _Q_W) > > DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) > > DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) > > DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) > > +DECLARE_INSN(fli_h, MATCH_FLI_H, MASK_FLI_H) > > +DECLARE_INSN(fmini_h, MATCH_FMINI_H, MASK_FMINI_H) > > +DECLARE_INSN(fmaxi_h, MATCH_FMAXI_H, MASK_FMAXI_H) > > +DECLARE_INSN(fround_h, MATCH_FROUND_H, MASK_FROUND_H) > > +DECLARE_INSN(fround_nx_h, MATCH_FROUNDNX_H, MASK_FROUNDNX_H) > > +DECLARE_INSN(fltq_h, MATCH_FLTQ_H, MASK_FLTQ_H) > > +DECLARE_INSN(fleq_h, MATCH_FLEQ_H, MASK_FLEQ_H) > > +DECLARE_INSN(fli_s, MATCH_FLI_S, MASK_FLI_S) > > +DECLARE_INSN(fmini_s, MATCH_FMINI_S, MASK_FMINI_S) > > +DECLARE_INSN(fmaxi_s, MATCH_FMAXI_S, MASK_FMAXI_S) > > +DECLARE_INSN(fround_s, MATCH_FROUND_S, MASK_FROUND_S) > > +DECLARE_INSN(fround_nx_s, MATCH_FROUNDNX_S, MASK_FROUNDNX_S) > > +DECLARE_INSN(fltq_s, MATCH_FLTQ_S, MASK_FLTQ_S) > > +DECLARE_INSN(fleq_s, MATCH_FLEQ_S, MASK_FLEQ_S) > > +DECLARE_INSN(fli_d, MATCH_FLI_D, MASK_FLI_D) > > +DECLARE_INSN(fmini_d, MATCH_FMINI_D, MASK_FMINI_D) > > +DECLARE_INSN(fmaxi_d, MATCH_FMAXI_D, MASK_FMAXI_D) > > +DECLARE_INSN(fround_d, MATCH_FROUND_D, MASK_FROUND_D) > > +DECLARE_INSN(fround_nx_d, MATCH_FROUNDNX_D, MASK_FROUNDNX_D) > > +DECLARE_INSN(fltq_d, MATCH_FLTQ_D, MASK_FLTQ_D) > > +DECLARE_INSN(fleq_d, MATCH_FLEQ_D, MASK_FLEQ_D) > > +DECLARE_INSN(fli_q, MATCH_FLI_Q, MASK_FLI_Q) > > +DECLARE_INSN(fmini_q, MATCH_FMINI_Q, MASK_FMINI_Q) > > +DECLARE_INSN(fmaxi_q, MATCH_FMAXI_Q, MASK_FMAXI_Q) > > +DECLARE_INSN(fround_q, MATCH_FROUND_Q, MASK_FROUND_Q) > > +DECLARE_INSN(fround_nx_q, MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q) > > +DECLARE_INSN(fltq_q, MATCH_FLTQ_Q, MASK_FLTQ_Q) > > +DECLARE_INSN(fleq_q, MATCH_FLEQ_Q, MASK_FLEQ_Q) > > +DECLARE_INSN(fcvtmod_w_d, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D) > > +DECLARE_INSN(fmvh_x_d, MATCH_FMVH_X_D, MASK_FMVH_X_D) > > +DECLARE_INSN(fmvh_x_q, MATCH_FMVH_X_Q, MASK_FMVH_X_Q) > > +DECLARE_INSN(fmvp_d_x, MATCH_FMVP_D_X, MASK_FMVP_D_X) > > +DECLARE_INSN(fmvp_q_x, MATCH_FMVP_Q_X, MASK_FMVP_Q_X) > > DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) > > DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) > > DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) > > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > > index f1dabeaab8e..3e9feaac2a7 100644 > > --- a/include/opcode/riscv.h > > +++ b/include/opcode/riscv.h > > @@ -376,6 +376,10 @@ enum riscv_insn_class > > INSN_CLASS_ZFHMIN_OR_ZHINXMIN, > > INSN_CLASS_ZFHMIN_AND_D, > > INSN_CLASS_ZFHMIN_AND_Q, > > + INSN_CLASS_ZFA, > > + INSN_CLASS_D_AND_ZFA, > > + INSN_CLASS_Q_AND_ZFA, > > + INSN_CLASS_ZFH_AND_ZFA, > > INSN_CLASS_ZBA, > > INSN_CLASS_ZBB, > > INSN_CLASS_ZBC, > > @@ -528,6 +532,7 @@ extern const char * const riscv_vsew[8]; > > extern const char * const riscv_vlmul[8]; > > extern const char * const riscv_vta[2]; > > extern const char * const riscv_vma[2]; > > +extern const char * const riscv_fli_value[32]; > > > > extern const struct riscv_opcode riscv_opcodes[]; > > extern const struct riscv_opcode riscv_insn_types[]; > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > > index 7ae6e709290..7a8be52281f 100644 > > --- a/opcodes/riscv-dis.c > > +++ b/opcodes/riscv-dis.c > > @@ -563,6 +563,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_= vma pc, disassemble_info *info > > print (info->stream, dis_style_text, "%d", rs1); > > break; > > > > + case 'i': > > + if (riscv_fli_value[rs1]) > > + print (info->stream, dis_style_text, "%s", riscv_fli_value[= rs1]); > > + else > > + print (info->stream, dis_style_immediate, "%d", rs1); > > + break; > > + > > default: > > /* xgettext:c-format */ > > print (info->stream, dis_style_text, > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 79be78eb367..eb4da1a7485 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -97,6 +97,15 @@ const char * const riscv_vma[2] =3D > > "mu", "ma" > > }; > > > > +/* The FLI.[HSDQ] value constants. */ > > +const char * const riscv_fli_value[32] =3D > > +{ > > + NULL, "min", NULL, NULL, NULL, NULL, NULL, NULL, > > + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, > > + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, > > + NULL, NULL, NULL, NULL, NULL, NULL, "inf", "nan", > > +}; > > + > > /* The order of overloaded instructions matters. Label arguments and > > register arguments look the same. Instructions that can have either > > for arguments must apear in the correct order in this table for the > > @@ -636,6 +645,15 @@ const struct riscv_opcode riscv_opcodes[] =3D > > {"fcvt.h.l", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H= _L, MASK_FCVT_H_L, match_opcode, 0 }, > > {"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s", MATCH_FCVT_H= _LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX, "D,s,m", MATCH_FCVT_H= _LU, MASK_FCVT_H_LU, match_opcode, 0 }, > > +{"fli.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,i", MATCH_FLI_H,= MASK_FLI_H, match_opcode, 0 }, > > +{"fmini.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMINI_= H, MASK_FMINI_H, match_opcode, 0 }, > > +{"fmaxi.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMAXI_= H, MASK_FMAXI_H, match_opcode, 0 }, > > +{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUND= _H|MASK_RM, MASK_FROUND_H|MASK_RM, match_opcode, 0 }, > > +{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND= _H, MASK_FROUND_H, match_opcode, 0 }, > > +{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUND= NX_H|MASK_RM, MASK_FROUNDNX_H|MASK_RM, match_opcode, 0 }, > > +{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND= NX_H, MASK_FROUNDNX_H, match_opcode, 0 }, > > +{"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H= , MASK_FLTQ_H, match_opcode, 0 }, > > +{"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H= , MASK_FLEQ_H, match_opcode, 0 }, > > > > /* Single-precision floating-point instruction subset. */ > > {"frcsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, M= ASK_FRCSR, match_opcode, INSN_ALIAS }, > > @@ -714,7 +732,16 @@ const struct riscv_opcode riscv_opcodes[] =3D > > {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L= , MASK_FCVT_S_L, match_opcode, 0 }, > > {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L= U|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L= U, MASK_FCVT_S_LU, match_opcode, 0 }, > > - > > +{"fli.s", 0, INSN_CLASS_ZFA, "D,i", MATCH_FLI_S, M= ASK_FLI_S, match_opcode, 0 }, > > +{"fmini.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMINI_S,= MASK_FMINI_S, match_opcode, 0 }, > > +{"fmaxi.s", 0, INSN_CLASS_ZFA, "D,S,T", MATCH_FMAXI_S,= MASK_FMAXI_S, match_opcode, 0 }, > > +{"fround.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUND_S= |MASK_RM, MASK_FROUND_S|MASK_RM, match_opcode, 0 }, > > +{"fround.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUND_S= , MASK_FROUND_S, match_opcode, 0 }, > > +{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUNDNX= _S|MASK_RM, MASK_FROUNDNX_S|MASK_RM, match_opcode, 0 }, > > +{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUNDNX= _S, MASK_FROUNDNX_S, match_opcode, 0 }, > > +{"fltq.s", 0, INSN_CLASS_ZFA, "d,S,T", MATCH_FLTQ_S, = MASK_FLTQ_S, match_opcode, 0 }, > > +{"fleq.s", 0, INSN_CLASS_ZFA, "d,S,T", MATCH_FLEQ_S, = MASK_FLEQ_S, match_opcode, 0 }, > > + > > /* Double-precision floating-point instruction subset. */ > > {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK= _C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, > > {"fld", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FLD, MASK_C= _FLD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, > > @@ -775,6 +802,18 @@ const struct riscv_opcode riscv_opcodes[] =3D > > {"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L= , MASK_FCVT_D_L, match_opcode, 0 }, > > {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L= U|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L= U, MASK_FCVT_D_LU, match_opcode, 0 }, > > +{"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,i", MATCH_FLI_D, M= ASK_FLI_D, match_opcode, 0 }, > > +{"fmini.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMINI_D,= MASK_FMINI_D, match_opcode, 0 }, > > +{"fmaxi.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,T", MATCH_FMAXI_D,= MASK_FMAXI_D, match_opcode, 0 }, > > +{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUND_D= |MASK_RM, MASK_FROUND_D|MASK_RM, match_opcode, 0 }, > > +{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUND_D= , MASK_FROUND_D, match_opcode, 0 }, > > +{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUNDNX= _D|MASK_RM, MASK_FROUNDNX_D|MASK_RM, match_opcode, 0 }, > > +{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUNDNX= _D, MASK_FROUNDNX_D, match_opcode, 0 }, > > +{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,m", MATCH_FCVTMOD_= W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, > > +{"fltq.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,T", MATCH_FLTQ_D, = MASK_FLTQ_D, match_opcode, 0 }, > > +{"fleq.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,T", MATCH_FLEQ_D, = MASK_FLEQ_D, match_opcode, 0 }, > > +{"fmvh.x.d", 32, INSN_CLASS_D_AND_ZFA, "d,S", MATCH_FMVH_X_D= , MASK_FMVH_X_D, match_opcode, 0}, > > +{"fmvp.d.x", 32, INSN_CLASS_D_AND_ZFA, "D,s,t", MATCH_FMVP_D_X= , MASK_FMVP_D_X, match_opcode, 0}, > > > > /* Quad-precision floating-point instruction subset. */ > > {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, ma= tch_opcode, INSN_DREF|INSN_16_BYTE }, > > @@ -833,6 +872,17 @@ const struct riscv_opcode riscv_opcodes[] =3D > > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L= , MASK_FCVT_Q_L, match_opcode, 0 }, > > {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L= U, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L= U, MASK_FCVT_Q_LU, match_opcode, 0 }, > > +{"fli.q", 0, INSN_CLASS_Q_AND_ZFA, "D,i", MATCH_FLI_Q, M= ASK_FLI_Q, match_opcode, 0 }, > > +{"fmini.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMINI_Q,= MASK_FMINI_Q, match_opcode, 0 }, > > +{"fmaxi.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMAXI_Q,= MASK_FMAXI_Q, match_opcode, 0 }, > > +{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUND_Q= |MASK_RM, MASK_FROUND_Q|MASK_RM, match_opcode, 0 }, > > +{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUND_Q= , MASK_FROUND_Q, match_opcode, 0 }, > > +{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUNDNX= _Q|MASK_RM, MASK_FROUNDNX_Q|MASK_RM, match_opcode, 0 }, > > +{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUNDNX= _Q, MASK_FROUNDNX_Q, match_opcode, 0 }, > > +{"fltq.q", 0, INSN_CLASS_Q_AND_ZFA, "d,S,T", MATCH_FLTQ_Q, = MASK_FLTQ_Q, match_opcode, 0 }, > > +{"fleq.q", 0, INSN_CLASS_Q_AND_ZFA, "d,S,T", MATCH_FLEQ_Q, = MASK_FLEQ_Q, match_opcode, 0 }, > > +{"fmvh.x.q", 64, INSN_CLASS_Q_AND_ZFA, "d,S", MATCH_FMVH_X_Q= , MASK_FMVH_X_Q, match_opcode, 0}, > > +{"fmvp.q.x", 64, INSN_CLASS_Q_AND_ZFA, "D,s,t", MATCH_FMVP_Q_X= , MASK_FMVP_Q_X, match_opcode, 0}, > > > > /* Compressed instructions. */ > > {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opco= de, 0 }, > > -- > > 2.34.1 > >