From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by sourceware.org (Postfix) with ESMTPS id 36CD63858D20 for ; Fri, 31 Mar 2023 08:31:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 36CD63858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52a.google.com with SMTP id w9so86676828edc.3 for ; Fri, 31 Mar 2023 01:31:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1680251460; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=trM09tFE9RUImDWo0gyz3e+M1CS51ByUG1kjKMHvKJ8=; b=UNH3/6pyTQ22BP+EL8pSsYyaCd61JfLohJ6MaYwPo624Tmt/o/vK0kFf2iaOeGYYFt jwuQ2qADD+HpLXZ7jYgEqgjquXRKx8KlYLH590/jNuwGVJ7TZrUR5J+vx5W5Y80WmcpF ZHM5W969Y4ocvMSZlolIjWs24+kbGk6K96mQ5346txsMjxfFlpNL7Z4TNQIpQ0/C7NXn r4iGjcz1iWHDIM8YKK+BQ4+AEjQ62j3HTJ+nQKYrASTekht6WBhhiEMlAXjtqG4RQeIg YVctSCY19Q6gTrmwseu5ACFI0rR71HLvdlZKFFJSmy2EJLHXNDXHFQNxBqphxT2NlZ5t 557w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680251460; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=trM09tFE9RUImDWo0gyz3e+M1CS51ByUG1kjKMHvKJ8=; b=fAhQLfEB/t02YTjZ3OOQ7ojHNfUlHowHwR6JLF+qv8Mty8teBx4maUsharVjlvnaKL Ch/JFcr+4I8sdj1YDwS9dvcFenXGRvvVLbx/bd01pbavbxiOqhKGw5A+v1JtHr4glveB zNROZY8dA10KmMNZx1gp25Ob4OfAcoz/GqiMeoSUU99Ow4xgw50cBzvad0RIDlWlb4sO INyfJT8nVLtfjAqw5o1kRfs2qdalB7u2SfGSvayAIEIeR/1lbJkgRwY4h14eT/eKQL2W M6MgDVhuKDnD9Mu+KOJWhBuWaR3Daq8uIWONB4HhweoZ8wN56oKW5kKITQ2NOCUVpUKF exTw== X-Gm-Message-State: AAQBX9dZiVI4lTc9crZu4I7LfGxYG74KOxU0wMEVoduN6ygW1XIyUcpK 4RGEZddeFttCYdascblU06LDBe8nsWFylKJEHwsCNt7/cq+NzDSF X-Google-Smtp-Source: AKy350bm2ktfmoKi8GKm5keWF3qMNjgotZwRSUTI8DdmbXYMKXVsr/GOb7uy0jEw9YAq7ZwvJRE8CG/atfJxaGxVuYw= X-Received: by 2002:a50:d69a:0:b0:501:d2fb:44bb with SMTP id r26-20020a50d69a000000b00501d2fb44bbmr12899267edi.5.1680251459641; Fri, 31 Mar 2023 01:30:59 -0700 (PDT) MIME-Version: 1.0 References: <20230330175438.107102-1-christoph.muellner@vrull.eu> <20230330175438.107102-2-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Fri, 31 Mar 2023 10:30:48 +0200 Message-ID: Subject: Re: [RFC PATCH v4 1/2] RISC-V: Allocate "various" operand type To: Nelson Chu Cc: Christoph Muellner , binutils@sourceware.org, Andrew Waterman , Palmer Dabbelt , Jim Wilson , Jan Beulich , Kito Cheng , Jeff Law , Tsukasa OI Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Applied to master, thanks! Philipp. On Fri, 31 Mar 2023 at 04:20, Nelson Chu wrote: > > Since I also don't know which operand name is better than W, and these > kinds of operand names are just used internally, so this patch is OK > to commit. > > Thanks > Nelson > > On Fri, Mar 31, 2023 at 1:54=E2=80=AFAM Christoph Muellner > wrote: > > > > From: Tsukasa OI > > > > This commit intends to move operands that require very special handling= or > > operand types that are so minor (e.g. only useful on a few instructions= ) > > under "W". I also intend this "W" to be "temporary" operand storage un= til > > we can find good two character (or less) operand type. > > > > In this commit, prefetch offset operand "f" for 'Zicbop' extension is m= oved > > to "Wif" because of its special handling (and allocating single charact= er > > "f" for this operand type seemed too much). > > > > Current expected allocation guideline is as follows: > > > > 1. 'W' > > 2. The most closely related single-letter extension in lowercase > > (strongly recommended but not mandatory) > > 3. Identify operand type > > > > The author currently plans to allocate following three-character operan= d > > types (for operands including instructions from unratified extensions). > > > > 1. "Wif" ('Zicbop': fetch offset) > > 2. "Wfv" (unratified 'Zfa': value operand from FLI.[HSDQ] instructions= ) > > 3. "Wfm" / "WfM" > > 'Zfh', 'F', 'D', 'Q': rounding modes "m" with special handling > > solely for widening conversion instructions. > > > > gas/ChangeLog: > > > > * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Move from > > "f" to "Wif". > > > > opcodes/ChangeLog: > > > > * riscv-dis.c (print_insn_args): Move from "f" to "Wif". > > * riscv-opc.c (riscv_opcodes): Reflect new operand type. > > --- > > gas/config/tc-riscv.c | 64 +++++++++++++++++++++++++++++++------------ > > opcodes/riscv-dis.c | 26 ++++++++++++++---- > > opcodes/riscv-opc.c | 6 ++-- > > 3 files changed, 71 insertions(+), 25 deletions(-) > > > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > > index 40550ba8d74..4eff07a6d4a 100644 > > --- a/gas/config/tc-riscv.c > > +++ b/gas/config/tc-riscv.c > > @@ -1362,7 +1362,6 @@ validate_riscv_insn (const struct riscv_opcode *o= pc, int length) > > case 'j': used_bits |=3D ENCODE_ITYPE_IMM (-1U); break; > > case 'a': used_bits |=3D ENCODE_JTYPE_IMM (-1U); break; > > case 'p': used_bits |=3D ENCODE_BTYPE_IMM (-1U); break; > > - case 'f': /* Fall through. */ > > case 'q': used_bits |=3D ENCODE_STYPE_IMM (-1U); break; > > case 'u': used_bits |=3D ENCODE_UTYPE_IMM (-1U); break; > > case 'z': break; /* Zero immediate. */ > > @@ -1389,6 +1388,21 @@ validate_riscv_insn (const struct riscv_opcode *= opc, int length) > > goto unknown_validate_operand; > > } > > break; > > + case 'W': /* Various operands. */ > > + switch (*++oparg) > > + { > > + case 'i': > > + switch (*++oparg) > > + { > > + case 'f': used_bits |=3D ENCODE_STYPE_IMM (-1U); break; > > + default: > > + goto unknown_validate_operand; > > + } > > + break; > > + default: > > + goto unknown_validate_operand; > > + } > > + break; > > case 'X': /* Integer immediate. */ > > { > > size_t n; > > @@ -3420,22 +3434,37 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, = expressionS *imm_expr, > > imm_expr->X_op =3D O_absent; > > continue; > > > > - case 'f': /* Prefetch offset, pseudo S-type but lower 5-bit= s zero. */ > > - if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > > - continue; > > - my_getExpression (imm_expr, asarg); > > - check_absolute_expr (ip, imm_expr, false); > > - if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > > - || imm_expr->X_add_number >=3D (signed) RISCV_IMM_REA= CH / 2 > > - || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH= / 2) > > - as_bad (_("improper prefetch offset (%ld)"), > > - (long) imm_expr->X_add_number); > > - ip->insn_opcode |=3D > > - ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & > > - ~ 0x1fU); > > - imm_expr->X_op =3D O_absent; > > - asarg =3D expr_parse_end; > > - continue; > > + case 'W': /* Various operands. */ > > + switch (*++oparg) > > + { > > + case 'i': > > + switch (*++oparg) > > + { > > + case 'f': > > + /* Prefetch offset for 'Zicbop' extension. > > + pseudo S-type but lower 5-bits zero. */ > > + if (riscv_handle_implicit_zero_offset (imm_expr, = asarg)) > > + continue; > > + my_getExpression (imm_expr, asarg); > > + check_absolute_expr (ip, imm_expr, false); > > + if (((unsigned) (imm_expr->X_add_number) & 0x1fU) > > + || imm_expr->X_add_number >=3D RISCV_IMM_REAC= H / 2 > > + || imm_expr->X_add_number < -RISCV_IMM_REACH = / 2) > > + as_bad (_ ("improper prefetch offset (%ld)"), > > + (long) imm_expr->X_add_number); > > + ip->insn_opcode |=3D ENCODE_STYPE_IMM ( > > + (unsigned) (imm_expr->X_add_number) & ~0x1fU)= ; > > + imm_expr->X_op =3D O_absent; > > + asarg =3D expr_parse_end; > > + continue; > > + default: > > + goto unknown_riscv_ip_operand; > > + } > > + break; > > + default: > > + goto unknown_riscv_ip_operand; > > + } > > + break; > > > > case 'X': /* Integer immediate. */ > > { > > @@ -3488,6 +3517,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, ex= pressionS *imm_expr, > > } > > } > > break; > > + > > default: > > unknown_riscv_ip_operand: > > as_fatal (_("internal: unknown argument type `%s'"), > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > > index f431124b423..3aaa45f419c 100644 > > --- a/opcodes/riscv-dis.c > > +++ b/opcodes/riscv-dis.c > > @@ -473,11 +473,6 @@ print_insn_args (const char *oparg, insn_t l, bfd_= vma pc, disassemble_info *info > > (int)EXTRACT_STYPE_IMM (l)); > > break; > > > > - case 'f': > > - print (info->stream, dis_style_address_offset, "%d", > > - (int)EXTRACT_STYPE_IMM (l)); > > - break; > > - > > case 'a': > > info->target =3D EXTRACT_JTYPE_IMM (l) + pc; > > (*info->print_address_func) (info->target, info); > > @@ -582,6 +577,27 @@ print_insn_args (const char *oparg, insn_t l, bfd_= vma pc, disassemble_info *info > > print (info->stream, dis_style_immediate, "%d", rs1); > > break; > > > > + case 'W': /* Various operands. */ > > + { > > + switch (*++oparg) > > + { > > + case 'i': > > + switch (*++oparg) > > + { > > + case 'f': > > + print (info->stream, dis_style_address_offset, "%d"= , > > + (int) EXTRACT_STYPE_IMM (l)); > > + break; > > + default: > > + goto undefined_modifier; > > + } > > + break; > > + default: > > + goto undefined_modifier; > > + } > > + } > > + break; > > + > > case 'X': /* Integer immediate. */ > > { > > size_t n; > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index f67375f10a9..d9d69cda548 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -313,9 +313,9 @@ const struct riscv_opcode riscv_opcodes[] =3D > > /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ > > > > /* Standard hints. */ > > -{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_P= REFETCH_I, match_opcode, 0 }, > > -{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_P= REFETCH_R, match_opcode, 0 }, > > -{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_P= REFETCH_W, match_opcode, 0 }, > > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_I, MASK= _PREFETCH_I, match_opcode, 0 }, > > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_R, MASK= _PREFETCH_R, match_opcode, 0 }, > > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "Wif(s)", MATCH_PREFETCH_W, MASK= _PREFETCH_W, match_opcode, 0 }, > > {"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE= , match_opcode, 0 }, > > > > /* Basic RVI instructions and aliases. */ > > -- > > 2.39.2 > >