From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by sourceware.org (Postfix) with ESMTPS id A48E43858D38 for ; Wed, 14 Jun 2023 04:27:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A48E43858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b3424edd5fso2746551fa.0 for ; Tue, 13 Jun 2023 21:27:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686716878; x=1689308878; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=mlPogMHcfoKrU0bahhk4AI/t/1fknGgTSNMS5k1D8cE=; b=QhDeUAsVr3tYXTL65EQGX1qjTL+4DTvBqzvZrzGZ0kDA41WoKYzlzxP/ycoTiJu93t pvMJePN5FVPoz9QzMHA5PUSz3Ya5MZul61aXDQ9QtkbJ/1Dq9837K79Lp7706wpUAEBX FQdgreyPQAGdk7vAsQVJZ6KWpweu2xwq4LhBrD/GWgj+gtCunLqG/Er/XVkso3arlBeJ srAYIVBJDF8WNXwBBybJLm4T5M9nE6Xh7jvjuga3UwpvLpLopBIiDAtgcvBMLzgK+lHO XfuQYaBCxpPEKZ0JxEOVJPCxLiDqyxThDq6CTEEMOkeQ3ezxH6OEU2yBMarxkzZavftD 9zyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686716878; x=1689308878; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mlPogMHcfoKrU0bahhk4AI/t/1fknGgTSNMS5k1D8cE=; b=ZRldMA0c/4xQBmnaEIzd6OOpCASvKmmIOxkkrsvnub1OAA987XjTGBMbMSX5jGZWZm Cc7othAFAeIzQPo9ureY0RmSycPY4a/sdWO+eTIHcQRIYPawi4zemAx8nAwbXYcu9IV1 ORzqS8YXAGl3dQfBF60n/yifIzbp/TCNJV5GqBqNJD3RfCDCPJen96+L3HN33o0tT7WL CLn6jSnRpvWlc/jzZhKH0u218rru7S+9MfM5qwkHJjmzZUcgZ8PW10//pJ9d3/+z7B30 gNAt+5MhTiJFn/GRGT8keaZj/mLXVTUfb6XoNr8uryPgLiIaxxUUVQVsltJjRwR9ao8O cs/Q== X-Gm-Message-State: AC+VfDxXJltDms5YVfRh+NF5MzSOlh4HdZgS28dr/rUxi+CSimQ1fbKA ehfscgDUUGlZ3jrIK0y50y5qkjC6i9umh0ENWmi8N3aehHE//g== X-Google-Smtp-Source: ACHHUZ6fESlP0nd4lvbADTcc2YIz9md/ZBE0auNnGTovPbJv6hsOuoBOUkaDY9gBtf+0a1613aXu8YJgkIaKShshBq8= X-Received: by 2002:a2e:9c5a:0:b0:2ac:82c1:5a3d with SMTP id t26-20020a2e9c5a000000b002ac82c15a3dmr5249162ljj.23.1686716877719; Tue, 13 Jun 2023 21:27:57 -0700 (PDT) MIME-Version: 1.0 References: <20230612083649.907511-1-chenfeiyang@loongson.cn> <4d7d191c-def8-2073-7926-6db37a2c7f64@xen0n.name> In-Reply-To: <4d7d191c-def8-2073-7926-6db37a2c7f64@xen0n.name> From: Feiyang Chen Date: Wed, 14 Jun 2023 12:27:45 +0800 Message-ID: Subject: Re: [PATCH] LoongArch: Add fcsr register names support To: WANG Xuerui Cc: Feiyang Chen , liuzhensong@loongson.cn, xuchenghua@loongson.cn, chenhuacai@loongson.cn, binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jun 13, 2023 at 5:49=E2=80=AFPM WANG Xuerui w= rote: > > > > On 2023/6/12 16:36, Feiyang Chen wrote: > > Add fcsr register names support for fcsr move instructions. > > "Support referring to FCSRs as $fcsrX" sounds clearer. Also you may > mention a bit more about the justification e.g. LLVM IAS compatibility > and/or correction of previous oversight (FCSRs aren't GPRs after all). > > > > > gas/ChangeLog: > > > > * config/tc-loongarch.c: > > (loongarch_fc_normal_name): New definition. > > (loongarch_single_float_opcodes): Modify `movgr2fcsr` and > > `movfcsr2gr`. > > > > include/ChangeLog: > > > > * opcode/loongarch.h (loongarch_fc_normal_name): New extern. > > > > opcodes/ChangeLog: > > > > * opcodes/loongarch-dis.c (loongarch_after_parse_args): Add > > fcsr register names support. > > * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg= _helper): > > Likewise. > > > > Signed-off-by: Feiyang Chen > > --- > > gas/config/tc-loongarch.c | 22 +++++++++++++++++++++- > > include/opcode/loongarch.h | 1 + > > opcodes/loongarch-dis.c | 16 +++++++++++++++- > > opcodes/loongarch-opc.c | 9 +++++++-- > > 4 files changed, 44 insertions(+), 4 deletions(-) > > We may have to add/tweak test cases for this. > > > > > diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c > > index c55d4ee234a..97971d76a57 100644 > > --- a/gas/config/tc-loongarch.c > > +++ b/gas/config/tc-loongarch.c > > @@ -223,6 +223,7 @@ md_parse_option (int c, const char *arg) > > > > static struct htab *r_htab =3D NULL; > > static struct htab *f_htab =3D NULL; > > +static struct htab *fc_htab =3D NULL; > > static struct htab *c_htab =3D NULL; > > static struct htab *cr_htab =3D NULL; > > static struct htab *v_htab =3D NULL; > > @@ -286,6 +287,18 @@ loongarch_after_parse_args () > > str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i = + 1), > > 0); > > > > + if (!fc_htab) > > + fc_htab =3D str_htab_create (), str_hash_insert (fc_htab, "", 0, = 0); > > + > > + for (i =3D 0; i < ARRAY_SIZE (loongarch_fc_normal_name); i++) > > + str_hash_insert (fc_htab, loongarch_fc_normal_name[i], (void *) (= i + 1), > > + 0); > > + > > + /* Add general purpose registers for backward compatibility. */ > > + for (i =3D 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) > > + str_hash_insert (fc_htab, loongarch_r_normal_name[i], (void *) (i= + 1), > > + 0); > > + > > if (!c_htab) > > c_htab =3D str_htab_create (), str_hash_insert (c_htab, "", 0, 0)= ; > > > > @@ -666,7 +679,14 @@ loongarch_args_parser_can_match_arg_helper (char e= sc_ch1, char esc_ch2, > > ret =3D imm - 1; > > break; > > case 'f': > > - imm =3D (intptr_t) str_hash_find (f_htab, arg); > > + switch (esc_ch2) > > + { > > + case 'c': > > + imm =3D (intptr_t) str_hash_find (fc_htab, arg); > > + break; > > + default: > > + imm =3D (intptr_t) str_hash_find (f_htab, arg); > > + } > > ip->match_now =3D 0 < imm; > > ret =3D imm - 1; > > break; > > diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h > > index 004bb6561ef..4ed273182c0 100644 > > --- a/include/opcode/loongarch.h > > +++ b/include/opcode/loongarch.h > > @@ -185,6 +185,7 @@ dec2 : [1-9][0-9]? > > extern const char *const loongarch_f_normal_name[32]; > > extern const char *const loongarch_f_lp64_name[32]; > > extern const char *const loongarch_f_lp64_name1[32]; > > + extern const char *const loongarch_fc_normal_name[4]; > > extern const char *const loongarch_c_normal_name[8]; > > extern const char *const loongarch_cr_normal_name[4]; > > extern const char *const loongarch_v_normal_name[32]; > > diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c > > index d064d30d553..0e7d9a88c25 100644 > > --- a/opcodes/loongarch-dis.c > > +++ b/opcodes/loongarch-dis.c > > @@ -61,6 +61,7 @@ get_loongarch_opcode_by_binfmt (insn_t insn) > > > > static const char *const *loongarch_r_disname =3D NULL; > > static const char *const *loongarch_f_disname =3D NULL; > > +static const char *const *loongarch_fc_disname =3D NULL; > > static const char *const *loongarch_c_disname =3D NULL; > > static const char *const *loongarch_cr_disname =3D NULL; > > static const char *const *loongarch_v_disname =3D NULL; > > @@ -78,6 +79,7 @@ set_default_loongarch_dis_options (void) > > > > loongarch_r_disname =3D loongarch_r_lp64_name; > > loongarch_f_disname =3D loongarch_f_lp64_name; > > + loongarch_fc_disname =3D loongarch_fc_normal_name; > > loongarch_c_disname =3D loongarch_c_normal_name; > > loongarch_cr_disname =3D loongarch_cr_normal_name; > > loongarch_v_disname =3D loongarch_v_normal_name; > > @@ -142,7 +144,19 @@ dis_one_arg (char esc1, char esc2, const char *bit= _field, > > info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_i= mm]); > > break; > > case 'f': > > - info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_im= m]); > > + switch (esc2) > > + { > > + case 'c': > > + if (u_imm < 4) > > + info->fprintf_func (info->stream, "%s", loongarch_fc_disname[= u_imm]); > > + else > > + /* For backward compatibility. Display using general purpose > > + register names if out of range. */ > > + info->fprintf_func (info->stream, "%s", loongarch_r_normal_na= me[u_imm]); > > I don't think it's proper to call *any* of the FCSRs "GPR" (or actually, > aliases to FCSR0, but that doesn't matter). What concrete scenario are > you trying to keep compatible with? A test case may explain it. > I agree with you, but the previous method of decoding treated "fcsr" as "gr." Therefore, to ensure proper compilation of the possible old code, I also need to consider "gr" as "fcsr." If you have a better solution, please inform me. For example, we may encounter the instruction "movgr2fcsr $r0, $r0," and it is essential to parse it correctly. On another note, I am not experienced in creating test cases. Could you please assist me with that? > > + break; > > + default: > > + info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_i= mm]); > > + } > > break; > > case 'c': > > switch (esc2) > > diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c > > index 573b691c1fd..99fbe318fd3 100644 > > --- a/opcodes/loongarch-opc.c > > +++ b/opcodes/loongarch-opc.c > > @@ -77,6 +77,11 @@ const char *const loongarch_f_lp64_name1[32] =3D > > "", "", "", "", "", "", "", "", "", "", "", "", "", "", "",= "", > > }; > > > > +const char *const loongarch_fc_normal_name[4] =3D > > +{ > > + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3", > > +}; > > + > > const char *const loongarch_c_normal_name[8] =3D > > { > > "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fc= c7", > > @@ -459,8 +464,8 @@ static struct loongarch_opcode loongarch_single_flo= at_opcodes[] =3D > > { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", = 0, 0, 0, 0 }, > > { 0x0114b400, 0xfffffc00, "movfr2gr.s", "r0:5,f5:5", = 0, 0, 0, 0 }, > > { 0x0114bc00, 0xfffffc00, "movfrh2gr.s", "r0:5,f5:5", = 0, 0, 0, 0 }, > > - { 0x0114c000, 0xfffffc00, "movgr2fcsr", "r0:5,r5:5", = 0, 0, 0, 0 }, > > - { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,r5:5", = 0, 0, 0, 0 }, > > + { 0x0114c000, 0xfffffc00, "movgr2fcsr", "fc0:5,r5:5", = 0, 0, 0, 0 }, > > + { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,fc5:5", = 0, 0, 0, 0 }, > > { 0x0114d000, 0xfffffc18, "movfr2cf", "c0:3,f5:5", = 0, 0, 0, 0 }, > > { 0x0114d400, 0xffffff00, "movcf2fr", "f0:5,c5:3", = 0, 0, 0, 0 }, > > { 0x0114d800, 0xfffffc18, "movgr2cf", "c0:3,r5:5", = 0, 0, 0, 0 },