From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92a.google.com (mail-ua1-x92a.google.com [IPv6:2607:f8b0:4864:20::92a]) by sourceware.org (Postfix) with ESMTPS id 8EA7F3858C52 for ; Thu, 21 Sep 2023 05:32:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8EA7F3858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bluewhale.systems Authentication-Results: sourceware.org; spf=none smtp.mailfrom=bluewhale.systems Received: by mail-ua1-x92a.google.com with SMTP id a1e0cc1a2514c-7ab68ef45e7so3073241.3 for ; Wed, 20 Sep 2023 22:32:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bluewhale-systems.20230601.gappssmtp.com; s=20230601; t=1695274369; x=1695879169; darn=sourceware.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=nTiZwupUwz926P7wDu8gYeSZMgJQpv+tbWqUR29vyiI=; b=vHfb53aqSTQsg8NW2ZHs1Bxk9y1B51zVSC9O7y6Tpf8DacZ+bB+Zq6NCSY+fBn4YXz tE0QBWfiny598/nwqObnTFMC3o4WFU86cR/+nVk/rb1U15O0TqB7hyJDUW9jENaXBwxg 8KWIc2yjWmy/IYHhHbsuQDMGcCcT2UciqsbVtowvcdqBUhVIxbnL45OxLK2uQoJgbyYG t4IQNRKksRazDpprTVZJWdtRly7OkpYqtwkfvsH+abqkVaCvo1KNf1JGG55/he5tcvPU EO5CktJiZPy0heRQC7rcsp5CQboVVTlG198XHPNVdKPnT2ZDtvNp+gpHWnyMCgmLm2ca CGMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695274369; x=1695879169; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nTiZwupUwz926P7wDu8gYeSZMgJQpv+tbWqUR29vyiI=; b=JpUvQFbJTQf/JyL3Q/StwWVVDyOKgUprVfWUQhG5fP/zFFt6GgfPl1sKJhVM4ZEHGp tXhFzA8PAWFKFrEitAN2bN9pX22pZ+SjtNdVZkb0gPGLZJQqAKtk4MWCfXjB/Ius2GKm VVwSdQBst+3a9Ym9oBY3g7YdOSCoNvxktNaWz630ZTtXEJRK7uSNHRWsDypDprTsOxxq LxoFGLhJabBIorC951AWhAvhDIZ3CPq11xjWhKChUIEabfp14cF/EIMfD4hwzfr3FCQX EMoQjOHkUtfmCvUOqaYj5ZZsT069VL6WvLtcv5HLo/vnfoR0xSs3ZEGhm0FgWbFdlTt4 oKdw== X-Gm-Message-State: AOJu0YxX5i7vNI6TnqdEzXdEMRFMf8HWhu4Y1xr4PyBDga0srafxmsd3 J9zCRXX3zv2WmzvKZeNOOaPzhjqegjm8wAts4sU= X-Google-Smtp-Source: AGHT+IEYL7b7nZrOpFUAnyc6G/aPG/ZrUKl5JZHehjDSi4LqifPmdYgmUJEnJdtCVrwFec5qDB7gaiD9uutC4gjoh5k= X-Received: by 2002:a1f:4f46:0:b0:48f:c2d6:630c with SMTP id d67-20020a1f4f46000000b0048fc2d6630cmr3414692vkb.1.1695274368778; Wed, 20 Sep 2023 22:32:48 -0700 (PDT) MIME-Version: 1.0 References: <20230920083124.2072273-1-ruiu@bluewhale.systems> In-Reply-To: From: Rui Ueyama Date: Thu, 21 Sep 2023 14:32:37 +0900 Message-ID: Subject: Re: [PATCH v2] RISC-V: emit R_RISCV_RELAX for the la pseudo instruction To: Nelson Chu Cc: Rui Ueyama , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Thank you for reviewing! I'll let you know when you can merge this patch (i.e. when my proposal is ratified.) Meanwhile, do I need to fill in the copyright assignment form? On Thu, Sep 21, 2023 at 9:19=E2=80=AFAM Nelson Chu wr= ote: > > Looks good, thanks! > > Nelson > > On Wed, Sep 20, 2023 at 4:34=E2=80=AFPM Rui Ueyama wro= te: >> >> Now the macro identifier is stored to tc_fix_data if a relocation >> is created as a result of assembler macro expansion. >> >> >> --- >> gas/config/tc-riscv.c | 15 +++++++++++++++ >> gas/config/tc-riscv.h | 8 ++++++++ >> gas/testsuite/gas/riscv/la-variants.d | 3 +++ >> 3 files changed, 26 insertions(+) >> >> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c >> index 3b520ad208b..c761b793afc 100644 >> --- a/gas/config/tc-riscv.c >> +++ b/gas/config/tc-riscv.c >> @@ -59,6 +59,9 @@ struct riscv_cl_insn >> fixS *fixp; >> }; >> >> +/* The identifier of the assembler macro we are expanding, if any. */ >> +static int source_macro =3D -1; >> + >> /* All RISC-V CSR belong to one of these classes. */ >> enum riscv_csr_class >> { >> @@ -1659,6 +1662,7 @@ append_insn (struct riscv_cl_insn *ip, expressionS= *address_expr, >> address_expr, false, reloc_type); >> >> ip->fixp->fx_tcbit =3D riscv_opts.relax; >> + ip->fixp->tc_fix_data.source_macro =3D source_macro; >> } >> } >> >> @@ -2020,6 +2024,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_= expr, >> int rs2 =3D (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; >> int mask =3D ip->insn_mo->mask; >> >> + source_macro =3D mask; >> + >> switch (mask) >> { >> case M_LI: >> @@ -2168,6 +2174,8 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_= expr, >> as_bad (_("internal: macro %s not implemented"), ip->insn_mo->nam= e); >> break; >> } >> + >> + source_macro =3D -1; >> } >> >> static const struct percent_op_match percent_op_utype[] =3D >> @@ -4049,6 +4057,13 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg = ATTRIBUTE_UNUSED) >> break; >> >> case BFD_RELOC_RISCV_GOT_HI20: >> + /* R_RISCV_GOT_HI20 and the following R_RISCV_LO12_I are relaxabl= e >> + only if it is created as a result of la or lga assembler macros= . */ >> + if (fixP->tc_fix_data.source_macro =3D=3D M_LA || >> + fixP->tc_fix_data.source_macro =3D=3D M_LGA) >> + relaxable =3D true; >> + break; >> + >> case BFD_RELOC_RISCV_ADD8: >> case BFD_RELOC_RISCV_ADD16: >> case BFD_RELOC_RISCV_ADD32: >> diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h >> index 0c70c7d4739..4fba3a07829 100644 >> --- a/gas/config/tc-riscv.h >> +++ b/gas/config/tc-riscv.h >> @@ -101,6 +101,14 @@ extern void riscv_pre_output_hook (void); >> #define TC_FORCE_RELOCATION_LOCAL(FIX) 1 >> #define DIFF_EXPR_OK 1 >> >> +struct riscv_fix >> +{ >> + int source_macro; >> +}; >> + >> +#define TC_FIX_TYPE struct riscv_fix >> +#define TC_INIT_FIX_DATA(FIX) (FIX)->tc_fix_data.source_macro =3D -1 >> + >> extern void riscv_pop_insert (void); >> #define md_pop_insert() riscv_pop_insert () >> >> diff --git a/gas/testsuite/gas/riscv/la-variants.d b/gas/testsuite/gas/r= iscv/la-variants.d >> index b1d316983b7..e8ac09c2af2 100644 >> --- a/gas/testsuite/gas/riscv/la-variants.d >> +++ b/gas/testsuite/gas/riscv/la-variants.d >> @@ -21,11 +21,13 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+00000617[ ]+auipc[ ]+a2,0x0 >> [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a >> +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+(00062603|00063603)[ ]+(lw|ld)[ ]+a2,0\(= a2\).* >> [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ >> [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+00000697[ ]+auipc[ ]+a3,0x0 >> [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a >> +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+(0006a683|0006b683)[ ]+(lw|ld)[ ]+a3,0\(= a3\).* >> [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ >> [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> @@ -37,6 +39,7 @@ Disassembly of section .text: >> [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+00000797[ ]+auipc[ ]+a5,0x0 >> [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a >> +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> [ ]+[0-9a-f]+:[ ]+(0007a783|0007b783)[ ]+(lw|ld)[ ]+a5,0\(= a5\).* >> [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ >> [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* >> -- >> 2.34.1 >>