From 135b9617d7cbd9a523ae4336bb00d7a469c942b2 Mon Sep 17 00:00:00 2001 From: David Guillen Fandos Date: Wed, 30 Nov 2022 22:14:09 +0100 Subject: [PATCH] MIPS: Add allegrex CPU and its basic instructions (plus tests) --- bfd/archures.c | 1 + bfd/bfd-in2.h | 1 + bfd/cpu-mips.c | 2 + bfd/elfxx-mips.c | 8 + binutils/readelf.c | 1 + gas/config/tc-mips.c | 7 +- gas/testsuite/gas/mips/allegrex.d | 36 +++ gas/testsuite/gas/mips/allegrex.s | 30 ++ gas/testsuite/gas/mips/allegrex@c0.d | 265 ++++++++++++++++++ gas/testsuite/gas/mips/allegrex@c1.d | 265 ++++++++++++++++++ gas/testsuite/gas/mips/allegrex@cp0b.d | 5 + gas/testsuite/gas/mips/allegrex@cp0bl.d | 5 + gas/testsuite/gas/mips/allegrex@cp0c.d | 5 + gas/testsuite/gas/mips/allegrex@cp2d.d | 5 + gas/testsuite/gas/mips/allegrex@cp2m.d | 5 + .../gas/mips/allegrex@isa-override-1.d | 28 ++ .../gas/mips/allegrex@isa-override-1.s | 23 ++ .../gas/mips/allegrex@isa-override-2.d | 4 + .../gas/mips/allegrex@isa-override-2.l | 4 + gas/testsuite/gas/mips/allegrex@save-sub.d | 5 + gas/testsuite/gas/mips/mips.exp | 35 ++- include/elf/mips.h | 1 + include/opcode/mips.h | 6 + opcodes/mips-dis.c | 4 + opcodes/mips-opc.c | 119 ++++---- 25 files changed, 800 insertions(+), 70 deletions(-) create mode 100644 gas/testsuite/gas/mips/allegrex.d create mode 100644 gas/testsuite/gas/mips/allegrex.s create mode 100644 gas/testsuite/gas/mips/allegrex@c0.d create mode 100644 gas/testsuite/gas/mips/allegrex@c1.d create mode 100644 gas/testsuite/gas/mips/allegrex@cp0b.d create mode 100644 gas/testsuite/gas/mips/allegrex@cp0bl.d create mode 100644 gas/testsuite/gas/mips/allegrex@cp0c.d create mode 100644 gas/testsuite/gas/mips/allegrex@cp2d.d create mode 100644 gas/testsuite/gas/mips/allegrex@cp2m.d create mode 100644 gas/testsuite/gas/mips/allegrex@isa-override-1.d create mode 100644 gas/testsuite/gas/mips/allegrex@isa-override-1.s create mode 100644 gas/testsuite/gas/mips/allegrex@isa-override-2.d create mode 100644 gas/testsuite/gas/mips/allegrex@isa-override-2.l create mode 100644 gas/testsuite/gas/mips/allegrex@save-sub.d diff --git a/bfd/archures.c b/bfd/archures.c index e817bb0a44b..af87b83b7c7 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -173,6 +173,7 @@ DESCRIPTION .#define bfd_mach_mips16000 16000 .#define bfd_mach_mips16 16 .#define bfd_mach_mips5 5 +.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31 *} .#define bfd_mach_mips_loongson_2e 3001 .#define bfd_mach_mips_loongson_2f 3002 .#define bfd_mach_mips_gs464 3003 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 0b071dda1e5..9dbb7f62f49 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1508,6 +1508,7 @@ enum bfd_architecture #define bfd_mach_mips16000 16000 #define bfd_mach_mips16 16 #define bfd_mach_mips5 5 +#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31 */ #define bfd_mach_mips_loongson_2e 3001 #define bfd_mach_mips_loongson_2f 3002 #define bfd_mach_mips_gs464 3003 diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c index d9a7b6dffa9..d63d7e2704c 100644 --- a/bfd/cpu-mips.c +++ b/bfd/cpu-mips.c @@ -108,6 +108,7 @@ enum I_mipsocteon3, I_xlr, I_interaptiv_mr2, + I_allegrex, I_micromips }; @@ -163,6 +164,7 @@ static const bfd_arch_info_type arch_info_struct[] = N (64, 64, bfd_mach_mips_xlr, "mips:xlr", false, NN(I_xlr)), N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", false, NN(I_interaptiv_mr2)), + N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", false, NN(I_allegrex)), N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NULL) }; diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index 932167c15c6..47391c2a8b9 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -6980,6 +6980,9 @@ _bfd_elf_mips_mach (flagword flags) case E_MIPS_MACH_IAMR2: return bfd_mach_mips_interaptiv_mr2; + case E_MIPS_MACH_ALLEGREX: + return bfd_mach_mips_allegrex; + default: switch (flags & EF_MIPS_ARCH) { @@ -12340,6 +12343,10 @@ mips_set_isa_flags (bfd *abfd) val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR; break; + case bfd_mach_mips_allegrex: + val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX; + break; + case bfd_mach_mips_octeon2: val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2; break; @@ -14506,6 +14513,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = { bfd_mach_mips4000, bfd_mach_mips6000 }, { bfd_mach_mipsisa32, bfd_mach_mips6000 }, { bfd_mach_mips4010, bfd_mach_mips6000 }, + { bfd_mach_mips_allegrex, bfd_mach_mips6000 }, /* MIPS I extensions. */ { bfd_mach_mips6000, bfd_mach_mips3000 }, diff --git a/binutils/readelf.c b/binutils/readelf.c index 1bd6df9448a..b34be7adbea 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -4044,6 +4044,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break; + case E_MIPS_MACH_ALLEGREX: strcat(buf, ", allegrex"); break; case 0: /* We simply ignore the field in this case to avoid confusion: MIPS ELF does not specify EF_MIPS_MACH, it is a GNU diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 9abdf389aca..9cabeaf9add 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -437,6 +437,7 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS64R3 \ || (ISA) == ISA_MIPS64R5 \ || (ISA) == ISA_MIPS64R6 \ + || (CPU) == CPU_ALLEGREX \ || (CPU) == CPU_R5900) \ && ((CPU) != CPU_GS464 \ || (CPU) != CPU_GS464E \ @@ -525,7 +526,7 @@ static int mips_32bitmode = 0; #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) /* True if CPU has a ror instruction. */ -#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) +#define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) == CPU_ALLEGREX) /* True if CPU is in the Octeon family. */ #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ @@ -536,7 +537,7 @@ static int mips_32bitmode = 0; /* True, if CPU has support for ldc1 and sdc1. */ #define CPU_HAS_LDC1_SDC1(CPU) \ - ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) + ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900) && ((CPU) != CPU_ALLEGREX)) /* True if mflo and mfhi can be immediately followed by instructions which write to the HI and LO registers. @@ -561,6 +562,7 @@ static int mips_32bitmode = 0; || mips_opts.isa == ISA_MIPS64R3 \ || mips_opts.isa == ISA_MIPS64R5 \ || mips_opts.isa == ISA_MIPS64R6 \ + || mips_opts.arch == CPU_ALLEGREX \ || mips_opts.arch == CPU_R4010 \ || mips_opts.arch == CPU_R5900 \ || mips_opts.arch == CPU_R10000 \ @@ -20004,6 +20006,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* MIPS II */ { "r6000", 0, 0, ISA_MIPS2, CPU_R6000 }, + { "allegrex", 0, 0, ISA_MIPS2, CPU_ALLEGREX }, /* MIPS III */ { "r4000", 0, 0, ISA_MIPS3, CPU_R4000 }, diff --git a/gas/testsuite/gas/mips/allegrex.d b/gas/testsuite/gas/mips/allegrex.d new file mode 100644 index 00000000000..97e69857f67 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex.d @@ -0,0 +1,36 @@ +#as: -march=allegrex -mabi=32 +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: Sony Allegrex CPU tests + +.*: file format .* + + +Disassembly of section .text: +0x00000000 7ca43980 ext \$4,\$5,0x6,0x8 +0x00000004 7ca46984 ins \$4,\$5,0x6,0x8 +0x00000008 7c073c20 seb \$7,\$7 +0x0000000c 7c0a4420 seb \$8,\$10 +0x00000010 7c073e20 seh \$7,\$7 +0x00000014 7c0a4620 seh \$8,\$10 +0x00000018 0064100a movz \$2,\$3,\$4 +0x0000001c 0064100b movn \$2,\$3,\$4 +0x00000020 7c0738a0 wsbh \$7,\$7 +0x00000024 7c0a40a0 wsbh \$8,\$10 +0x00000028 7c0738e0 wsbw \$7,\$7 +0x0000002c 7c0a40e0 wsbw \$8,\$10 +0x00000030 7c073d20 bitrev \$7,\$7 +0x00000034 7c0a4520 bitrev \$8,\$10 +0x00000038 00402817 clo \$5,\$2 +0x0000003c 00801816 clz \$3,\$4 +0x00000040 0109001c madd \$8,\$9 +0x00000044 0109001d maddu \$8,\$9 +0x00000048 0109002e msub \$8,\$9 +0x0000004c 0109002f msubu \$8,\$9 +0x00000050 0109382d min \$7,\$8,\$9 +0x00000054 0109382c max \$7,\$8,\$9 +0x00000058 002acf02 ror \$25,\$10,0x1c +0x0000005c 002ac902 ror \$25,\$10,0x4 +0x00000060 0004c823 negu \$25,\$4 +0x00000064 032ac846 rorv \$25,\$10,\$25 +0x00000068 008ac846 rorv \$25,\$10,\$4 +0x0000006c 008ac846 rorv \$25,\$10,\$4 diff --git a/gas/testsuite/gas/mips/allegrex.s b/gas/testsuite/gas/mips/allegrex.s new file mode 100644 index 00000000000..b04fd36b042 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex.s @@ -0,0 +1,30 @@ + .text + .set noreorder + + ext $4, $5, 6, 8 + ins $4, $5, 6, 8 + seb $7 + seb $8, $10 + seh $7 + seh $8, $10 + movz $2, $3, $4 + movn $2, $3, $4 + wsbh $7 + wsbh $8, $10 + wsbw $7 + wsbw $8, $10 + bitrev $7 + bitrev $8, $10 + clo $5, $2 + clz $3, $4 + madd $8, $9 + maddu $8, $9 + msub $8, $9 + msubu $8, $9 + min $7, $8, $9 + max $7, $8, $9 + rotl $25, $10, 4 + rotr $25, $10, 4 + rotl $25, $10, $4 + rotr $25, $10, $4 + rotrv $25, $10, $4 diff --git a/gas/testsuite/gas/mips/allegrex@c0.d b/gas/testsuite/gas/mips/allegrex@c0.d new file mode 100644 index 00000000000..8e3ca43111b --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@c0.d @@ -0,0 +1,265 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS C0/COP0 instructions +#as: -32 +#source: c0.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 42000000 c0 0x0 +[0-9a-f]+ <[^>]*> 42000001 tlbr +[0-9a-f]+ <[^>]*> 42000002 tlbwi +[0-9a-f]+ <[^>]*> 42000003 c0 0x3 +[0-9a-f]+ <[^>]*> 42000004 c0 0x4 +[0-9a-f]+ <[^>]*> 42000005 c0 0x5 +[0-9a-f]+ <[^>]*> 42000006 tlbwr +[0-9a-f]+ <[^>]*> 42000007 c0 0x7 +[0-9a-f]+ <[^>]*> 42000008 tlbp +[0-9a-f]+ <[^>]*> 42000009 c0 0x9 +[0-9a-f]+ <[^>]*> 4200000a c0 0xa +[0-9a-f]+ <[^>]*> 4200000b c0 0xb +[0-9a-f]+ <[^>]*> 4200000c c0 0xc +[0-9a-f]+ <[^>]*> 4200000d c0 0xd +[0-9a-f]+ <[^>]*> 4200000e c0 0xe +[0-9a-f]+ <[^>]*> 4200000f c0 0xf +[0-9a-f]+ <[^>]*> 42000010 c0 0x10 +[0-9a-f]+ <[^>]*> 42000011 c0 0x11 +[0-9a-f]+ <[^>]*> 42000012 c0 0x12 +[0-9a-f]+ <[^>]*> 42000013 c0 0x13 +[0-9a-f]+ <[^>]*> 42000014 c0 0x14 +[0-9a-f]+ <[^>]*> 42000015 c0 0x15 +[0-9a-f]+ <[^>]*> 42000016 c0 0x16 +[0-9a-f]+ <[^>]*> 42000017 c0 0x17 +[0-9a-f]+ <[^>]*> 42000018 eret +[0-9a-f]+ <[^>]*> 42000019 c0 0x19 +[0-9a-f]+ <[^>]*> 4200001a c0 0x1a +[0-9a-f]+ <[^>]*> 4200001b c0 0x1b +[0-9a-f]+ <[^>]*> 4200001c c0 0x1c +[0-9a-f]+ <[^>]*> 4200001d c0 0x1d +[0-9a-f]+ <[^>]*> 4200001e c0 0x1e +[0-9a-f]+ <[^>]*> 4200001f c0 0x1f +[0-9a-f]+ <[^>]*> 42000020 c0 0x20 +[0-9a-f]+ <[^>]*> 42000021 c0 0x21 +[0-9a-f]+ <[^>]*> 42000022 c0 0x22 +[0-9a-f]+ <[^>]*> 42000023 c0 0x23 +[0-9a-f]+ <[^>]*> 42000024 c0 0x24 +[0-9a-f]+ <[^>]*> 42000025 c0 0x25 +[0-9a-f]+ <[^>]*> 42000026 c0 0x26 +[0-9a-f]+ <[^>]*> 42000027 c0 0x27 +[0-9a-f]+ <[^>]*> 42000028 c0 0x28 +[0-9a-f]+ <[^>]*> 42000029 c0 0x29 +[0-9a-f]+ <[^>]*> 4200002a c0 0x2a +[0-9a-f]+ <[^>]*> 4200002b c0 0x2b +[0-9a-f]+ <[^>]*> 4200002c c0 0x2c +[0-9a-f]+ <[^>]*> 4200002d c0 0x2d +[0-9a-f]+ <[^>]*> 4200002e c0 0x2e +[0-9a-f]+ <[^>]*> 4200002f c0 0x2f +[0-9a-f]+ <[^>]*> 42000030 c0 0x30 +[0-9a-f]+ <[^>]*> 42000031 c0 0x31 +[0-9a-f]+ <[^>]*> 42000032 c0 0x32 +[0-9a-f]+ <[^>]*> 42000033 c0 0x33 +[0-9a-f]+ <[^>]*> 42000034 c0 0x34 +[0-9a-f]+ <[^>]*> 42000035 c0 0x35 +[0-9a-f]+ <[^>]*> 42000036 c0 0x36 +[0-9a-f]+ <[^>]*> 42000037 c0 0x37 +[0-9a-f]+ <[^>]*> 42000038 c0 0x38 +[0-9a-f]+ <[^>]*> 42000039 c0 0x39 +[0-9a-f]+ <[^>]*> 4200003a c0 0x3a +[0-9a-f]+ <[^>]*> 4200003b c0 0x3b +[0-9a-f]+ <[^>]*> 4200003c c0 0x3c +[0-9a-f]+ <[^>]*> 4200003d c0 0x3d +[0-9a-f]+ <[^>]*> 4200003e c0 0x3e +[0-9a-f]+ <[^>]*> 4200003f c0 0x3f +[0-9a-f]+ <[^>]*> 43000000 c0 0x1000000 +[0-9a-f]+ <[^>]*> 43000001 c0 0x1000001 +[0-9a-f]+ <[^>]*> 43000002 c0 0x1000002 +[0-9a-f]+ <[^>]*> 43000003 c0 0x1000003 +[0-9a-f]+ <[^>]*> 43000004 c0 0x1000004 +[0-9a-f]+ <[^>]*> 43000005 c0 0x1000005 +[0-9a-f]+ <[^>]*> 43000006 c0 0x1000006 +[0-9a-f]+ <[^>]*> 43000007 c0 0x1000007 +[0-9a-f]+ <[^>]*> 43000008 c0 0x1000008 +[0-9a-f]+ <[^>]*> 43000009 c0 0x1000009 +[0-9a-f]+ <[^>]*> 4300000a c0 0x100000a +[0-9a-f]+ <[^>]*> 4300000b c0 0x100000b +[0-9a-f]+ <[^>]*> 4300000c c0 0x100000c +[0-9a-f]+ <[^>]*> 4300000d c0 0x100000d +[0-9a-f]+ <[^>]*> 4300000e c0 0x100000e +[0-9a-f]+ <[^>]*> 4300000f c0 0x100000f +[0-9a-f]+ <[^>]*> 43000010 c0 0x1000010 +[0-9a-f]+ <[^>]*> 43000011 c0 0x1000011 +[0-9a-f]+ <[^>]*> 43000012 c0 0x1000012 +[0-9a-f]+ <[^>]*> 43000013 c0 0x1000013 +[0-9a-f]+ <[^>]*> 43000014 c0 0x1000014 +[0-9a-f]+ <[^>]*> 43000015 c0 0x1000015 +[0-9a-f]+ <[^>]*> 43000016 c0 0x1000016 +[0-9a-f]+ <[^>]*> 43000017 c0 0x1000017 +[0-9a-f]+ <[^>]*> 43000018 c0 0x1000018 +[0-9a-f]+ <[^>]*> 43000019 c0 0x1000019 +[0-9a-f]+ <[^>]*> 4300001a c0 0x100001a +[0-9a-f]+ <[^>]*> 4300001b c0 0x100001b +[0-9a-f]+ <[^>]*> 4300001c c0 0x100001c +[0-9a-f]+ <[^>]*> 4300001d c0 0x100001d +[0-9a-f]+ <[^>]*> 4300001e c0 0x100001e +[0-9a-f]+ <[^>]*> 4300001f c0 0x100001f +[0-9a-f]+ <[^>]*> 43000020 c0 0x1000020 +[0-9a-f]+ <[^>]*> 43000021 c0 0x1000021 +[0-9a-f]+ <[^>]*> 43000022 c0 0x1000022 +[0-9a-f]+ <[^>]*> 43000023 c0 0x1000023 +[0-9a-f]+ <[^>]*> 43000024 c0 0x1000024 +[0-9a-f]+ <[^>]*> 43000025 c0 0x1000025 +[0-9a-f]+ <[^>]*> 43000026 c0 0x1000026 +[0-9a-f]+ <[^>]*> 43000027 c0 0x1000027 +[0-9a-f]+ <[^>]*> 43000028 c0 0x1000028 +[0-9a-f]+ <[^>]*> 43000029 c0 0x1000029 +[0-9a-f]+ <[^>]*> 4300002a c0 0x100002a +[0-9a-f]+ <[^>]*> 4300002b c0 0x100002b +[0-9a-f]+ <[^>]*> 4300002c c0 0x100002c +[0-9a-f]+ <[^>]*> 4300002d c0 0x100002d +[0-9a-f]+ <[^>]*> 4300002e c0 0x100002e +[0-9a-f]+ <[^>]*> 4300002f c0 0x100002f +[0-9a-f]+ <[^>]*> 43000030 c0 0x1000030 +[0-9a-f]+ <[^>]*> 43000031 c0 0x1000031 +[0-9a-f]+ <[^>]*> 43000032 c0 0x1000032 +[0-9a-f]+ <[^>]*> 43000033 c0 0x1000033 +[0-9a-f]+ <[^>]*> 43000034 c0 0x1000034 +[0-9a-f]+ <[^>]*> 43000035 c0 0x1000035 +[0-9a-f]+ <[^>]*> 43000036 c0 0x1000036 +[0-9a-f]+ <[^>]*> 43000037 c0 0x1000037 +[0-9a-f]+ <[^>]*> 43000038 c0 0x1000038 +[0-9a-f]+ <[^>]*> 43000039 c0 0x1000039 +[0-9a-f]+ <[^>]*> 4300003a c0 0x100003a +[0-9a-f]+ <[^>]*> 4300003b c0 0x100003b +[0-9a-f]+ <[^>]*> 4300003c c0 0x100003c +[0-9a-f]+ <[^>]*> 4300003d c0 0x100003d +[0-9a-f]+ <[^>]*> 4300003e c0 0x100003e +[0-9a-f]+ <[^>]*> 4300003f c0 0x100003f +[0-9a-f]+ <[^>]*> 42000000 c0 0x0 +[0-9a-f]+ <[^>]*> 42000001 tlbr +[0-9a-f]+ <[^>]*> 42000002 tlbwi +[0-9a-f]+ <[^>]*> 42000003 c0 0x3 +[0-9a-f]+ <[^>]*> 42000004 c0 0x4 +[0-9a-f]+ <[^>]*> 42000005 c0 0x5 +[0-9a-f]+ <[^>]*> 42000006 tlbwr +[0-9a-f]+ <[^>]*> 42000007 c0 0x7 +[0-9a-f]+ <[^>]*> 42000008 tlbp +[0-9a-f]+ <[^>]*> 42000009 c0 0x9 +[0-9a-f]+ <[^>]*> 4200000a c0 0xa +[0-9a-f]+ <[^>]*> 4200000b c0 0xb +[0-9a-f]+ <[^>]*> 4200000c c0 0xc +[0-9a-f]+ <[^>]*> 4200000d c0 0xd +[0-9a-f]+ <[^>]*> 4200000e c0 0xe +[0-9a-f]+ <[^>]*> 4200000f c0 0xf +[0-9a-f]+ <[^>]*> 42000010 c0 0x10 +[0-9a-f]+ <[^>]*> 42000011 c0 0x11 +[0-9a-f]+ <[^>]*> 42000012 c0 0x12 +[0-9a-f]+ <[^>]*> 42000013 c0 0x13 +[0-9a-f]+ <[^>]*> 42000014 c0 0x14 +[0-9a-f]+ <[^>]*> 42000015 c0 0x15 +[0-9a-f]+ <[^>]*> 42000016 c0 0x16 +[0-9a-f]+ <[^>]*> 42000017 c0 0x17 +[0-9a-f]+ <[^>]*> 42000018 eret +[0-9a-f]+ <[^>]*> 42000019 c0 0x19 +[0-9a-f]+ <[^>]*> 4200001a c0 0x1a +[0-9a-f]+ <[^>]*> 4200001b c0 0x1b +[0-9a-f]+ <[^>]*> 4200001c c0 0x1c +[0-9a-f]+ <[^>]*> 4200001d c0 0x1d +[0-9a-f]+ <[^>]*> 4200001e c0 0x1e +[0-9a-f]+ <[^>]*> 4200001f c0 0x1f +[0-9a-f]+ <[^>]*> 42000020 c0 0x20 +[0-9a-f]+ <[^>]*> 42000021 c0 0x21 +[0-9a-f]+ <[^>]*> 42000022 c0 0x22 +[0-9a-f]+ <[^>]*> 42000023 c0 0x23 +[0-9a-f]+ <[^>]*> 42000024 c0 0x24 +[0-9a-f]+ <[^>]*> 42000025 c0 0x25 +[0-9a-f]+ <[^>]*> 42000026 c0 0x26 +[0-9a-f]+ <[^>]*> 42000027 c0 0x27 +[0-9a-f]+ <[^>]*> 42000028 c0 0x28 +[0-9a-f]+ <[^>]*> 42000029 c0 0x29 +[0-9a-f]+ <[^>]*> 4200002a c0 0x2a +[0-9a-f]+ <[^>]*> 4200002b c0 0x2b +[0-9a-f]+ <[^>]*> 4200002c c0 0x2c +[0-9a-f]+ <[^>]*> 4200002d c0 0x2d +[0-9a-f]+ <[^>]*> 4200002e c0 0x2e +[0-9a-f]+ <[^>]*> 4200002f c0 0x2f +[0-9a-f]+ <[^>]*> 42000030 c0 0x30 +[0-9a-f]+ <[^>]*> 42000031 c0 0x31 +[0-9a-f]+ <[^>]*> 42000032 c0 0x32 +[0-9a-f]+ <[^>]*> 42000033 c0 0x33 +[0-9a-f]+ <[^>]*> 42000034 c0 0x34 +[0-9a-f]+ <[^>]*> 42000035 c0 0x35 +[0-9a-f]+ <[^>]*> 42000036 c0 0x36 +[0-9a-f]+ <[^>]*> 42000037 c0 0x37 +[0-9a-f]+ <[^>]*> 42000038 c0 0x38 +[0-9a-f]+ <[^>]*> 42000039 c0 0x39 +[0-9a-f]+ <[^>]*> 4200003a c0 0x3a +[0-9a-f]+ <[^>]*> 4200003b c0 0x3b +[0-9a-f]+ <[^>]*> 4200003c c0 0x3c +[0-9a-f]+ <[^>]*> 4200003d c0 0x3d +[0-9a-f]+ <[^>]*> 4200003e c0 0x3e +[0-9a-f]+ <[^>]*> 4200003f c0 0x3f +[0-9a-f]+ <[^>]*> 43000000 c0 0x1000000 +[0-9a-f]+ <[^>]*> 43000001 c0 0x1000001 +[0-9a-f]+ <[^>]*> 43000002 c0 0x1000002 +[0-9a-f]+ <[^>]*> 43000003 c0 0x1000003 +[0-9a-f]+ <[^>]*> 43000004 c0 0x1000004 +[0-9a-f]+ <[^>]*> 43000005 c0 0x1000005 +[0-9a-f]+ <[^>]*> 43000006 c0 0x1000006 +[0-9a-f]+ <[^>]*> 43000007 c0 0x1000007 +[0-9a-f]+ <[^>]*> 43000008 c0 0x1000008 +[0-9a-f]+ <[^>]*> 43000009 c0 0x1000009 +[0-9a-f]+ <[^>]*> 4300000a c0 0x100000a +[0-9a-f]+ <[^>]*> 4300000b c0 0x100000b +[0-9a-f]+ <[^>]*> 4300000c c0 0x100000c +[0-9a-f]+ <[^>]*> 4300000d c0 0x100000d +[0-9a-f]+ <[^>]*> 4300000e c0 0x100000e +[0-9a-f]+ <[^>]*> 4300000f c0 0x100000f +[0-9a-f]+ <[^>]*> 43000010 c0 0x1000010 +[0-9a-f]+ <[^>]*> 43000011 c0 0x1000011 +[0-9a-f]+ <[^>]*> 43000012 c0 0x1000012 +[0-9a-f]+ <[^>]*> 43000013 c0 0x1000013 +[0-9a-f]+ <[^>]*> 43000014 c0 0x1000014 +[0-9a-f]+ <[^>]*> 43000015 c0 0x1000015 +[0-9a-f]+ <[^>]*> 43000016 c0 0x1000016 +[0-9a-f]+ <[^>]*> 43000017 c0 0x1000017 +[0-9a-f]+ <[^>]*> 43000018 c0 0x1000018 +[0-9a-f]+ <[^>]*> 43000019 c0 0x1000019 +[0-9a-f]+ <[^>]*> 4300001a c0 0x100001a +[0-9a-f]+ <[^>]*> 4300001b c0 0x100001b +[0-9a-f]+ <[^>]*> 4300001c c0 0x100001c +[0-9a-f]+ <[^>]*> 4300001d c0 0x100001d +[0-9a-f]+ <[^>]*> 4300001e c0 0x100001e +[0-9a-f]+ <[^>]*> 4300001f c0 0x100001f +[0-9a-f]+ <[^>]*> 43000020 c0 0x1000020 +[0-9a-f]+ <[^>]*> 43000021 c0 0x1000021 +[0-9a-f]+ <[^>]*> 43000022 c0 0x1000022 +[0-9a-f]+ <[^>]*> 43000023 c0 0x1000023 +[0-9a-f]+ <[^>]*> 43000024 c0 0x1000024 +[0-9a-f]+ <[^>]*> 43000025 c0 0x1000025 +[0-9a-f]+ <[^>]*> 43000026 c0 0x1000026 +[0-9a-f]+ <[^>]*> 43000027 c0 0x1000027 +[0-9a-f]+ <[^>]*> 43000028 c0 0x1000028 +[0-9a-f]+ <[^>]*> 43000029 c0 0x1000029 +[0-9a-f]+ <[^>]*> 4300002a c0 0x100002a +[0-9a-f]+ <[^>]*> 4300002b c0 0x100002b +[0-9a-f]+ <[^>]*> 4300002c c0 0x100002c +[0-9a-f]+ <[^>]*> 4300002d c0 0x100002d +[0-9a-f]+ <[^>]*> 4300002e c0 0x100002e +[0-9a-f]+ <[^>]*> 4300002f c0 0x100002f +[0-9a-f]+ <[^>]*> 43000030 c0 0x1000030 +[0-9a-f]+ <[^>]*> 43000031 c0 0x1000031 +[0-9a-f]+ <[^>]*> 43000032 c0 0x1000032 +[0-9a-f]+ <[^>]*> 43000033 c0 0x1000033 +[0-9a-f]+ <[^>]*> 43000034 c0 0x1000034 +[0-9a-f]+ <[^>]*> 43000035 c0 0x1000035 +[0-9a-f]+ <[^>]*> 43000036 c0 0x1000036 +[0-9a-f]+ <[^>]*> 43000037 c0 0x1000037 +[0-9a-f]+ <[^>]*> 43000038 c0 0x1000038 +[0-9a-f]+ <[^>]*> 43000039 c0 0x1000039 +[0-9a-f]+ <[^>]*> 4300003a c0 0x100003a +[0-9a-f]+ <[^>]*> 4300003b c0 0x100003b +[0-9a-f]+ <[^>]*> 4300003c c0 0x100003c +[0-9a-f]+ <[^>]*> 4300003d c0 0x100003d +[0-9a-f]+ <[^>]*> 4300003e c0 0x100003e +[0-9a-f]+ <[^>]*> 4300003f c0 0x100003f + \.\.\. diff --git a/gas/testsuite/gas/mips/allegrex@c1.d b/gas/testsuite/gas/mips/allegrex@c1.d new file mode 100644 index 00000000000..9fbf8d38fe5 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@c1.d @@ -0,0 +1,265 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS C1/COP1 instructions +#as: -32 +#source: c1.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 46000000 add\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000001 sub\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000002 mul\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000003 div\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000004 sqrt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000005 abs\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000006 mov\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000007 neg\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000008 c1 0x8 +[0-9a-f]+ <[^>]*> 46000009 c1 0x9 +[0-9a-f]+ <[^>]*> 4600000a c1 0xa +[0-9a-f]+ <[^>]*> 4600000b c1 0xb +[0-9a-f]+ <[^>]*> 4600000c round\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000d trunc\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000e ceil\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000f floor\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000010 c1 0x10 +[0-9a-f]+ <[^>]*> 46000011 c1 0x11 +[0-9a-f]+ <[^>]*> 46000012 c1 0x12 +[0-9a-f]+ <[^>]*> 46000013 c1 0x13 +[0-9a-f]+ <[^>]*> 46000014 c1 0x14 +[0-9a-f]+ <[^>]*> 46000015 c1 0x15 +[0-9a-f]+ <[^>]*> 46000016 c1 0x16 +[0-9a-f]+ <[^>]*> 46000017 c1 0x17 +[0-9a-f]+ <[^>]*> 46000018 c1 0x18 +[0-9a-f]+ <[^>]*> 46000019 c1 0x19 +[0-9a-f]+ <[^>]*> 4600001a c1 0x1a +[0-9a-f]+ <[^>]*> 4600001b c1 0x1b +[0-9a-f]+ <[^>]*> 4600001c c1 0x1c +[0-9a-f]+ <[^>]*> 4600001d c1 0x1d +[0-9a-f]+ <[^>]*> 4600001e c1 0x1e +[0-9a-f]+ <[^>]*> 4600001f c1 0x1f +[0-9a-f]+ <[^>]*> 46000020 c1 0x20 +[0-9a-f]+ <[^>]*> 46000021 c1 0x21 +[0-9a-f]+ <[^>]*> 46000022 c1 0x22 +[0-9a-f]+ <[^>]*> 46000023 c1 0x23 +[0-9a-f]+ <[^>]*> 46000024 cvt\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000025 c1 0x25 +[0-9a-f]+ <[^>]*> 46000026 c1 0x26 +[0-9a-f]+ <[^>]*> 46000027 c1 0x27 +[0-9a-f]+ <[^>]*> 46000028 c1 0x28 +[0-9a-f]+ <[^>]*> 46000029 c1 0x29 +[0-9a-f]+ <[^>]*> 4600002a c1 0x2a +[0-9a-f]+ <[^>]*> 4600002b c1 0x2b +[0-9a-f]+ <[^>]*> 4600002c c1 0x2c +[0-9a-f]+ <[^>]*> 4600002d c1 0x2d +[0-9a-f]+ <[^>]*> 4600002e c1 0x2e +[0-9a-f]+ <[^>]*> 4600002f c1 0x2f +[0-9a-f]+ <[^>]*> 46000030 c\.f\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000031 c\.un\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000032 c\.eq\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000033 c\.ueq\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000034 c\.olt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000035 c\.ult\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000036 c\.ole\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000037 c\.ule\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000038 c\.sf\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000039 c\.ngle\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003a c\.seq\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003b c\.ngl\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003c c\.lt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003d c\.nge\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003e c\.le\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600003f c\.ngt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 47000000 c1 0x1000000 +[0-9a-f]+ <[^>]*> 47000001 c1 0x1000001 +[0-9a-f]+ <[^>]*> 47000002 c1 0x1000002 +[0-9a-f]+ <[^>]*> 47000003 c1 0x1000003 +[0-9a-f]+ <[^>]*> 47000004 c1 0x1000004 +[0-9a-f]+ <[^>]*> 47000005 c1 0x1000005 +[0-9a-f]+ <[^>]*> 47000006 c1 0x1000006 +[0-9a-f]+ <[^>]*> 47000007 c1 0x1000007 +[0-9a-f]+ <[^>]*> 47000008 c1 0x1000008 +[0-9a-f]+ <[^>]*> 47000009 c1 0x1000009 +[0-9a-f]+ <[^>]*> 4700000a c1 0x100000a +[0-9a-f]+ <[^>]*> 4700000b c1 0x100000b +[0-9a-f]+ <[^>]*> 4700000c c1 0x100000c +[0-9a-f]+ <[^>]*> 4700000d c1 0x100000d +[0-9a-f]+ <[^>]*> 4700000e c1 0x100000e +[0-9a-f]+ <[^>]*> 4700000f c1 0x100000f +[0-9a-f]+ <[^>]*> 47000010 c1 0x1000010 +[0-9a-f]+ <[^>]*> 47000011 c1 0x1000011 +[0-9a-f]+ <[^>]*> 47000012 c1 0x1000012 +[0-9a-f]+ <[^>]*> 47000013 c1 0x1000013 +[0-9a-f]+ <[^>]*> 47000014 c1 0x1000014 +[0-9a-f]+ <[^>]*> 47000015 c1 0x1000015 +[0-9a-f]+ <[^>]*> 47000016 c1 0x1000016 +[0-9a-f]+ <[^>]*> 47000017 c1 0x1000017 +[0-9a-f]+ <[^>]*> 47000018 c1 0x1000018 +[0-9a-f]+ <[^>]*> 47000019 c1 0x1000019 +[0-9a-f]+ <[^>]*> 4700001a c1 0x100001a +[0-9a-f]+ <[^>]*> 4700001b c1 0x100001b +[0-9a-f]+ <[^>]*> 4700001c c1 0x100001c +[0-9a-f]+ <[^>]*> 4700001d c1 0x100001d +[0-9a-f]+ <[^>]*> 4700001e c1 0x100001e +[0-9a-f]+ <[^>]*> 4700001f c1 0x100001f +[0-9a-f]+ <[^>]*> 47000020 c1 0x1000020 +[0-9a-f]+ <[^>]*> 47000021 c1 0x1000021 +[0-9a-f]+ <[^>]*> 47000022 c1 0x1000022 +[0-9a-f]+ <[^>]*> 47000023 c1 0x1000023 +[0-9a-f]+ <[^>]*> 47000024 c1 0x1000024 +[0-9a-f]+ <[^>]*> 47000025 c1 0x1000025 +[0-9a-f]+ <[^>]*> 47000026 c1 0x1000026 +[0-9a-f]+ <[^>]*> 47000027 c1 0x1000027 +[0-9a-f]+ <[^>]*> 47000028 c1 0x1000028 +[0-9a-f]+ <[^>]*> 47000029 c1 0x1000029 +[0-9a-f]+ <[^>]*> 4700002a c1 0x100002a +[0-9a-f]+ <[^>]*> 4700002b c1 0x100002b +[0-9a-f]+ <[^>]*> 4700002c c1 0x100002c +[0-9a-f]+ <[^>]*> 4700002d c1 0x100002d +[0-9a-f]+ <[^>]*> 4700002e c1 0x100002e +[0-9a-f]+ <[^>]*> 4700002f c1 0x100002f +[0-9a-f]+ <[^>]*> 47000030 c1 0x1000030 +[0-9a-f]+ <[^>]*> 47000031 c1 0x1000031 +[0-9a-f]+ <[^>]*> 47000032 c1 0x1000032 +[0-9a-f]+ <[^>]*> 47000033 c1 0x1000033 +[0-9a-f]+ <[^>]*> 47000034 c1 0x1000034 +[0-9a-f]+ <[^>]*> 47000035 c1 0x1000035 +[0-9a-f]+ <[^>]*> 47000036 c1 0x1000036 +[0-9a-f]+ <[^>]*> 47000037 c1 0x1000037 +[0-9a-f]+ <[^>]*> 47000038 c1 0x1000038 +[0-9a-f]+ <[^>]*> 47000039 c1 0x1000039 +[0-9a-f]+ <[^>]*> 4700003a c1 0x100003a +[0-9a-f]+ <[^>]*> 4700003b c1 0x100003b +[0-9a-f]+ <[^>]*> 4700003c c1 0x100003c +[0-9a-f]+ <[^>]*> 4700003d c1 0x100003d +[0-9a-f]+ <[^>]*> 4700003e c1 0x100003e +[0-9a-f]+ <[^>]*> 4700003f c1 0x100003f +[0-9a-f]+ <[^>]*> 46000000 add\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000001 sub\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000002 mul\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000003 div\.s \$f0,\$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000004 sqrt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000005 abs\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000006 mov\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000007 neg\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000008 c1 0x8 +[0-9a-f]+ <[^>]*> 46000009 c1 0x9 +[0-9a-f]+ <[^>]*> 4600000a c1 0xa +[0-9a-f]+ <[^>]*> 4600000b c1 0xb +[0-9a-f]+ <[^>]*> 4600000c round\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000d trunc\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000e ceil\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 4600000f floor\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000010 c1 0x10 +[0-9a-f]+ <[^>]*> 46000011 c1 0x11 +[0-9a-f]+ <[^>]*> 46000012 c1 0x12 +[0-9a-f]+ <[^>]*> 46000013 c1 0x13 +[0-9a-f]+ <[^>]*> 46000014 c1 0x14 +[0-9a-f]+ <[^>]*> 46000015 c1 0x15 +[0-9a-f]+ <[^>]*> 46000016 c1 0x16 +[0-9a-f]+ <[^>]*> 46000017 c1 0x17 +[0-9a-f]+ <[^>]*> 46000018 c1 0x18 +[0-9a-f]+ <[^>]*> 46000019 c1 0x19 +[0-9a-f]+ <[^>]*> 4600001a c1 0x1a +[0-9a-f]+ <[^>]*> 4600001b c1 0x1b +[0-9a-f]+ <[^>]*> 4600001c c1 0x1c +[0-9a-f]+ <[^>]*> 4600001d c1 0x1d +[0-9a-f]+ <[^>]*> 4600001e c1 0x1e +[0-9a-f]+ <[^>]*> 4600001f c1 0x1f +[0-9a-f]+ <[^>]*> 46000020 c1 0x20 +[0-9a-f]+ <[^>]*> 46000021 c1 0x21 +[0-9a-f]+ <[^>]*> 46000022 c1 0x22 +[0-9a-f]+ <[^>]*> 46000023 c1 0x23 +[0-9a-f]+ <[^>]*> 46000024 cvt\.w\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000025 c1 0x25 +[0-9a-f]+ <[^>]*> 46000026 c1 0x26 +[0-9a-f]+ <[^>]*> 46000027 c1 0x27 +[0-9a-f]+ <[^>]*> 46000028 c1 0x28 +[0-9a-f]+ <[^>]*> 46000029 c1 0x29 +[0-9a-f]+ <[^>]*> 4600002a c1 0x2a +[0-9a-f]+ <[^>]*> 4600002b c1 0x2b +[0-9a-f]+ <[^>]*> 4600002c c1 0x2c +[0-9a-f]+ <[^>]*> 4600002d c1 0x2d +[0-9a-f]+ <[^>]*> 4600002e c1 0x2e +[0-9a-f]+ <[^>]*> 4600002f c1 0x2f +[0-9a-f]+ <[^>]*> 46000030 c\.f\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000031 c\.un\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000032 c\.eq\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000033 c\.ueq\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000034 c\.olt\.s \$f0,\$f0 +[0-9a-f]+ <[^>]*> 46000035 c\.ult\.s \$f0,\$f0 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+[0-9a-f]+ <[^>]*> 47000025 c1 0x1000025 +[0-9a-f]+ <[^>]*> 47000026 c1 0x1000026 +[0-9a-f]+ <[^>]*> 47000027 c1 0x1000027 +[0-9a-f]+ <[^>]*> 47000028 c1 0x1000028 +[0-9a-f]+ <[^>]*> 47000029 c1 0x1000029 +[0-9a-f]+ <[^>]*> 4700002a c1 0x100002a +[0-9a-f]+ <[^>]*> 4700002b c1 0x100002b +[0-9a-f]+ <[^>]*> 4700002c c1 0x100002c +[0-9a-f]+ <[^>]*> 4700002d c1 0x100002d +[0-9a-f]+ <[^>]*> 4700002e c1 0x100002e +[0-9a-f]+ <[^>]*> 4700002f c1 0x100002f +[0-9a-f]+ <[^>]*> 47000030 c1 0x1000030 +[0-9a-f]+ <[^>]*> 47000031 c1 0x1000031 +[0-9a-f]+ <[^>]*> 47000032 c1 0x1000032 +[0-9a-f]+ <[^>]*> 47000033 c1 0x1000033 +[0-9a-f]+ <[^>]*> 47000034 c1 0x1000034 +[0-9a-f]+ <[^>]*> 47000035 c1 0x1000035 +[0-9a-f]+ <[^>]*> 47000036 c1 0x1000036 +[0-9a-f]+ <[^>]*> 47000037 c1 0x1000037 +[0-9a-f]+ <[^>]*> 47000038 c1 0x1000038 +[0-9a-f]+ <[^>]*> 47000039 c1 0x1000039 +[0-9a-f]+ <[^>]*> 4700003a c1 0x100003a +[0-9a-f]+ <[^>]*> 4700003b c1 0x100003b +[0-9a-f]+ <[^>]*> 4700003c c1 0x100003c +[0-9a-f]+ <[^>]*> 4700003d c1 0x100003d +[0-9a-f]+ <[^>]*> 4700003e c1 0x100003e +[0-9a-f]+ <[^>]*> 4700003f c1 0x100003f + \.\.\. diff --git a/gas/testsuite/gas/mips/allegrex@cp0b.d b/gas/testsuite/gas/mips/allegrex@cp0b.d new file mode 100644 index 00000000000..a4aebdd626b --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@cp0b.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP0 branch instructions +#as: -32 +#source: cp0b.s +#dump: mips1@cp0b.d diff --git a/gas/testsuite/gas/mips/allegrex@cp0bl.d b/gas/testsuite/gas/mips/allegrex@cp0bl.d new file mode 100644 index 00000000000..2b1f3bb3cdd --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@cp0bl.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP0 branch likely instructions +#as: -32 +#source: cp0bl.s +#dump: mips2@cp0bl.d diff --git a/gas/testsuite/gas/mips/allegrex@cp0c.d b/gas/testsuite/gas/mips/allegrex@cp0c.d new file mode 100644 index 00000000000..cf8dc942714 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@cp0c.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP0 control register move instructions +#as: -32 +#source: cp0c.s +#dump: mips1@cp0c.d diff --git a/gas/testsuite/gas/mips/allegrex@cp2d.d b/gas/testsuite/gas/mips/allegrex@cp2d.d new file mode 100644 index 00000000000..1ab311e0ede --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@cp2d.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP2 doubleword memory access instructions +#as: -32 +#error_output: cp2d.l +#source: cp2d.s diff --git a/gas/testsuite/gas/mips/allegrex@cp2m.d b/gas/testsuite/gas/mips/allegrex@cp2m.d new file mode 100644 index 00000000000..ad68946b64f --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@cp2m.d @@ -0,0 +1,5 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: MIPS CP2 memory access instructions +#as: -32 +#error_output: cp2m.l +#source: cp2m.s diff --git a/gas/testsuite/gas/mips/allegrex@isa-override-1.d b/gas/testsuite/gas/mips/allegrex@isa-override-1.d new file mode 100644 index 00000000000..5d33ac45d77 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@isa-override-1.d @@ -0,0 +1,28 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS ISA override code generation +#as: -32 + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> dc820000 0xdc820000 +[0-9a-f]+ <[^>]*> 340189ab li at,0x89ab +[0-9a-f]+ <[^>]*> 00010c38 0x10c38 +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> 3c029000 lui v0,0x9000 +[0-9a-f]+ <[^>]*> 00021438 0x21438 +[0-9a-f]+ <[^>]*> 34428000 ori v0,v0,0x8000 +[0-9a-f]+ <[^>]*> 00021438 0x21438 +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at +[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\) +[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\) +[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab +[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at + \.\.\. diff --git a/gas/testsuite/gas/mips/allegrex@isa-override-1.s b/gas/testsuite/gas/mips/allegrex@isa-override-1.s new file mode 100644 index 00000000000..02352f85547 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@isa-override-1.s @@ -0,0 +1,23 @@ + .text + .globl foo + .ent foo +foo: + ld $2, 0($4) + or $2, 0x89ab0000 + .set push + .set mips3 + ld $2, 0($4) + or $2, 0x89ab0000 + dli $2, 0x9000000080000000 + .set mips0 + ld $2, 0($4) + or $2, 0x89ab0000 + .set mips3 + .set pop + ld $2, 0($4) + or $2, 0x89ab0000 + .end foo + +# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 4, 0 + .space 16 diff --git a/gas/testsuite/gas/mips/allegrex@isa-override-2.d b/gas/testsuite/gas/mips/allegrex@isa-override-2.d new file mode 100644 index 00000000000..8ed11298e96 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@isa-override-2.d @@ -0,0 +1,4 @@ +#name: MIPS ISA override code generation 2 +#as: -32 +#source: isa-override-2.s +#error_output: allegrex@isa-override-2.l diff --git a/gas/testsuite/gas/mips/allegrex@isa-override-2.l b/gas/testsuite/gas/mips/allegrex@isa-override-2.l new file mode 100644 index 00000000000..272a9318312 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@isa-override-2.l @@ -0,0 +1,4 @@ +.*: Assembler messages: +.*:5: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000' +.*:10: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000' +.*:13: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000' diff --git a/gas/testsuite/gas/mips/allegrex@save-sub.d b/gas/testsuite/gas/mips/allegrex@save-sub.d new file mode 100644 index 00000000000..047d323f804 --- /dev/null +++ b/gas/testsuite/gas/mips/allegrex@save-sub.d @@ -0,0 +1,5 @@ +#objdump: -dr +#as: -32 -I$srcdir/$subdir +#name: SAVE/RESTORE instruction subset disassembly +#source: save-sub.s +#dump: mips1@save-sub.d diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index ff4fdc51652..ca54f126755 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -536,6 +536,9 @@ mips_arch_create xlr 64 mips64 { oddspreg } \ mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat nollsc } \ { -march=r5900 -mtune=r5900 } { -mmips:5900 } \ { mipsr5900el-*-* mips64r5900el-*-* } +mips_arch_create allegrex 32 mips2 { singlefloat ror oddspreg } \ + { -march=allegrex -mtune=allegrex } { -mmips:allegrex } \ + { allegrex-*-* allegrex-*-* } mips_arch_create mips16e2-interaptiv-mr2 32 mips16e2-32 {} \ { -march=interaptiv-mr2 -mips16 } \ { -mmips:interaptiv-mr2 } @@ -1358,12 +1361,12 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "cp1-names-mips64r2" run_dump_test "cp1-names-sb1" - # The VR5400 and R5900 have their own sets of COP2 instructions, so + # The VR5400, R5900 & Allegrex have their own sets of COP2 instructions, so # exclude them from generic testing. Likewise the Octeon and DMFC2/DMTC2. run_dump_test_arches "cp2" [mips_arch_list_matching mips1 \ - !vr5400 !r5900] + !vr5400 !r5900 !allegrex] run_dump_test_arches "cp2-64" [mips_arch_list_matching mips1 \ - !vr5400 !r5900 !octeon] + !vr5400 !r5900 !octeon !allegrex] run_dump_test_arches "cp2b" [mips_arch_list_matching mips1] run_dump_test_arches "cp2bl" [mips_arch_list_matching mips1] run_dump_test_arches "cp2m" [mips_arch_list_matching mips1] @@ -1622,6 +1625,8 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "r5900-all-vu0" run_list_test "r5900-error-vu0" "-march=r5900" + run_dump_test "allegrex" + run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2] run_list_test "ase-errors-1" "-mabi=32 -march=mips1" "ASE errors (1)" @@ -1856,7 +1861,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "attr-gnu-4-0" "-mfp32 -32" \ [mips_arch_list_matching mips1 !mips32r6] run_dump_test_arches "attr-gnu-4-0" "-mfpxx -32" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "attr-gnu-4-0" "-mfp64 -32" \ [mips_arch_list_matching mips32r2] run_dump_test_arches "attr-gnu-4-0" "-mfp64 -mno-odd-spreg -32" \ @@ -1886,7 +1891,7 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips3] } run_dump_test_arches "attr-none-o32-fpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "attr-none-o32-fp64" \ [mips_arch_list_matching mips32r2] run_dump_test_arches "attr-none-o32-fp64-nooddspreg" \ @@ -1918,7 +1923,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-1-msoft-float" "-32 -msoft-float" \ [mips_arch_list_matching mips1] run_dump_test_arches "attr-gnu-4-1" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "attr-gnu-4-1" "-32 -mfp32" \ [mips_arch_list_matching mips1 !mips32r6] if { $has_newabi } { @@ -1929,7 +1934,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp32" \ [mips_arch_list_matching mips1 !mips32r6] run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp64" \ [mips_arch_list_matching mips32r2] run_list_test_arches "attr-gnu-4-2-mdouble-float" \ @@ -1951,7 +1956,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp32" \ [mips_arch_list_matching mips1 !mips32r6] run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp64" \ [mips_arch_list_matching mips32r2] run_list_test_arches "attr-gnu-4-3-mhard-float" \ @@ -1973,7 +1978,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-4" "-32 -mfp32" \ [mips_arch_list_matching mips1 !mips32r6] run_list_test_arches "attr-gnu-4-4" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_list_test_arches "attr-gnu-4-4" "-32 -mfp64" \ [mips_arch_list_matching mips32r2] run_list_test_arches "attr-gnu-4-4" "-32 -mfp64 -mno-odd-spreg" \ @@ -2002,7 +2007,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-5-msoft-float" "-32 -msoft-float" \ [mips_arch_list_matching mips1] run_dump_test_arches "attr-gnu-4-5" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_list_test_arches "attr-gnu-4-6" "-32 -mfp32" \ [mips_arch_list_matching mips1 !mips32r6] @@ -2017,7 +2022,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-6-msoft-float" "-32 -msoft-float" \ [mips_arch_list_matching mips1] run_list_test_arches "attr-gnu-4-6" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "attr-gnu-4-6" "-32 -mfp64" \ [mips_arch_list_matching mips32r2] @@ -2034,7 +2039,7 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "attr-gnu-4-7-msoft-float" "-32 -msoft-float" \ [mips_arch_list_matching mips1] run_list_test_arches "attr-gnu-4-7" "-32 -mfpxx" \ - [mips_arch_list_matching mips2 !r5900] + [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "attr-gnu-4-7" "-32 -mfp64 -mno-odd-spreg" \ [mips_arch_list_matching mips32r2] @@ -2060,13 +2065,13 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx -mno-odd-spreg" \ [mips_arch_list_matching mips2 !singlefloat] run_dump_test_arches "fpxx-oddfpreg" \ - [mips_arch_list_matching oddspreg] + [mips_arch_list_matching oddspreg !allegrex] run_dump_test_arches "odd-spreg" "-mfp32" [mips_arch_list_matching oddspreg] - run_dump_test_arches "odd-spreg" "-mfpxx" [mips_arch_list_matching oddspreg] + run_dump_test_arches "odd-spreg" "-mfpxx" [mips_arch_list_matching oddspreg !allegrex] run_dump_test_arches "odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2] run_dump_test_arches "no-odd-spreg" "-mfp32" [mips_arch_list_matching mips1 \ !mips32r6] - run_dump_test_arches "no-odd-spreg" "-mfpxx" [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "no-odd-spreg" "-mfpxx" [mips_arch_list_matching mips2 !r5900 !allegrex] run_dump_test_arches "no-odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2] run_dump_test "module-check" run_list_test "module-check-warn" "-32" diff --git a/include/elf/mips.h b/include/elf/mips.h index 823f8dc9832..741f165b424 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -302,6 +302,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_GS464 0x00A20000 #define E_MIPS_MACH_GS464E 0x00A30000 #define E_MIPS_MACH_GS264E 0x00A40000 +#define E_MIPS_MACH_ALLEGREX 0x00A50000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 8603a5858bc..f56c2b0e6d1 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1265,6 +1265,8 @@ static const unsigned int mips_isa_table[] = { #define INSN_XLR 0x00000020 /* Imagination interAptiv MR2. */ #define INSN_INTERAPTIV_MR2 0x04000000 +/* Sony PSP Allegrex instruction. */ +#define INSN_ALLEGREX 0x08000000 /* DSP ASE */ #define ASE_DSP 0x00000001 @@ -1377,6 +1379,7 @@ static const unsigned int mips_isa_table[] = { #define CPU_MIPS64R3 66 #define CPU_MIPS64R5 68 #define CPU_MIPS64R6 69 +#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */ #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 @@ -1459,6 +1462,9 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_INTERAPTIV_MR2: return (mask & INSN_INTERAPTIV_MR2) != 0; + case CPU_ALLEGREX: + return (mask & INSN_ALLEGREX) != 0; + default: return false; } diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index faeebccfc3b..85182c6dff7 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -706,6 +706,10 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, + ISA_MIPS2, 0, mips_cp0_names_numeric, NULL, 0, + mips_cp1_names_numeric, mips_hwr_names_numeric }, + /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 329bdc628cb..4404f6280ed 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -317,6 +317,7 @@ decode_mips_operand (const char *p) /* Emotion Engine MIPS r5900. */ #define EE INSN_5900 #define M1 INSN_10000 +#define AL INSN_ALLEGREX #define SB1 INSN_SB1 #define N411 INSN_4111 #define N412 INSN_4120 @@ -341,8 +342,10 @@ decode_mips_operand (const char *p) #define G3 EE -/* 64 bit CPU with 32 bit FPU (single float). */ -#define SF EE +/* CPU without 64 bit FPU support (single float only). */ +#define SF (AL \ + |EE \ + ) /* Support for 128 bit MMI instructions. */ #define MMI EE @@ -971,8 +974,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, {"wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 }, {"cache", "k,+j(b)", 0x7c000025, 0xfc00007f, RD_3, 0, I37, 0, 0 }, -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, I37 }, -{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0 }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3|AL, 0, I37 }, +{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3|AL, 0, 0 }, {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, @@ -990,8 +993,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"clo", "d,s", 0x00000051, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +{"clo", "d,s", 0x00000017, 0xfc1f07ff, WR_1|RD_2, 0, AL, 0, 0 }, {"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +{"clz", "d,s", 0x00000016, 0xfc1f07ff, WR_1|RD_2, 0, AL, 0, 0 }, /* ctc0 is at the bottom of the table. */ {"ctc1", "t,g", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, {"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, 0 }, @@ -1187,13 +1192,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, -{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, +{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32|AL, 0, 0 }, {"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 }, {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I37, 0, 0 }, {"evp", "t", 0x41600004, 0xffe0ffff, WR_1|TRAP, 0, I37, 0, 0 }, -{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, +{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33|AL, 0, 0 }, {"exts32", "t,r,+p,+s", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"exts", "t,r,+P,+S", 0x7000003b, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* exts32 */ {"exts", "t,r,+p,+S", 0x7000003a, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, @@ -1204,7 +1209,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"hibernate", "", 0x42000023, 0xffffffff, 0, 0, V1, 0, 0 }, {"hypcall", "", 0x42000028, 0xffffffff, TRAP, 0, 0, IVIRT, 0 }, {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, -{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, +{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33|AL, 0, 0 }, {"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, {"jr", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ {"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, @@ -1277,10 +1282,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE }, -{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE }, -{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL }, +{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE|AL }, +{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE|AL }, {"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 }, {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, @@ -1324,10 +1329,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|AL }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE|AL }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE|AL }, {"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 }, {"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ @@ -1367,7 +1372,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1|AL, 0, 0 }, {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, @@ -1376,7 +1381,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"madd1", "d,s,t", 0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, {"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, -{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, +{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1|AL, 0, 0 }, {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, @@ -1384,6 +1389,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, {"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, N411, 0, 0 }, +{"max", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, AL, 0, 0 }, {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, @@ -1430,7 +1436,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* mfc2 is at the bottom of the table. */ /* mfhc2 is at the bottom of the table. */ /* mfc3 is at the bottom of the table. */ -{"mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LC, 0, N5, 0, 0 }, +{"mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LC, 0, N5|AL, 0, 0 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, I37 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_1|RD_HI, 0, 0, D32, 0 }, {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_1|RD_HI, 0, EE, 0, 0 }, @@ -1440,6 +1446,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, {"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, +{"min", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, AL, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, @@ -1455,7 +1462,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE|AL, 0, I37 }, {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F, LEXT, 0 }, {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, @@ -1469,7 +1476,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE|AL, 0, I37 }, {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, @@ -1497,10 +1504,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, +{"msub", "s,t", 0x0000002e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, AL, 0, 0 }, {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, +{"msubu", "s,t", 0x0000002f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, AL, 0, 0 }, {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, @@ -1528,7 +1537,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* mtc2 is at the bottom of the table. */ /* mthc2 is at the bottom of the table. */ /* mtc3 is at the bottom of the table. */ -{"mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|CM, 0, N5, 0, 0 }, +{"mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|CM, 0, N5|AL, 0, 0 }, {"mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, I37 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_1|WR_HI, 0, 0, D32, 0 }, {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_1|WR_HI, 0, EE, 0, 0 }, @@ -1799,13 +1808,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT, 0 }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL, SMT, 0 }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, SMT, 0 }, {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, @@ -1855,10 +1864,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE }, -{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE }, -{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL }, +{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE|AL }, +{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE|AL }, {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, @@ -1866,8 +1875,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, I69 }, {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, I37 }, -{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, -{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, +{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33|AL, 0, 0 }, +{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33|AL, 0, 0 }, {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, {"seq", "d,v,t", 0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, @@ -1990,10 +1999,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|AL }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE|AL }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE|AL }, {"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 }, {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ @@ -2090,7 +2099,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"wait", "J", 0x42000020, 0xfe00003f, NODS, 0, I32|N55, 0, 0 }, {"waiti", "", 0x42000020, 0xffffffff, NODS, 0, L1, 0, 0 }, {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_2, 0, I33, 0, 0 }, -{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, +{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_1|RD_2, 0, I33|AL, 0, 0 }, +{"wsbw", "d,w", 0x7c0000e0, 0xffe007ff, WR_1|RD_2, 0, AL, 0, 0 }, {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, {"xor", "D,S,T", 0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, @@ -2126,7 +2136,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D64, 0 }, {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, +{"bitrev", "d,w", 0x7c000520, 0xffe007ff, WR_1|RD_2, 0, AL, 0, 0 }, +{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, AL }, {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, {"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 }, {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, @@ -3343,7 +3354,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 }, /* RFE conflicts with the new Virt spec instruction tlbgp. */ -{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32 }, +{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32|AL }, /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ @@ -3376,11 +3387,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfhc2", "t,G", 0x48600000, 0xffe007ff, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mfhc2", "t,i", 0x48600000, 0xffe00000, WR_1|RD_C2|LC, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{"mfic", "t,G", 0x70000024, 0xffe007ff, WR_1|RD_C0|LC, 0, AL, 0, 0 }, {"mtc2", "t,G", 0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE }, {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I32, 0, IOCT|IOCTP|IOCT2 }, {"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, {"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM, 0, I33, 0, IOCT|IOCTP|IOCT2 }, +{"mtic", "t,G", 0x70000026, 0xffe007ff, RD_1|WR_C0|WR_CC|CM, 0, AL, 0, 0 }, {"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, {"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, {"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 }, @@ -3390,16 +3403,16 @@ const struct mips_opcode mips_builtin_opcodes[] = /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X instructions, so they are here for the latters to take precedence. */ -{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE }, -{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE }, -{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE }, -{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE }, +{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE|AL }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE|AL }, +{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE|AL }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE|AL }, +{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE|AL }, +{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE|AL }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE|AL }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE|AL }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE|AL }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE|AL }, /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the @@ -3408,11 +3421,11 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c0", "C", 0x42000000, 0xfe000000, CP, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"c1", "C", 0x46000000, 0xfe000000, FP_S, 0, I1, 0, 0 }, {"c2", "C", 0x4a000000, 0xfe000000, CP, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 }, -{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, I3_33 }, +{"c3", "C", 0x4e000000, 0xfe000000, CP, 0, I1, 0, I3_33|AL }, {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2 }, -{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, I3_33 }, +{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1, 0, I3_33|AL }, }; #define MIPS_NUM_OPCODES \ -- 2.38.1