On Fri, Jan 20, 2023 at 8:04 PM Philipp Tomsich wrote: > On Wed, 21 Dec 2022 at 18:07, Christoph Muellner > wrote: > > > > From: Christoph Müllner > > > > This commit adds the Zvkb ISA extension instructions, which are part > > of the vector crypto extensions. > > > > Signed-off-by: Christoph Müllner > > --- > > bfd/elfxx-riscv.c | 5 ++++ > > gas/config/tc-riscv.c | 13 ++++++++++ > > gas/testsuite/gas/riscv/zvkb.d | 36 ++++++++++++++++++++++++++++ > > gas/testsuite/gas/riscv/zvkb.s | 28 ++++++++++++++++++++++ > > include/opcode/riscv-opc.h | 44 ++++++++++++++++++++++++++++++++++ > > include/opcode/riscv.h | 5 ++++ > > opcodes/riscv-dis.c | 4 ++++ > > opcodes/riscv-opc.c | 16 +++++++++++++ > > 8 files changed, 151 insertions(+) > > create mode 100644 gas/testsuite/gas/riscv/zvkb.d > > create mode 100644 gas/testsuite/gas/riscv/zvkb.s > > > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > > index 0bcf2fdcfa3..22a6954ff41 100644 > > --- a/bfd/elfxx-riscv.c > > +++ b/bfd/elfxx-riscv.c > > @@ -1205,6 +1205,7 @@ static struct riscv_supported_ext > riscv_supported_std_z_ext[] = > > {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > > @@ -2415,6 +2416,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > > || riscv_subset_supports (rps, "zve64d") > > || riscv_subset_supports (rps, "zve64f") > > || riscv_subset_supports (rps, "zve32f")); > > + case INSN_CLASS_ZVKB: > > + return riscv_subset_supports (rps, "zvkb"); > > case INSN_CLASS_SVINVAL: > > return riscv_subset_supports (rps, "svinval"); > > case INSN_CLASS_H: > > @@ -2573,6 +2576,8 @@ riscv_multi_subset_supports_ext > (riscv_parse_subset_t *rps, > > return _("v' or `zve64x' or `zve32x"); > > case INSN_CLASS_ZVEF: > > return _("v' or `zve64d' or `zve64f' or `zve32f"); > > + case INSN_CLASS_ZVKB: > > + return _("zvkb"); > > case INSN_CLASS_SVINVAL: > > return "svinval"; > > case INSN_CLASS_H: > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > > index 77c0d2e32ab..51d302127c5 100644 > > --- a/gas/config/tc-riscv.c > > +++ b/gas/config/tc-riscv.c > > @@ -1322,6 +1322,7 @@ validate_riscv_insn (const struct riscv_opcode > *opc, int length) > > case 'i': > > case 'j': > > case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; > > + case 'l': used_bits |= ENCODE_RVV_VI_UIMM6(-1U); break; > > case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; > > case 'M': break; /* Macro operand, must be a mask register. > */ > > case 'T': break; /* Macro operand, must be a vector > register. */ > > @@ -2981,6 +2982,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, > expressionS *imm_expr, > > asarg = expr_end; > > continue; > > > > + case 'l': /* 6-bit vector arith unsigned immediate */ > > + my_getExpression (imm_expr, asarg); > > + check_absolute_expr (ip, imm_expr, FALSE); > > + if (imm_expr->X_add_number < 0 > > + || imm_expr->X_add_number >= 64) > > + as_bad (_("bad value for vector immediate field, " > > + "value must be 0...63")); > > + ip->insn_opcode |= ENCODE_RVV_VI_UIMM6 > (imm_expr->X_add_number); > > + imm_expr->X_op = O_absent; > > + asarg = expr_end; > > This has to be adjusted (after 6eb099ae9324), as expr_end has been > renamed to expr_parse_end. > Note that the old version will still compile (although with a > warning), as expr_end is now a function exported from expr.c. > > Please roll this change/adjustment into the next version of the series. > Thanks for the heads up! A rebased patchset with all mentioned issues addressed and all tests passing can be found here (branch might get force-pushed at any time): https://github.com/cmuellner/binutils-gdb/tree/riscv-zvk-with-fixes BR Christoph > > Thanks, > Philipp. > > > + continue; > > + > > case 'm': /* optional vector mask */ > > if (*asarg == '\0') > > { > > diff --git a/gas/testsuite/gas/riscv/zvkb.d > b/gas/testsuite/gas/riscv/zvkb.d > > new file mode 100644 > > index 00000000000..63aacba951c > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zvkb.d > > @@ -0,0 +1,36 @@ > > +#as: -march=rv64gc_zvkb > > +#objdump: -dr > > + > > +.*:[ ]+file format .* > > + > > + > > +Disassembly of section .text: > > +0+000 <.text>: > > +[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12 > > +[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t > > +[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1 > > +[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t > > +[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12 > > +[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t > > +[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1 > > +[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t > > +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 > > +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t > > +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 > > +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t > > +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12 > > +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t > > +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1 > > +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t > > +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 > > +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t > > +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 > > +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t > > +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 > > +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t > > +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12 > > +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t > > +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 > > +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t > > +[ ]+[0-9a-f]+:[ ]+0687b257[ ]+vandn.vi[ ]+v4,v8,15 > > +[ ]+[0-9a-f]+:[ ]+04883257[ ]+vandn.vi[ ]+v4,v8,-16,v0.t > > diff --git a/gas/testsuite/gas/riscv/zvkb.s > b/gas/testsuite/gas/riscv/zvkb.s > > new file mode 100644 > > index 00000000000..fd741505883 > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/zvkb.s > > @@ -0,0 +1,28 @@ > > + vclmul.vv v4, v8, v12 > > + vclmul.vv v4, v8, v12, v0.t > > + vclmul.vx v4, v8, a1 > > + vclmul.vx v4, v8, a1, v0.t > > + vclmulh.vv v4, v8, v12 > > + vclmulh.vv v4, v8, v12, v0.t > > + vclmulh.vx v4, v8, a1 > > + vclmulh.vx v4, v8, a1, v0.t > > + vrol.vv v4, v8, v12 > > + vrol.vv v4, v8, v12, v0.t > > + vrol.vx v4, v8, a1 > > + vrol.vx v4, v8, a1, v0.t > > + vror.vv v4, v8, v12 > > + vror.vv v4, v8, v12, v0.t > > + vror.vx v4, v8, a1 > > + vror.vx v4, v8, a1, v0.t > > + vror.vi v4, v8, 0 > > + vror.vi v4, v8, 63, v0.t > > + vbrev8.v v4, v8 > > + vbrev8.v v4, v8, v0.t > > + vrev8.v v4, v8 > > + vrev8.v v4, v8, v0.t > > + vandn.vv v4, v8, v12 > > + vandn.vv v4, v8, v12, v0.t > > + vandn.vx v4, v8, a1 > > + vandn.vx v4, v8, a1, v0.t > > + vandn.vi v4, v8, 15 > > + vandn.vi v4, v8, -16, v0.t > > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > > index 06e3df0f5a6..575fa5d322c 100644 > > --- a/include/opcode/riscv-opc.h > > +++ b/include/opcode/riscv-opc.h > > @@ -2055,6 +2055,35 @@ > > #define MASK_VDOTUVV 0xfc00707f > > #define MATCH_VFDOTVV 0xe4001057 > > #define MASK_VFDOTVV 0xfc00707f > > +/* Zvkb instructions. */ > > +#define MATCH_VCLMULVV 0x30002057 > > +#define MASK_VCLMULVV 0xfc00707f > > +#define MATCH_VCLMULVX 0x30006057 > > +#define MASK_VCLMULVX 0xfc00707f > > +#define MATCH_VCLMULHVV 0x34002057 > > +#define MASK_VCLMULHVV 0xfc00707f > > +#define MATCH_VCLMULHVX 0x34006057 > > +#define MASK_VCLMULHVX 0xfc00707f > > +#define MATCH_VROLVV 0x54000057 > > +#define MASK_VROLVV 0xfc00707f > > +#define MATCH_VROLVX 0x54004057 > > +#define MASK_VROLVX 0xfc00707f > > +#define MATCH_VRORVV 0x50000057 > > +#define MASK_VRORVV 0xfc00707f > > +#define MATCH_VRORVX 0x50004057 > > +#define MASK_VRORVX 0xfc00707f > > +#define MATCH_VRORVI 0x50003057 > > +#define MASK_VRORVI 0xf800707f > > +#define MATCH_VBREV8V 0x48042057 > > +#define MASK_VBREV8V 0xfc0ff07f > > +#define MATCH_VREV8V 0x4804a057 > > +#define MASK_VREV8V 0xfc0ff07f > > +#define MATCH_VANDNVV 0x04000057 > > +#define MASK_VANDNVV 0xfc00707f > > +#define MATCH_VANDNVX 0x04004057 > > +#define MASK_VANDNVX 0xfc00707f > > +#define MATCH_VANDNVI 0x04003057 > > +#define MASK_VANDNVI 0xfc00707f > > /* Svinval instruction. */ > > #define MATCH_SINVAL_VMA 0x16000073 > > #define MASK_SINVAL_VMA 0xfe007fff > > @@ -3118,6 +3147,21 @@ DECLARE_INSN(cbo_zero, MATCH_CBO_ZERO, > MASK_CBO_ZERO); > > /* Zawrs instructions. */ > > DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) > > DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) > > +/* Zvkb instructions. */ > > +DECLARE_INSN(vclmulvv, MATCH_VCLMULVV, MASK_VCLMULVV) > > +DECLARE_INSN(vclmulvx, MATCH_VCLMULVX, MASK_VCLMULVX) > > +DECLARE_INSN(vclmulhvv, MATCH_VCLMULHVV, MASK_VCLMULHVV) > > +DECLARE_INSN(vclmulhvx, MATCH_VCLMULHVX, MASK_VCLMULHVX) > > +DECLARE_INSN(vrolvv, MATCH_VROLVV, MASK_VROLVV) > > +DECLARE_INSN(vrolvx, MATCH_VROLVX, MASK_VROLVX) > > +DECLARE_INSN(vrorvv, MATCH_VRORVV, MASK_VRORVV) > > +DECLARE_INSN(vrorvx, MATCH_VRORVX, MASK_VRORVX) > > +DECLARE_INSN(vrorvi, MATCH_VRORVI, MASK_VRORVI) > > +DECLARE_INSN(vbrev8v, MATCH_VBREV8V, MASK_VBREV8V) > > +DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V) > > +DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV) > > +DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX) > > +DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI) > > /* Vendor-specific (T-Head) XTheadBa instructions. */ > > DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) > > /* Vendor-specific (T-Head) XTheadBb instructions. */ > > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > > index c3cbde600cb..1ba123e4933 100644 > > --- a/include/opcode/riscv.h > > +++ b/include/opcode/riscv.h > > @@ -100,6 +100,8 @@ static inline unsigned int riscv_insn_length (insn_t > insn) > > (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5)) > > #define EXTRACT_RVV_VI_UIMM(x) \ > > (RV_X(x, 15, 5)) > > +#define EXTRACT_RVV_VI_UIMM6(x) \ > > + (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5)) > > #define EXTRACT_RVV_OFFSET(x) \ > > (RV_X(x, 29, 3)) > > #define EXTRACT_RVV_VB_IMM(x) \ > > @@ -151,6 +153,8 @@ static inline unsigned int riscv_insn_length (insn_t > insn) > > (RV_X(x, 0, 10) << 20) > > #define ENCODE_RVV_VC_IMM(x) \ > > (RV_X(x, 0, 11) << 20) > > +#define ENCODE_RVV_VI_UIMM6(x) \ > > + (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26) > > > > #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == > (x)) > > #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == > (x)) > > @@ -405,6 +409,7 @@ enum riscv_insn_class > > INSN_CLASS_ZKND_OR_ZKNE, > > INSN_CLASS_V, > > INSN_CLASS_ZVEF, > > + INSN_CLASS_ZVKB, > > INSN_CLASS_SVINVAL, > > INSN_CLASS_ZICBOM, > > INSN_CLASS_ZICBOP, > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > > index 0e1f3b4610a..6bb21ebb56f 100644 > > --- a/opcodes/riscv-dis.c > > +++ b/opcodes/riscv-dis.c > > @@ -397,6 +397,10 @@ print_insn_args (const char *oparg, insn_t l, > bfd_vma pc, disassemble_info *info > > print (info->stream, dis_style_immediate, "%d", > > (int)EXTRACT_RVV_OFFSET (l)); > > break; > > + case 'l': > > + print (info->stream, dis_style_immediate, "%d", > > + (int)EXTRACT_RVV_VI_UIMM6 (l)); > > + break; > > case 'm': > > if (!EXTRACT_OPERAND (VMASK, l)) > > { > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 0e691544f9b..98ca3a4cc56 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -1815,6 +1815,22 @@ const struct riscv_opcode riscv_opcodes[] = > > {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, > match_opcode, 0}, > > {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, > match_opcode, 0}, > > > > +/* Zvkb instructions. */ > > +{"vclmul.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULVV, > MASK_VCLMULVV, match_opcode, 0}, > > +{"vclmul.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULVX, > MASK_VCLMULVX, match_opcode, 0}, > > +{"vclmulh.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VCLMULHVV, > MASK_VCLMULHVV, match_opcode, 0}, > > +{"vclmulh.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VCLMULHVX, > MASK_VCLMULHVX, match_opcode, 0}, > > +{"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROLVV, > MASK_VROLVV, match_opcode, 0}, > > +{"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROLVX, > MASK_VROLVX, match_opcode, 0}, > > +{"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VRORVV, > MASK_VRORVV, match_opcode, 0}, > > +{"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VRORVX, > MASK_VRORVX, match_opcode, 0}, > > +{"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VRORVI, > MASK_VRORVI, match_opcode, 0}, > > +{"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8V, > MASK_VBREV8V, match_opcode, 0}, > > +{"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8V, > MASK_VREV8V, match_opcode, 0}, > > +{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDNVV, > MASK_VANDNVV, match_opcode, 0}, > > +{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, > MASK_VANDNVX, match_opcode, 0}, > > +{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, > MASK_VANDNVI, match_opcode, 0}, > > + > > /* Supervisor instructions. */ > > {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, > MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, > > {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, > MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, > > -- > > 2.38.1 > > >