From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by sourceware.org (Postfix) with ESMTPS id C1633385840A for ; Fri, 18 Nov 2022 07:25:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C1633385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ot1-x336.google.com with SMTP id p27-20020a056830319b00b0066d7a348e20so2570842ots.8 for ; Thu, 17 Nov 2022 23:25:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=/RWvQOL0R6PLcfN9C2Aek8RuHw4nIOQKBziahwM1sQI=; b=kbmTGAD23JzJNfwq28K75jP31TsypQigNsw/DizkyIlgtyV6EPs4B15E83+0HEL5bI MjSvDd2W6hC2r0kcr5vcpFmtKucituk9910i8T+/Gf7bX80yTJCYRkhhZbJR75KR4PYf AfnNa1evc4oB3anE2o5Cs+GOl8HQKNLWMF9mYbcGCfDAtIFiDSdH4LOBJSxtL/PDHHBW Kd8430kS/A7dub7Mq/YpYAcDy/sxPQ83LmrmKmtvz+50IPs3g0xD+lVbwfR/EHtEN+ZK tXBD0LT3Q1H6IIG77Zcp6IRpuYs12f1sAyKOR0/hZ+MknQtJ5qD1Zwsv+j6DSeivyJ1v AhMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/RWvQOL0R6PLcfN9C2Aek8RuHw4nIOQKBziahwM1sQI=; b=xTRBPqPPa6Xs2DqcycqQ9ZmcxgTfd0C+zpg78IK6z8LDo9FEyjwLFKi4fwDeioHQOp vJP9ydk+5kjfWhigYvyWTdB3RZ0FBvzLBeEeMO1Od8+fa/kU+aQf0Cxs12SUaPHsICjy nvEDtlCNuKbWZnimGfnI4OJ5YNIkG8KQ3O4HN0rNzcMNFJCTSdk2zEn65jSJpZG31Dzv IOUwk21lOO8sbvsxdLiX8RJ2gzAjVUwrApWsyM8HHUFqDCEKeW8a9lXJSYG+f3TSWruZ 9EQtOxgWsQoqPCkQlFzdTi1TuMhcXYMvA2kVOfZgvl8ruerR5Glo4Wx+qanbMPUt9w4a FlOQ== X-Gm-Message-State: ANoB5pl1Dwfi2egJIQOkVnj606NL8sMZ7JGzzwnl1agYem0uWAsyugxg evDKKK81WWKrfG3wymzYS3KfrnKn71RJf1RXcc1NIw== X-Google-Smtp-Source: AA0mqf6k+rLNdNSdX/58ng21DaVUcsFQLYvbAOuqHw+7pcZwyizRQSeX/jp8bGt/IEmEXG+nJd+5yQC168jpBqxP/kI= X-Received: by 2002:a05:6830:22d2:b0:661:abab:aa4d with SMTP id q18-20020a05683022d200b00661ababaa4dmr3145159otc.382.1668756348046; Thu, 17 Nov 2022 23:25:48 -0800 (PST) MIME-Version: 1.0 References: <4c45925619ab51261ca87d309883c9aa7cd05240.1668736896.git.research_trasio@irq.a4lg.com> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Fri, 18 Nov 2022 08:25:35 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Add INSN_DREF to memory read/write instructions To: Nelson Chu Cc: Tsukasa OI , Lifang Xia , Kito Cheng , Palmer Dabbelt , Tsukasa OI , Binutils Content-Type: multipart/alternative; boundary="00000000000057a53105edb99dbd" X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000057a53105edb99dbd Content-Type: text/plain; charset="UTF-8" On Fri, Nov 18, 2022 at 3:18 AM Nelson Chu wrote: > LGTM, but I think we must get the approvals from Lifang and Christoph. > Ack. I've also reviewed the size flags. However, I am not sure I understand the purpose of these flags. I can't find any use of them in the repo. Also, there are no tests for these flags. Can you shed some light on this? Thanks, Christoph > > Thanks > Nelson > > On Fri, Nov 18, 2022 at 10:02 AM Tsukasa OI > wrote: > > > > From: Tsukasa OI > > > > From: Tsukasa OI > > > > This commit adds INSN_DREF flag (and size-related flags) to instruction > > which reads/writes the memory directly. It however excludes > cache-related > > instructions that does synchronization with other cores but otherwise > > does not touch the contents of the memory. > > > > INSN_DREF and size flags are added to following instructions: > > > > - "cbo.zero" > > - All instructions from following custom extensions: > > - XTheadFMemIdx > > - XTheadInt > > - XTheadMemIdx > > - XTheadMemPair > > > > opcodes/ChangeLog: > > > > * riscv-opc.c (riscv_opcodes): Add INSN_DREF and size flags on > the > > instructions directly reads/writes memory. > > --- > > opcodes/riscv-opc.c | 124 ++++++++++++++++++++++---------------------- > > 1 file changed, 62 insertions(+), 62 deletions(-) > > > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 0e691544f9bc..5a6f98421512 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -933,7 +933,7 @@ const struct riscv_opcode riscv_opcodes[] = > > {"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, > MASK_CBO_CLEAN, match_opcode, 0 }, > > {"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, > MASK_CBO_FLUSH, match_opcode, 0 }, > > {"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, > MASK_CBO_INVAL, match_opcode, 0 }, > > -{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, > MASK_CBO_ZERO, match_opcode, 0 }, > > +{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, > MASK_CBO_ZERO, match_opcode, INSN_DREF }, > > > > /* Zawrs instructions. */ > > {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, > match_opcode, 0 }, > > @@ -1922,77 +1922,77 @@ const struct riscv_opcode riscv_opcodes[] = > > {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", > MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, > > > > /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ > > -{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, > > -{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, > > -{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, > > -{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, > > -{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, > > -{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, > > -{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, > > -{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, > > +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", > MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > > > /* Vendor-specific (T-Head) XTheadFmv instructions. */ > > {"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, > MASK_TH_FMV_HW_X, match_opcode, 0}, > > {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, > MASK_TH_FMV_X_HW, match_opcode, 0}, > > > > /* Vendor-specific (T-Head) XTheadInt instructions. */ > > -{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, > MASK_TH_IPOP, match_opcode, 0}, > > -{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, > MASK_TH_IPUSH, match_opcode, 0}, > > +{"th.ipop", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPOP, > MASK_TH_IPOP, match_opcode, INSN_DREF }, > > +{"th.ipush", 0, INSN_CLASS_XTHEADINT, "", MATCH_TH_IPUSH, > MASK_TH_IPUSH, match_opcode, INSN_DREF }, > > > > /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ > > -{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, > > -{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, 0}, > > -{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, 0}, > > -{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, 0}, > > -{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, 0}, > > -{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, 0}, > > -{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, 0}, > > -{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, 0}, > > -{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, 0}, > > -{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, 0}, > > -{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, 0}, > > -{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, 0}, > > -{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, 0}, > > -{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, 0}, > > -{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, 0}, > > -{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, 0}, > > -{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, 0}, > > -{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, 0}, > > -{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, 0}, > > -{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, 0}, > > -{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, 0}, > > -{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, 0}, > > - > > -{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRD, MASK_TH_LRD, match_opcode, 0}, > > -{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRW, MASK_TH_LRW, match_opcode, 0}, > > -{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, 0}, > > -{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRH, MASK_TH_LRH, match_opcode, 0}, > > -{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, 0}, > > -{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRB, MASK_TH_LRB, match_opcode, 0}, > > -{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, 0}, > > -{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRD, MASK_TH_SRD, match_opcode, 0}, > > -{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRW, MASK_TH_SRW, match_opcode, 0}, > > -{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRH, MASK_TH_SRH, match_opcode, 0}, > > -{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRB, MASK_TH_SRB, match_opcode, 0}, > > - > > -{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURD, MASK_TH_LURD, match_opcode, 0}, > > -{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURW, MASK_TH_LURW, match_opcode, 0}, > > -{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, 0}, > > -{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURH, MASK_TH_LURH, match_opcode, 0}, > > -{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, 0}, > > -{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURB, MASK_TH_LURB, match_opcode, 0}, > > -{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, 0}, > > -{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURD, MASK_TH_SURD, match_opcode, 0}, > > -{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURW, MASK_TH_SURW, match_opcode, 0}, > > -{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURH, MASK_TH_SURH, match_opcode, 0}, > > -{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURB, MASK_TH_SURB, match_opcode, 0}, > > +{"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, INSN_DREF|INSN_8_BYTE }, > > +{"th.ldib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LDIB, MASK_TH_LDIB, match_th_load_inc, INSN_DREF|INSN_8_BYTE }, > > +{"th.lwia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIA, MASK_TH_LWIA, match_th_load_inc, INSN_DREF|INSN_4_BYTE }, > > +{"th.lwib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWIB, MASK_TH_LWIB, match_th_load_inc, INSN_DREF|INSN_4_BYTE }, > > +{"th.lwuia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIA, MASK_TH_LWUIA, match_th_load_inc, INSN_DREF|INSN_4_BYTE }, > > +{"th.lwuib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LWUIB, MASK_TH_LWUIB, match_th_load_inc, INSN_DREF|INSN_4_BYTE }, > > +{"th.lhia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIA, MASK_TH_LHIA, match_th_load_inc, INSN_DREF|INSN_2_BYTE }, > > +{"th.lhib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHIB, MASK_TH_LHIB, match_th_load_inc, INSN_DREF|INSN_2_BYTE }, > > +{"th.lhuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIA, MASK_TH_LHUIA, match_th_load_inc, INSN_DREF|INSN_2_BYTE }, > > +{"th.lhuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LHUIB, MASK_TH_LHUIB, match_th_load_inc, INSN_DREF|INSN_2_BYTE }, > > +{"th.lbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIA, MASK_TH_LBIA, match_th_load_inc, INSN_DREF|INSN_1_BYTE }, > > +{"th.lbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBIB, MASK_TH_LBIB, match_th_load_inc, INSN_DREF|INSN_1_BYTE }, > > +{"th.lbuia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIA, MASK_TH_LBUIA, match_th_load_inc, INSN_DREF|INSN_1_BYTE }, > > +{"th.lbuib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_LBUIB, MASK_TH_LBUIB, match_th_load_inc, INSN_DREF|INSN_1_BYTE }, > > +{"th.sdia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIA, MASK_TH_SDIA, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.sdib", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SDIB, MASK_TH_SDIB, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.swia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIA, MASK_TH_SWIA, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.swib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SWIB, MASK_TH_SWIB, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.shia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIA, MASK_TH_SHIA, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.shib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SHIB, MASK_TH_SHIB, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.sbia", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIA, MASK_TH_SBIA, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.sbib", 0, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", > MATCH_TH_SBIB, MASK_TH_SBIB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > + > > +{"th.lrd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRD, MASK_TH_LRD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.lrw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRW, MASK_TH_LRW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lrwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRWU, MASK_TH_LRWU, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lrh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRH, MASK_TH_LRH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lrhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRHU, MASK_TH_LRHU, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lrb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRB, MASK_TH_LRB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.lrbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LRBU, MASK_TH_LRBU, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.srd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRD, MASK_TH_SRD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.srw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRW, MASK_TH_SRW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.srh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRH, MASK_TH_SRH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.srb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SRB, MASK_TH_SRB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > + > > +{"th.lurd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURD, MASK_TH_LURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.lurw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURW, MASK_TH_LURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lurwu", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURWU, MASK_TH_LURWU, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.lurh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURH, MASK_TH_LURH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lurhu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURHU, MASK_TH_LURHU, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.lurb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURB, MASK_TH_LURB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.lurbu", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_LURBU, MASK_TH_LURBU, match_opcode, INSN_DREF|INSN_1_BYTE }, > > +{"th.surd", 64, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURD, MASK_TH_SURD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +{"th.surw", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURW, MASK_TH_SURW, match_opcode, INSN_DREF|INSN_4_BYTE }, > > +{"th.surh", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURH, MASK_TH_SURH, match_opcode, INSN_DREF|INSN_2_BYTE }, > > +{"th.surb", 0, INSN_CLASS_XTHEADMEMIDX, "d,s,t,Xu2@25", > MATCH_TH_SURB, MASK_TH_SURB, match_opcode, INSN_DREF|INSN_1_BYTE }, > > > > /* Vendor-specific (T-Head) XTheadMemPair instructions. */ > > -{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, 0}, > > -{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, 0}, > > -{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, 0}, > > -{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_SDD, MASK_TH_SDD, match_opcode, 0}, > > -{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_SWD, MASK_TH_SWD, match_opcode, 0}, > > +{"th.ldd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_LDD, MASK_TH_LDD, match_th_load_pair, INSN_DREF|INSN_16_BYTE }, > > +{"th.lwd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWD, MASK_TH_LWD, match_th_load_pair, INSN_DREF|INSN_8_BYTE }, > > +{"th.lwud", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_LWUD, MASK_TH_LWUD, match_th_load_pair, INSN_DREF|INSN_8_BYTE }, > > +{"th.sdd", 64, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl4", > MATCH_TH_SDD, MASK_TH_SDD, match_opcode, INSN_DREF|INSN_16_BYTE }, > > +{"th.swd", 0, INSN_CLASS_XTHEADMEMPAIR, "d,t,(s),Xu2@25,Xl3", > MATCH_TH_SWD, MASK_TH_SWD, match_opcode, INSN_DREF|INSN_8_BYTE }, > > > > /* Vendor-specific (T-Head) XTheadMac instructions. */ > > {"th.mula", 0, INSN_CLASS_XTHEADMAC, "d,s,t", MATCH_TH_MULA, > MASK_TH_MULA, match_opcode, 0}, > > > > base-commit: 9c93bc90d577ac191ec94503e04cdcf87a3d2a1a > > -- > > 2.38.1 > > > --00000000000057a53105edb99dbd--