From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by sourceware.org (Postfix) with ESMTPS id F110A3AA8C7C for ; Sun, 18 Sep 2022 06:51:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F110A3AA8C7C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-qt1-x829.google.com with SMTP id ay9so8018032qtb.0 for ; Sat, 17 Sep 2022 23:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=34cbKVEkBQO+IhjUoxqNa6+TH/j6CktZWd6n+wFDUEs=; b=OLY8lFrgX6cFpQSx33l5tDEr48u1jqXketJpHMXcVvLKCGlOg9XHeZ0paaBltgIIqN sLpF36onv+CFpVe/j04IoEJpXgvMJyFnGprau3pcIUZBPBW+HKPfxNuuCO6QY+ksASlX L/KsYeyBm8ER41WXxz+8ggoamN6pIFUQp7s2QmrDFfphW+qQdqK+ARlokw8v1XuPDRMI 457CY4a4XUxUWWGlwl0aQpNEy3MM7k0RbMukTyj4/W5xMbm52K0lPH0esD5sXrc24cqf sia8SRa+4ULSBhbwHY5nQaxRHPsnkdYqYlOqcQq706gKAhErxqneLW7ybeKrDYcpP4JC 06Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=34cbKVEkBQO+IhjUoxqNa6+TH/j6CktZWd6n+wFDUEs=; b=SvRDW6UtmislNCSg/57Mv0kdwnGFt4ZX4jHnQPhXNZQT9iOYZOWNL/ZQMc+RPrd/wn uPkIwHfMLBYOF2VPy4bz0ZD+DHzraERrgOT+1rQBBPVjs+xPFeGHn9jLJzwq07mtbIHs LiHAQtJis10Sv+TzacpxJhce7oKJKWN2oAoR68/RVMhUW9aQwi2ga1bCc/XXFG57X7Cp eBXJ7y998s2cjVgMhdBkmf/XfFPBgqsNCZ27eEUAUtLwd+3ThYAxjcWKg9gto6oB8KPZ sLxozmLhJKNpDtHcF43X/fh3HY61Lf3wjYL2mc/oyHnv2WCwuWkTpNnLBWk11s3srgSw JtpA== X-Gm-Message-State: ACrzQf30YPYJ+QeLovInKaPQGLrbV61ipqCXLcucWOqYSdn9CYe2WhPx X9BU39coC+wR7gqABNF4DPQ9n8mX5os53XFx0EW9hQ== X-Google-Smtp-Source: AMsMyM4esBsPVbg4gj9fODpp6qihtN73RiCFvMH+1QVNRoGd8+Smwo9Tfn4GIeO57Kp2lBQSmee1yUkTBJykCId0c+s= X-Received: by 2002:a05:622a:1ba8:b0:35b:b64b:5c82 with SMTP id bp40-20020a05622a1ba800b0035bb64b5c82mr10653946qtb.95.1663483877357; Sat, 17 Sep 2022 23:51:17 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Sun, 18 Sep 2022 08:51:05 +0200 Message-ID: Subject: Re: [PATCH 00/13] Add support for the T-Head vendor extensions To: Palmer Dabbelt Cc: nelson@rivosinc.com, binutils@sourceware.org, kito.cheng@sifive.com, Jim Wilson , philipp.tomsich@vrull.eu, cooper.qu@linux.alibaba.com, lifang_xia@linux.alibaba.com, yunhai@linux.alibaba.com, zhiwei_liu@linux.alibaba.com Content-Type: multipart/alternative; boundary="000000000000998d6205e8ee0562" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HTML_MESSAGE,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000998d6205e8ee0562 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Sep 16, 2022 at 11:58 AM Palmer Dabbelt wrote: > On Fri, 16 Sep 2022 02:36:32 PDT (-0700), nelson@rivosinc.com wrote: > > Hi Christoph, > > > > > > On Tue, Sep 6, 2022 at 8:22 PM Christoph Muellner > > wrote: > >> > >> From: Christoph M=C3=BCllner > >> > >> This series introduces support for the T-Head vendor extensions, > >> which are implemented e.g. in the XuanTie C906 and XuanTie C910 > >> processors: > >> * XTheadBa > >> * XTheadBb > >> * XTheadBs > >> * XTheadCmo > >> * XTheadCondMov > >> * XTheadFMemIdx > >> * XTheadMac > >> * XTheadMemIdx > >> * XTheadMemPair > >> * XTheadSync > >> > >> The xthead* extensions are documented here: > >> > https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0= .0/xthead-2022-09-05-2.0.0.pdf > >> > >> The "th." instruction prefix prevents future conflicts with standard > >> extensions and has been documentented in a PR for the RISC-V toolchain > >> conventions: > >> https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 > >> > >> The goal of this patchset is to provide access to these instruction > >> so that compilers/users can optimize SW accordingly. > >> > >> Note, that the T-Head vendor extensions do not contain all > >> vendor-specific > >> functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are > >> included). > >> Instead the extensions cover coherent functionality, that is exposed to > >> S and U mode. > >> > >> To enable the extensions above, the following two methods are possible: > >> * add the extension to the arch string (e.g. > >> * -march=3Drv64gc_xtheadcmo_xtheadsync) > >> * implicitly select the extensions via CPU selection (e.g. > >> * -mcpu=3Dthead-c910) > >> > >> The patchset attempts to minimize code changes in generic/infrastructu= re > >> code. All patches in this series come with tests to avoid future > regressions. > >> > >> Christoph M=C3=BCllner (13): > >> RISC-V: Add generic support for vendor extensions > >> RISC-V: Add T-Head CMO vendor extension > >> RISC-V: Add T-Head SYNC vendor extension > >> RISC-V: Add support for arbitrary immediate encoding formats > >> RISC-V: Add T-Head Bitmanip vendor extension > >> RISC-V: Add T-Head CondMov vendor extension > >> RISC-V: Add T-Head MAC vendor extension > >> RISC-V: Add T-Head FMemIdx vendor extension > >> RISC-V: Add T-Head MemIdx vendor extension > >> RISC-V: Add support for literal instruction arguments > >> RISC-V: Add T-Head MemPair vendor extension > > > > There are three minor issues, > > > > 1. Probably need to add new extension support in > > riscv_multi_subset_supports_ext, although it is just used for > > reporting better error messages. > > 2. The operand L seems only to be used for t-head for now, so it > > should be still a vendor operand, named with the X prefix probably > > better. > > 3. I remember Lifang mentioned before that we should add these vendor > > stuff based on the vendor infra in the integration branch, and that's > > what I asked him to rebase his patches to there before, since the > > previous policy cannot accept vendor stuff on master branch. But now > > I think most of us agree to accept t-head extensions on mainline > > directly, so I figured these things cannot be blocked by the vendor > > infra and cannot be committed. That doesn't mean we don't need the > > vendor infra, that means we can support the vendor infra later if me > > or someone have time to move them back to mainline. > > > > Therefore, these patches look good to me for now, thank you very much > > for spending so much time to implement these. But personally, I think > > we should get the approval from the T-Head guys at least. Btw, If > > these implementations are referred to and based on the integration > > branch, then I think it would be better to keep at least the > > co-authors there in the commit message here; if these patches are > > re-write without referring to the implementation from the integration > > branch, then I need to apologize to them, because I asked them to > > rewrite their patches over there, and cannot be committed to mainline > > at that time... > > > >> riscv: gas: Add command line option '-mcpu=3D' to specify the CPU > >> riscv: Add T-Head entries for the -mcpu=3D flag > > > > Not sure if it is necessary to add -mcpu in assembler, since the > > compiler should recognize -mcpu, and will expand it to the correct > > extensions to assembler. If there are no objections for a period of > > time, then please go ahead and commit these. > > I'd also learn towards keeping -mcpu out of the assembler, it's just > going to result in subtly different behavior between GCC and GAS which > will cause subtle headaches in the future. All -mcpu does is set -march > and -mtune, so if we just continue keeping it in GCC then we have a > single source of truth. GCC will already need to understand -march for > everything that GAS needs to know anyway, so it's not like it's adding > complexity. > > Is there something broken in GCC where -mcpu isn't setting the right > -march for GAS and thus we're not getting the right extensions enabled? > If that's the case I'd argue we're better off just fixing the bug over > there. > No, nothing is broken. The main use case was direct invocations of the assembler, but I'm fine with dropping the patch. Thanks, Christoph > > > > > Thank you very much > > Nelson > > > >> bfd/elfxx-riscv.c | 39 ++- > >> gas/config/tc-riscv.c | 127 +++++++ > >> gas/doc/c-riscv.texi | 70 ++++ > >> gas/testsuite/gas/riscv/mcpu-fail-unknown.d | 3 + > >> gas/testsuite/gas/riscv/mcpu-fail-unknown.l | 2 + > >> gas/testsuite/gas/riscv/mcpu-ok-c906.d | 6 + > >> gas/testsuite/gas/riscv/mcpu-ok-c910.d | 6 + > >> gas/testsuite/gas/riscv/x-thead-ba-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-ba-fail.l | 3 + > >> gas/testsuite/gas/riscv/x-thead-ba-fail.s | 3 + > >> gas/testsuite/gas/riscv/x-thead-ba.d | 13 + > >> gas/testsuite/gas/riscv/x-thead-ba.s | 6 + > >> gas/testsuite/gas/riscv/x-thead-bb-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-bb-fail.l | 7 + > >> gas/testsuite/gas/riscv/x-thead-bb-fail.s | 7 + > >> gas/testsuite/gas/riscv/x-thead-bb.d | 30 ++ > >> gas/testsuite/gas/riscv/x-thead-bb.s | 22 ++ > >> gas/testsuite/gas/riscv/x-thead-bs-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-bs-fail.l | 3 + > >> gas/testsuite/gas/riscv/x-thead-bs-fail.s | 3 + > >> gas/testsuite/gas/riscv/x-thead-bs.d | 14 + > >> gas/testsuite/gas/riscv/x-thead-bs.s | 6 + > >> gas/testsuite/gas/riscv/x-thead-cmo-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-cmo-fail.l | 22 ++ > >> gas/testsuite/gas/riscv/x-thead-cmo-fail.s | 22 ++ > >> gas/testsuite/gas/riscv/x-thead-cmo.d | 30 ++ > >> gas/testsuite/gas/riscv/x-thead-cmo.s | 22 ++ > >> gas/testsuite/gas/riscv/x-thead-condmov.d | 11 + > >> gas/testsuite/gas/riscv/x-thead-condmov.s | 3 + > >> .../gas/riscv/x-thead-fmemidx-fail.d | 3 + > >> .../gas/riscv/x-thead-fmemidx-fail.l | 18 + > >> .../gas/riscv/x-thead-fmemidx-fail.s | 17 + > >> gas/testsuite/gas/riscv/x-thead-fmemidx.d | 25 ++ > >> gas/testsuite/gas/riscv/x-thead-fmemidx.s | 17 + > >> gas/testsuite/gas/riscv/x-thead-mac.d | 15 + > >> gas/testsuite/gas/riscv/x-thead-mac.s | 7 + > >> gas/testsuite/gas/riscv/x-thead-memidx-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-memidx-fail.l | 14 + > >> gas/testsuite/gas/riscv/x-thead-memidx-fail.s | 14 + > >> gas/testsuite/gas/riscv/x-thead-memidx.d | 53 +++ > >> gas/testsuite/gas/riscv/x-thead-memidx.s | 48 +++ > >> .../gas/riscv/x-thead-mempair-fail.d | 3 + > >> .../gas/riscv/x-thead-mempair-fail.l | 30 ++ > >> .../gas/riscv/x-thead-mempair-fail.s | 30 ++ > >> gas/testsuite/gas/riscv/x-thead-mempair.d | 14 + > >> gas/testsuite/gas/riscv/x-thead-mempair.s | 6 + > >> gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 + > >> gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 + > >> gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 + > >> gas/testsuite/gas/riscv/x-thead-sync.d | 14 + > >> gas/testsuite/gas/riscv/x-thead-sync.s | 6 + > >> include/opcode/riscv-opc.h | 326 ++++++++++++++++++ > >> include/opcode/riscv.h | 27 ++ > >> opcodes/riscv-dis.c | 44 +++ > >> opcodes/riscv-opc.c | 155 +++++++++ > >> 55 files changed, 1394 insertions(+), 2 deletions(-) > >> create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.d > >> create mode 100644 gas/testsuite/gas/riscv/mcpu-fail-unknown.l > >> create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c906.d > >> create mode 100644 gas/testsuite/gas/riscv/mcpu-ok-c910.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-ba.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bb.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-bs.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-cmo.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-condmov.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-fmemidx.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mac.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-memidx.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-mempair.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.l > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync-fail.s > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.d > >> create mode 100644 gas/testsuite/gas/riscv/x-thead-sync.s > >> > >> -- > >> 2.37.2 > >> > --000000000000998d6205e8ee0562--