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Mon, 03 Jul 2023 03:11:07 -0700 (PDT) MIME-Version: 1.0 References: <20230701052104.4018352-1-christoph.muellner@vrull.eu> <20230701052104.4018352-6-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Mon, 3 Jul 2023 12:10:52 +0200 Message-ID: Subject: Re: [PATCH v6 05/15] RISC-V: Add support for the Zvknh[a,b] ISA extensions To: Nelson Chu Cc: binutils@sourceware.org, Nathan Huckleberry , nhuck@pmull.org, Jeff Law , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Jul 3, 2023 at 11:47=E2=80=AFAM Nelson Chu wr= ote: > > > > On Sat, Jul 1, 2023 at 1:21=E2=80=AFPM Christoph Muellner wrote: >> >> From: Christoph M=C3=BCllner >> >> Zvknh[a,b] are parts of the vector crypto extensions. >> >> This extension adds the following instructions: >> - vsha2ms.vv >> - vsha2c[hl].vv >> >> bfd/ChangeLog: >> >> * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction >> class support for Zvknh[a,b]. >> (riscv_multi_subset_supports_ext): Likewise. >> >> gas/ChangeLog: >> >> * testsuite/gas/riscv/zvknha.d: New test. >> * testsuite/gas/riscv/zvknha_zvknhb.s: New test. >> * testsuite/gas/riscv/zvknhb.d: New test. >> >> include/ChangeLog: >> >> * opcode/riscv-opc.h (MATCH_VSHA2CH_VV): New. >> (MASK_VSHA2CH_VV): New. >> (MATCH_VSHA2CL_VV): New. >> (MASK_VSHA2CL_VV): New. >> (MATCH_VSHA2MS_VV): New. >> (MASK_VSHA2MS_VV): New. >> (DECLARE_INSN): New. >> * opcode/riscv.h (enum riscv_insn_class): Add instruction class >> support for Zvknh[a,b]. >> >> opcodes/ChangeLog: >> >> * riscv-opc.c: Add Zvknh[a,b] instructions. >> >> Signed-off-by: Nathan Huckleberry >> Signed-off-by: Christoph M=C3=BCllner >> --- >> bfd/elfxx-riscv.c | 13 +++++++++++++ >> gas/testsuite/gas/riscv/zvknha.d | 12 ++++++++++++ >> gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +++ >> gas/testsuite/gas/riscv/zvknhb.d | 12 ++++++++++++ >> include/opcode/riscv-opc.h | 11 +++++++++++ >> include/opcode/riscv.h | 3 +++ >> opcodes/riscv-opc.c | 5 +++++ >> 7 files changed, 59 insertions(+) >> create mode 100644 gas/testsuite/gas/riscv/zvknha.d >> create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s >> create mode 100644 gas/testsuite/gas/riscv/zvknhb.d >> >> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c >> index be8d956f316..696b5c10147 100644 >> --- a/bfd/elfxx-riscv.c >> +++ b/bfd/elfxx-riscv.c >> @@ -1266,6 +1266,8 @@ static struct riscv_supported_ext riscv_supported_= std_z_ext[] =3D >> {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> + {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, >> @@ -2439,6 +2441,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t= *rps, >> return riscv_subset_supports (rps, "zvkg"); >> case INSN_CLASS_ZVKNED: >> return riscv_subset_supports (rps, "zvkned"); >> + case INSN_CLASS_ZVKNHA: >> + return riscv_subset_supports (rps, "zvknha"); >> + case INSN_CLASS_ZVKNHB: >> + return riscv_subset_supports (rps, "zvknhb"); >> + case INSN_CLASS_ZVKNHA_OR_ZVKNHB: >> + return (riscv_subset_supports (rps, "zvknha") >> + || riscv_subset_supports (rps, "zvknhb")); > > > Looks like we only have INSN_CLASS_ZVKNHA_OR_ZVKNHB in the opcode table, = so INSN_CLASS_ZVKNHA and INSN_CLASS_ZVKNHB are redundant here. Fixed. > >> >> case INSN_CLASS_SVINVAL: >> return riscv_subset_supports (rps, "svinval"); >> case INSN_CLASS_H: >> @@ -2635,6 +2644,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subs= et_t *rps, >> return _("zvkg"); >> case INSN_CLASS_ZVKNED: >> return _("zvkned"); >> + case INSN_CLASS_ZVKNHA: >> + return _("zvknha"); >> + case INSN_CLASS_ZVKNHB: >> + return _("zvknhb"); > > > Likewise, the INSN_CLASS_ZVKNHA_OR_ZVKNHB define is lost, so I guess it w= ill return an unreachable INSN_CLASS_* internal error. Fixed. > >> >> case INSN_CLASS_SVINVAL: >> return "svinval"; >> case INSN_CLASS_H: >> diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/= zvknha.d >> new file mode 100644 >> index 00000000000..36d660f634f >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/zvknha.d >> @@ -0,0 +1,12 @@ >> +#as: -march=3Drv64gc_zvknha >> +#source: zvknha_zvknhb.s >> +#objdump: -dr >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> +0+000 <.text>: >> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 >> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 >> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 >> diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas= /riscv/zvknha_zvknhb.s >> new file mode 100644 >> index 00000000000..d20e6310531 >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s >> @@ -0,0 +1,3 @@ >> + vsha2ch.vv v4, v8, v12 >> + vsha2cl.vv v4, v8, v12 >> + vsha2ms.vv v4, v8, v12 >> diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/= zvknhb.d >> new file mode 100644 >> index 00000000000..ab0f035889e >> --- /dev/null >> +++ b/gas/testsuite/gas/riscv/zvknhb.d >> @@ -0,0 +1,12 @@ >> +#as: -march=3Drv64gc_zvknhb >> +#source: zvknha_zvknhb.s >> +#objdump: -dr >> + >> +.*:[ ]+file format .* >> + >> + >> +Disassembly of section .text: >> +0+000 <.text>: >> +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 >> +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 >> +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 >> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h >> index b8c3834b819..95c4188d084 100644 >> --- a/include/opcode/riscv-opc.h >> +++ b/include/opcode/riscv-opc.h >> @@ -2191,6 +2191,13 @@ >> #define MASK_VAESKF2_VI 0xfe00707f >> #define MATCH_VAESZ_VS 0xa603a077 >> #define MASK_VAESZ_VS 0xfe0ff07f >> +/* Zvknh[a,b] instructions. */ >> +#define MATCH_VSHA2CH_VV 0xba002077 >> +#define MASK_VSHA2CH_VV 0xfe00707f >> +#define MATCH_VSHA2CL_VV 0xbe002077 >> +#define MASK_VSHA2CL_VV 0xfe00707f >> +#define MATCH_VSHA2MS_VV 0xb6002077 >> +#define MASK_VSHA2MS_VV 0xfe00707f >> /* Svinval instruction. */ >> #define MATCH_SINVAL_VMA 0x16000073 >> #define MASK_SINVAL_VMA 0xfe007fff >> @@ -3337,6 +3344,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAE= SEM_VV) >> DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) >> DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) >> DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) >> +/* Zvknh[a,b] instructions. */ >> +DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) >> +DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) >> +DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) >> /* Vendor-specific (T-Head) XTheadBa instructions. */ >> DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) >> /* Vendor-specific (T-Head) XTheadBb instructions. */ >> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h >> index 5d55dbcedf3..77207ea79b2 100644 >> --- a/include/opcode/riscv.h >> +++ b/include/opcode/riscv.h >> @@ -418,6 +418,9 @@ enum riscv_insn_class >> INSN_CLASS_ZVBC, >> INSN_CLASS_ZVKG, >> INSN_CLASS_ZVKNED, >> + INSN_CLASS_ZVKNHA, >> + INSN_CLASS_ZVKNHB, > > > Likewise. Fixed. Thanks for pointing that out. Since this got merged, I have sent out a new patch to address this. BR, Christoph > >> >> + INSN_CLASS_ZVKNHA_OR_ZVKNHB, >> INSN_CLASS_SVINVAL, >> INSN_CLASS_ZICBOM, >> INSN_CLASS_ZICBOP, >> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c >> index 175cf5cc94f..297fda85af5 100644 >> --- a/opcodes/riscv-opc.c >> +++ b/opcodes/riscv-opc.c >> @@ -1925,6 +1925,11 @@ const struct riscv_opcode riscv_opcodes[] =3D >> {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MA= SK_VAESKF2_VI, match_opcode, 0}, >> {"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VA= ESZ_VS, match_opcode, 0}, >> >> +/* Zvknh[a,b] instructions. */ >> +{"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2= CH_VV, MASK_VSHA2CH_VV, match_opcode, 0}, >> +{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2= CL_VV, MASK_VSHA2CL_VV, match_opcode, 0}, >> +{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2= MS_VV, MASK_VSHA2MS_VV, match_opcode, 0}, >> + >> /* Supervisor instructions. */ >> {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MA= SK_RS1, match_opcode, INSN_ALIAS }, >> {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MA= SK_RD, match_opcode, INSN_ALIAS }, >> -- >> 2.41.0 >>