* [PATCH, AArch64] Fix disassembling of index register in ld/st register offset instructions
@ 2014-02-24 15:12 Yufeng Zhang
2014-02-27 12:36 ` Marcus Shawcroft
0 siblings, 1 reply; 2+ messages in thread
From: Yufeng Zhang @ 2014-02-24 15:12 UTC (permalink / raw)
To: binutils; +Cc: Marcus Shawcroft
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Hi,
This patch fixes a bug in printing the index register in the load/store
register offset instruction when the index register is of register 31.
Instead of printing [xw]31, e.g.
ldr xzr, [sp,x31,sxtx #3]
it should print the [xw]zr, e.g.
ldr xzr, [sp,xzr,sxtx #3]
The patch passes regtest on aarch64-none-elf.
OK for the trunk and 2.24 branch?
Thanks,
Yufeng
opcodes/
* aarch64-opc.c (print_register_offset_address): Call
get_int_reg_name to prepare the register name.
gas/testsuite/
* gas/aarch64/ldst-reg-reg-offset.s: Add tests.
* gas/aarch64/ldst-reg-reg-offset.d: Update.
[-- Attachment #2: patch --]
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diff --git a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d
index 486d9c8..b720633 100644
--- a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d
+++ b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d
@@ -85,3 +85,7 @@ Disassembly of section \.text:
134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\]
138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\]
13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\]
+ 140: f87ffbe1 ldr x1, \[sp,xzr,sxtx #3\]
+ 144: f83ffbe1 str x1, \[sp,xzr,sxtx #3\]
+ 148: b87fdbe1 ldr w1, \[sp,wzr,sxtw #2\]
+ 14c: b83fdbe1 str w1, \[sp,wzr,sxtw #2\]
diff --git a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s
index afa7c4d..195c830 100644
--- a/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s
+++ b/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s
@@ -86,3 +86,9 @@
func:
ld_or_st str
ld_or_st ldr
+
+ /* When the index register is of register 31, it should be ZR. */
+ ldr x1, [sp, xzr, sxtx #3]
+ str x1, [sp, xzr, sxtx #3]
+ ldr w1, [sp, wzr, sxtw #2]
+ str w1, [sp, wzr, sxtw #2]
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4313327..a84c758 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2282,9 +2282,12 @@ print_register_offset_address (char *buf, size_t size,
else
tb[0] = '\0';
- snprintf (buf, size, "[%s,%c%d%s]",
+ snprintf (buf, size, "[%s,%s%s]",
get_64bit_int_reg_name (opnd->addr.base_regno, 1),
- wm_p ? 'w' : 'x', opnd->addr.offset.regno, tb);
+ get_int_reg_name (opnd->addr.offset.regno,
+ wm_p ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X,
+ 0 /* sp_reg_p */),
+ tb);
}
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH, AArch64] Fix disassembling of index register in ld/st register offset instructions
2014-02-24 15:12 [PATCH, AArch64] Fix disassembling of index register in ld/st register offset instructions Yufeng Zhang
@ 2014-02-27 12:36 ` Marcus Shawcroft
0 siblings, 0 replies; 2+ messages in thread
From: Marcus Shawcroft @ 2014-02-27 12:36 UTC (permalink / raw)
To: Yufeng Zhang; +Cc: binutils
On 24 February 2014 15:12, Yufeng Zhang <Yufeng.Zhang@arm.com> wrote:
> opcodes/
>
> * aarch64-opc.c (print_register_offset_address): Call
> get_int_reg_name to prepare the register name.
>
> gas/testsuite/
>
> * gas/aarch64/ldst-reg-reg-offset.s: Add tests.
> * gas/aarch64/ldst-reg-reg-offset.d: Update.
This is OK for trunk and 2.24.
/Marcus
^ permalink raw reply [flat|nested] 2+ messages in thread
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2014-02-24 15:12 [PATCH, AArch64] Fix disassembling of index register in ld/st register offset instructions Yufeng Zhang
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