* [PATCH] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
@ 2021-01-05 10:00 Nelson Chu
2021-01-05 19:18 ` Jim Wilson
0 siblings, 1 reply; 2+ messages in thread
From: Nelson Chu @ 2021-01-05 10:00 UTC (permalink / raw)
To: binutils, claire, jimw, andrew, kito.cheng
From: Claire Xenia Wolf <claire@symbioticeda.com>
In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we
should update them to INSN_ALIAS when we have supported other ZB* extensions
in the future. Though we still use the [MATCH|MAKS]_[GREVI|GORCI|PACK|PACKW]
to encode them.
This patch is implemented according to the following link,
https://github.com/riscv/riscv-bitmanip/pull/101
Besides, according to this,
https://sourceware.org/pipermail/binutils/2021-January/114717.html
Jim had helped to send the email to the copyright clerk asking how to
handle the situation. So before this, I still keep the Changlog and
author as the previous patch.
2021-01-05 Claire Xenia Wolf <claire@symbioticeda.com>
Jim Wilson <jimw@sifive.com>
Maxim Blinov <maxim.blinov@embecosm.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
(riscv_parse_add_implicit_subsets): If b is set, then we regard
zba, zbb and zbc as implicit extensions.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB*.
(riscv_get_default_ext_version): Do not check the default_isa_spec when
the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_NONE.
* testsuite/gas/riscv/bitmanip-insns-32.d: New testcase.
* testsuite/gas/riscv/bitmanip-insns-64.d: Likewise.
* testsuite/gas/riscv/bitmanip-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Add MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
---
bfd/elfxx-riscv.c | 25 +++++--
gas/config/tc-riscv.c | 14 +++-
gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 ++++++++++
gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 ++++++++++++++
gas/testsuite/gas/riscv/bitmanip-insns.s | 58 +++++++++++++++
include/opcode/riscv-opc.h | 108 ++++++++++++++++++++++++++++
include/opcode/riscv.h | 4 ++
opcodes/riscv-opc.c | 69 ++++++++++++++++--
8 files changed, 359 insertions(+), 11 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d3b6472..7baf10f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1597,7 +1597,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
- "zicsr", "zifencei", NULL
+ "zicsr", "zifencei", "zba", "zbb", "zbc", NULL
};
static const char * const riscv_std_s_ext_strtab[] =
@@ -1723,7 +1723,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
riscv_subset_t *subset = NULL;
/* Add the zicsr and zifencei only when the i's version less than 2.1. */
- if ((riscv_lookup_subset (rps->subset_list, "i", &subset))
+ if (riscv_lookup_subset (rps->subset_list, "i", &subset)
&& (subset->major_version < 2
|| (subset->major_version == 2
&& subset->minor_version < 1)))
@@ -1736,7 +1736,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
RISCV_UNKNOWN_VERSION, TRUE);
}
- if ((riscv_lookup_subset (rps->subset_list, "q", &subset)))
+ if (riscv_lookup_subset (rps->subset_list, "q", &subset))
{
riscv_parse_add_subset (rps, "d",
RISCV_UNKNOWN_VERSION,
@@ -1748,7 +1748,7 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
}
- else if ((riscv_lookup_subset (rps->subset_list, "d", &subset)))
+ else if (riscv_lookup_subset (rps->subset_list, "d", &subset))
{
riscv_parse_add_subset (rps, "f",
RISCV_UNKNOWN_VERSION,
@@ -1757,12 +1757,12 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
}
- else if ((riscv_lookup_subset (rps->subset_list, "f", &subset)))
+ else if (riscv_lookup_subset (rps->subset_list, "f", &subset))
riscv_parse_add_subset (rps, "zicsr",
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
- if ((riscv_lookup_subset (rps->subset_list, "g", &subset)))
+ if (riscv_lookup_subset (rps->subset_list, "g", &subset))
{
riscv_parse_add_subset (rps, "zicsr",
RISCV_UNKNOWN_VERSION,
@@ -1771,6 +1771,19 @@ riscv_parse_add_implicit_subsets (riscv_parse_subset_t *rps)
RISCV_UNKNOWN_VERSION,
RISCV_UNKNOWN_VERSION, TRUE);
}
+
+ if (riscv_lookup_subset (rps->subset_list, "b", &subset))
+ {
+ riscv_parse_add_subset (rps, "zba",
+ RISCV_UNKNOWN_VERSION,
+ RISCV_UNKNOWN_VERSION, TRUE);
+ riscv_parse_add_subset (rps, "zbb",
+ RISCV_UNKNOWN_VERSION,
+ RISCV_UNKNOWN_VERSION, TRUE);
+ riscv_parse_add_subset (rps, "zbc",
+ RISCV_UNKNOWN_VERSION,
+ RISCV_UNKNOWN_VERSION, TRUE);
+ }
}
/* Function for parsing arch string.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e938a88..959327a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -251,6 +251,16 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZIFENCEI:
return riscv_subset_supports ("zifencei");
+ case INSN_CLASS_ZBA:
+ return riscv_subset_supports ("zba");
+ case INSN_CLASS_ZBB:
+ return riscv_subset_supports ("zbb");
+ case INSN_CLASS_ZBC:
+ return riscv_subset_supports ("zbc");
+ case INSN_CLASS_ZBA_OR_ZBB:
+ return (riscv_subset_supports ("zba")
+ || riscv_subset_supports ("zbb"));
+
default:
as_fatal ("Unreachable");
return FALSE;
@@ -296,7 +306,8 @@ riscv_get_default_ext_version (const char *name,
&& ext->name
&& strcmp (ext->name, name) == 0)
{
- if (ext->isa_spec_class == default_isa_spec)
+ if (ext->isa_spec_class == ISA_SPEC_CLASS_NONE
+ || ext->isa_spec_class == default_isa_spec)
{
*major_version = ext->major_version;
*minor_version = ext->minor_version;
@@ -1451,6 +1462,7 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bfd_boolean sign)
}
/* Expand RISC-V assembly macros into one or more instructions. */
+
static void
macro (struct riscv_cl_insn *ip, expressionS *imm_expr,
bfd_reloc_code_real_type *imm_reloc)
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-32.d b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
new file mode 100644
index 0000000..8864859
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-32.d
@@ -0,0 +1,37 @@
+#as: -march=rv32ib
+#source: bitmanip-insns.s
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+0805c533[ ]+zext.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6985d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns-64.d b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
new file mode 100644
index 0000000..a9b685d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns-64.d
@@ -0,0 +1,55 @@
+#as: -march=rv64ib -defsym __64_bit__=1
+#source: bitmanip-insns.s
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+0805c53b[ ]+zext.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6b85d513[ ]+rev8[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+2875d513[ ]+orc.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0805853b[ ]+add.uw[ ]+a0,a1,zero
+[ ]+[0-9a-f]+:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0805951b[ ]+slli.uw[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+0bf5951b[ ]+slli.uw[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+60059513[ ]+clz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60159513[ ]+ctz[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60259513[ ]+cpop[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+60459513[ ]+sext.b[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+60559513[ ]+sext.h[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+00c5c533[ ]+xor[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005d513[ ]+rori[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d513[ ]+rori[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005951b[ ]+clzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6015951b[ ]+ctzw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+6025951b[ ]+cpopw[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+63f5d513[ ]+rori[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6005d51b[ ]+roriw[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+61f5d51b[ ]+roriw[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/bitmanip-insns.s b/gas/testsuite/gas/riscv/bitmanip-insns.s
new file mode 100644
index 0000000..b14e89c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/bitmanip-insns.s
@@ -0,0 +1,58 @@
+ # pseudo/aliaese
+ zext.h a0, a1
+ rev8 a0, a1
+ orc.b a0, a1
+.ifdef __64_bit__
+ zext.w a0, a1
+.endif
+
+ # ZBA
+ sh1add a0, a1, a2
+ sh2add a0, a1, a2
+ sh3add a0, a1, a2
+.ifdef __64_bit__
+ sh1add.uw a0, a1, a2
+ sh2add.uw a0, a1, a2
+ sh3add.uw a0, a1, a2
+ add.uw a0, a1, a2
+ slli.uw a0, a1, 0
+ slli.uw a0, a1, 63
+.endif
+
+ # ZBB
+ clz a0, a1
+ ctz a0, a1
+ cpop a0, a1
+ min a0, a1, a2
+ max a0, a1, a2
+ minu a0, a1, a2
+ maxu a0, a1, a2
+ sext.b a0, a1
+ sext.h a0, a1
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xor a0, a1, a2
+ rori a0, a1, 0
+ rori a0, a1, 31
+ ror a0, a1, a2
+ ror a0, a1, 0
+ ror a0, a1, 31
+ rol a0, a1, a2
+.ifdef __64_bit__
+ clzw a0, a1
+ ctzw a0, a1
+ cpopw a0, a1
+ rori a0, a1, 63
+ ror a0, a1, 63
+ roriw a0, a1, 0
+ roriw a0, a1, 31
+ rorw a0, a1, a2
+ rorw a0, a1, 0
+ rorw a0, a1, 31
+ rolw a0, a1, a2
+.endif
+
+ # ZBC
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ clmulr a0, a1, a2
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cf55753..7dbe830 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -189,6 +189,78 @@
#define MASK_REMW 0xfe00707f
#define MATCH_REMUW 0x200703b
#define MASK_REMUW 0xfe00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI 0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI 0xfc00707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK 0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW 0xfe00707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD 0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD 0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD 0xfe00707f
+#define MATCH_SH1ADD_UW 0x2000203b
+#define MASK_SH1ADD_UW 0xfe00707f
+#define MATCH_SH2ADD_UW 0x2000403b
+#define MASK_SH2ADD_UW 0xfe00707f
+#define MATCH_SH3ADD_UW 0x2000603b
+#define MASK_SH3ADD_UW 0xfe00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW 0xfe00707f
+#define MATCH_SLLI_UW 0x800101b
+#define MASK_SLLI_UW 0xfc00707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ 0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ 0xfff0707f
+#define MATCH_CPOP 0x60201013
+#define MASK_CPOP 0xfff0707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN 0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX 0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU 0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU 0xfe00707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B 0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H 0xfff0707f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN 0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN 0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR 0xfe00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI 0xfc00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR 0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL 0xfe00707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW 0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW 0xfff0707f
+#define MATCH_CPOPW 0x6020101b
+#define MASK_CPOPW 0xfff0707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW 0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW 0xfe00707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW 0xfe00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL 0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH 0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR 0xfe00707f
#define MATCH_AMOADD_W 0x202f
#define MASK_AMOADD_W 0xf800707f
#define MATCH_AMOXOR_W 0x2000202f
@@ -927,6 +999,42 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
+DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
+DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
+DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index d491f45..b35069c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -311,6 +311,10 @@ enum riscv_insn_class
INSN_CLASS_D_AND_C,
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
+ INSN_CLASS_ZBA,
+ INSN_CLASS_ZBB,
+ INSN_CLASS_ZBC,
+ INSN_CLASS_ZBA_OR_ZBB,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cb0ebd3..2ade8af 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -56,6 +56,16 @@ const char * const riscv_fpr_names_abi[NFPR] = {
"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
};
+/* The MATCH/MASK immediate macros for rvb pseudo instructions. */
+
+#define MASK_RVB_IMM (OP_MASK_SHAMT << OP_SH_SHAMT)
+
+#define ENCODE_PERM_IMM(xlen, prefix, suffix) \
+ (ENCODE_ITYPE_IMM ((((xlen) - 1) & (((xlen) - 1) << (prefix)) & (suffix))))
+
+#define MATCH_PERM8_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 3, -1))
+#define MATCH_PERMB_IMM(xlen) (ENCODE_PERM_IMM ((xlen), 0, 0x7))
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -238,10 +248,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
{"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
{"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
-{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
{"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI | ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
{"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
{"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
{"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
@@ -374,7 +381,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
-{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS },
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
@@ -502,6 +508,55 @@ const struct riscv_opcode riscv_opcodes[] =
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
{"remuw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
+/* Bitmanip instruction subset - ZBA/ZBB/ZBC */
+{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
+{"sh1add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
+{"sh2add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
+{"sh3add.uw",64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
+{"zext.w", 64, INSN_CLASS_ZBA_OR_ZBB, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
+{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
+{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
+{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
+
+{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
+{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
+{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
+{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
+{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
+{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
+{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
+{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
+{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
+{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 }, /* INSN_ALIAS of pack */
+{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 }, /* INSN_ALIAS of packw */
+{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
+{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, INSN_ALIAS },
+{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (32), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 }, /* INSN_ALIAS of grevi */
+{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_PERM8_IMM (64), MASK_GREVI | MASK_RVB_IMM, match_opcode, 0 }, /* INSN_ALIAS of grevi */
+{"orc.b", 32, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (32), MASK_GORCI | MASK_RVB_IMM, match_opcode, 0 }, /* INSN_ALIAS of gorci */
+{"orc.b", 64, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_PERMB_IMM (64), MASK_GORCI | MASK_RVB_IMM, match_opcode, 0 }, /* INSN_ALIAS of gorci */
+
+{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+
/* Single-precision floating-point instruction subset */
{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
@@ -926,12 +981,18 @@ const struct riscv_ext_version riscv_ext_version_table[] =
{"c", ISA_SPEC_CLASS_20190608, 2, 0},
{"c", ISA_SPEC_CLASS_2P2, 2, 0},
+{"b", ISA_SPEC_CLASS_NONE, 0, 93},
+
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0},
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+{"zba", ISA_SPEC_CLASS_NONE, 0, 93},
+{"zbb", ISA_SPEC_CLASS_NONE, 0, 93},
+{"zbc", ISA_SPEC_CLASS_NONE, 0, 93},
+
/* Terminate the list. */
{NULL, 0, 0, 0}
};
--
2.7.4
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93).
2021-01-05 10:00 [PATCH] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93) Nelson Chu
@ 2021-01-05 19:18 ` Jim Wilson
0 siblings, 0 replies; 2+ messages in thread
From: Jim Wilson @ 2021-01-05 19:18 UTC (permalink / raw)
To: Nelson Chu
Cc: Binutils, Clifford Wolf, Andrew Waterman, Kito Cheng, Maxim Blinov
You dropped the -menable-experimental-extensions option. You are allowing
zba/zbb/zbc support without explicit versions. And you are mapping B to
zba/zbb/zbc. Are you sure we want to do that? Just because it is "frozen"
doesn't mean that it won't change again. It just means it is less likely
to change again.
I'm also concerned about the number of changes being made to the B spec
right before the Binutils release branch is made. Some of these changes
just came through on Monday this week. That isn't enough time for
simulator support and cross checking the assembler against the simulator to
verify it. So do we really want to ship an assembler with an untested
unverified B extension implementation? Without the
-menable-experimental-extensions option? This could come back and bite us
in the future if we find bugs, or people design hardware using this
"frozen" implementation and the final one turns out to be different.
Jim
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-01-05 19:18 UTC | newest]
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2021-01-05 10:00 [PATCH] RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93) Nelson Chu
2021-01-05 19:18 ` Jim Wilson
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