From: Jim Wilson <jimw@sifive.com>
To: Nelson Chu <nelson.chu@sifive.com>
Cc: Binutils <binutils@sourceware.org>, Alan Modra <amodra@gmail.com>,
Nick Clifton <nickc@redhat.com>,
Kito Cheng <kito.cheng@sifive.com>,
Andrew Waterman <andrew@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Simon Cook <simon.cook@embecosm.com>,
Jeremy Bennett <jeremy.bennett@embecosm.com>
Subject: Re: [Integration 0/6] RISC-V: The prototype of the integration and working branches for binutils.
Date: Tue, 30 Mar 2021 16:16:12 -0700 [thread overview]
Message-ID: <CAFyWVaaAx+c4BV4xX3ZL4_d9up0uGe9mjDNEQ4NKFHc2Udnx+w@mail.gmail.com> (raw)
In-Reply-To: <1617097017-16776-1-git-send-email-nelson.chu@sifive.com>
On Tue, Mar 30, 2021 at 2:37 AM Nelson Chu <nelson.chu@sifive.com> wrote:
> RISC-V GNU binutils will have another two FSF develop branches to let
> developers can contribute their works, but these works are not ratified
> yet, so they aren't allowed to merge into mainline. The two branches are
> integration branch and working branch. The series of patches are the
> prototypes for these two develop branches, and they won't be applied to
> the mainline. Please see the details in the comments of the patches,
> and feels free to share any thought and suggestion, if you are interested.
>
The series looks OK to me. I made some minor comments, other than the Zfh
fcvt.q.h and fcvt.h.q which I think are broken and need to be fixed.
Jim
next prev parent reply other threads:[~2021-03-30 23:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-30 9:36 Nelson Chu
2021-03-30 9:36 ` [Integration 1/6] RISC-V/extended: Add extended extension hooks when parsing architecture string Nelson Chu
2021-03-30 22:46 ` Jim Wilson
2021-03-30 9:36 ` [Integration 2/6] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions Nelson Chu
2021-03-30 22:53 ` Jim Wilson
2021-03-30 9:36 ` [Integration 3/6] RISC-V/sifive: Add sifive cache control instructions Nelson Chu
2021-03-30 22:56 ` Jim Wilson
2021-03-30 9:36 ` [Integration 4/6] RISC-V/rvv: Add rvv v0.10 instructions Nelson Chu
2021-03-30 9:36 ` [Integration 5/6] RISC-V/zfh: Add half-precision floating-point v0.1 instructions Nelson Chu
2021-03-30 23:09 ` Jim Wilson
2021-04-06 2:01 ` Nelson Chu
2021-03-30 9:36 ` [Integration 6/6] RISC-V/zfh: Support .float16 directive for assembler Nelson Chu
2021-03-30 23:14 ` Jim Wilson
2021-03-30 23:16 ` Jim Wilson [this message]
2021-04-16 2:32 ` [Integration 0/6] RISC-V: The prototype of the integration and working branches for binutils Nelson Chu
2021-04-20 19:10 ` Jim Wilson
2021-04-20 21:07 ` Mike Frysinger
2021-04-22 1:39 ` Nelson Chu
2021-04-22 1:27 ` Nelson Chu
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