* [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
@ 2019-12-16 5:21 ` Nelson Chu
2020-01-03 1:32 ` [PING] " Nelson Chu
2020-02-01 3:08 ` Jim Wilson
2019-12-16 5:21 ` [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12 Nelson Chu
` (3 subsequent siblings)
5 siblings, 2 replies; 25+ messages in thread
From: Nelson Chu @ 2019-12-16 5:21 UTC (permalink / raw)
To: binutils
Add new .option `csrcheck/nocsrcheck` and GAS option `-mcsrcheck/-mno-csrcheck`
to enbale/disable the CSR checking. Disable the CSR checking by default.
gas/
* config/tc-riscv.c: Add new .option and GAS options to enbale/disable
the CSR checking. We disable the CSR checking by default.
(riscv_ip, reg_lookup_internal): Check the `riscv_opts.csrcheck`
before we doing the CSR checking.
* doc/c-riscv.texi: Add description for the new .option and assembler
options.
* testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsrcheck` to enable
the CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
---
gas/config/tc-riscv.c | 23 +++++++++++++++++++++-
gas/doc/c-riscv.texi | 13 ++++++++++++
gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
.../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
6 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 592864b..9c6cde0 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -83,6 +83,7 @@ struct riscv_set_options
int rve; /* Generate RVE code. */
int relax; /* Emit relocs the linker is allowed to relax. */
int arch_attr; /* Emit arch attribute. */
+ int csrcheck; /* Enable the CSR checking. */
};
static struct riscv_set_options riscv_opts =
@@ -92,6 +93,7 @@ static struct riscv_set_options riscv_opts =
0, /* rve */
1, /* relax */
DEFAULT_RISCV_ATTR, /* arch_attr */
+ 0. /* csrcheck */
};
static void
@@ -566,7 +568,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
return -1;
- if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
+ if (class == RCLASS_CSR
+ && riscv_opts.csrcheck
+ && !reg_csr_lookup_internal (s))
return -1;
return DECODE_REG_NUM (r);
@@ -1590,6 +1594,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
/* Check if we write a read-only CSR by the CSR
instruction. */
if (insn_with_csr
+ && riscv_opts.csrcheck
&& !riscv_csr_read_only_check (ip->insn_opcode))
{
/* Don't parse the next insn in the riscv_opcode.
@@ -2328,6 +2333,8 @@ enum options
OPTION_NO_RELAX,
OPTION_ARCH_ATTR,
OPTION_NO_ARCH_ATTR,
+ OPTION_CSR_CHECK,
+ OPTION_NO_CSR_CHECK,
OPTION_END_OF_ENUM
};
@@ -2342,6 +2349,8 @@ struct option md_longopts[] =
{"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
{"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
{"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
+ {"mcsrcheck", no_argument, NULL, OPTION_CSR_CHECK},
+ {"mno-csrcheck", no_argument, NULL, OPTION_NO_CSR_CHECK},
{NULL, no_argument, NULL, 0}
};
@@ -2420,6 +2429,14 @@ md_parse_option (int c, const char *arg)
riscv_opts.arch_attr = FALSE;
break;
+ case OPTION_CSR_CHECK:
+ riscv_opts.csrcheck = TRUE;
+ break;
+
+ case OPTION_NO_CSR_CHECK:
+ riscv_opts.csrcheck = FALSE;
+ break;
+
default:
return 0;
}
@@ -2812,6 +2829,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
riscv_opts.relax = TRUE;
else if (strcmp (name, "norelax") == 0)
riscv_opts.relax = FALSE;
+ else if (strcmp (name, "csrcheck") == 0)
+ riscv_opts.csrcheck = TRUE;
+ else if (strcmp (name, "nocsrcheck") == 0)
+ riscv_opts.csrcheck = FALSE;
else if (strcmp (name, "push") == 0)
{
struct riscv_option_stack *s;
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 9bc8c82..644e332 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -59,6 +59,15 @@ required to materialize symbol addresses. (default)
@item -mno-relax
Don't do linker relaxations.
+@cindex @samp{-mcsrcheck} option, RISC-V
+@item -mcsrcheck
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set. The
+read-only CSR can not be written by the CSR instructions.
+
+@cindex @samp{-mno-csrcheck} option, RISC-V
+@item -mno-csrcheck
+Don't do CSR cheching.
@end table
@c man end
@@ -160,6 +169,10 @@ opportunistically relax some code sequences, but sometimes this behavior is not
desirable.
@end table
+@item csrcheck
+@itemx nocsrcheck
+Enables or disables the CSR checking.
+
@cindex INSN directives
@item .insn @var{value}
@itemx .insn @var{value}
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
index 4c27f47..2b9faeb 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -1,3 +1,3 @@
-#as: -march=rv32i
+#as: -march=rv32i -mcsrcheck
#source: priv-reg-all.s
#error_output: priv-reg-fail-fext.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
index 9c93d8a..72ff57b 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if
+#as: -march=rv32if -mcsrcheck
#source: priv-reg-fail-read-only-01.s
#error_output: priv-reg-fail-read-only-01.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
index ede45c5..22ad2da 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -1,3 +1,3 @@
-#as: -march=rv32if
+#as: -march=rv32if -mcsrcheck
#source: priv-reg-fail-read-only-02.s
#error_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
index 88038bd..e45337f 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -1,3 +1,3 @@
-#as: -march=rv64if
+#as: -march=rv64if -mcsrcheck
#source: priv-reg-all.s
#error_output: priv-reg-fail-rv32-only.l
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
@ 2019-12-16 5:21 Nelson Chu
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
` (5 more replies)
0 siblings, 6 replies; 25+ messages in thread
From: Nelson Chu @ 2019-12-16 5:21 UTC (permalink / raw)
To: binutils
Dear Palmer,
I'm on the master branch, but failed to notice that my internal build environment
add the --disable-gdb configure option to disable the GDB build. I'm really sorry
for this. After attaching the v3 patches, I can build riscv-gdb now. However,
the csr checking only work for the assembler so far. I extend the DECLARE_CSR
to record more informaton (`class`), but these information are unused in GDB.
Therefore, I just fix the GDB build failed by allowing more arguments for
DECLARE_CSR.
Thanks and best regards
Nelson
Fix the build failed for GDB.
* [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
Same as the previous one.
* [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
Upadte the gdb/riscv-tdep.h and gdb/riscv-tdep.c since the DECLARE_CSR is changed.
* [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
Same as the previous one.
* [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
Same as the previous one.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
@ 2019-12-16 5:21 ` Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 2:38 ` Jim Wilson
2019-12-16 5:21 ` [PATCH v3 4/4] RISC-V: Disable the CSR checking by default Nelson Chu
` (4 subsequent siblings)
5 siblings, 2 replies; 25+ messages in thread
From: Nelson Chu @ 2019-12-16 5:21 UTC (permalink / raw)
To: binutils
CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR
when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address
is 0x3. The read-only CSR can not be written by the CSR instructions.
gas/
* config/tc-riscv.c (insn_with_csr): New boolean to indicate we are
assembling instruction with CSR.
(enum csr_insn_type): New enum is used to classify the CSR instruction.
(riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
are used to check if we write a read-only CSR by the CSR instruction.
(riscv_ip): Call riscv_csr_read_only_check after parsing all arguments.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
all CSR for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
all CSR instructions for the read-only CSR checking.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
---
gas/config/tc-riscv.c | 65 +++++
.../gas/riscv/priv-reg-fail-read-only-01.d | 3 +
.../gas/riscv/priv-reg-fail-read-only-01.l | 69 +++++
.../gas/riscv/priv-reg-fail-read-only-01.s | 295 +++++++++++++++++++++
.../gas/riscv/priv-reg-fail-read-only-02.d | 3 +
.../gas/riscv/priv-reg-fail-read-only-02.l | 25 ++
.../gas/riscv/priv-reg-fail-read-only-02.s | 90 +++++++
7 files changed, 550 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 4c9ff52..592864b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -195,6 +195,9 @@ static bfd_boolean start_assemble = FALSE;
/* Indicate arch attribute is explictly set. */
static bfd_boolean explicit_arch_attr = FALSE;
+/* Indicate we are assembling instruction with CSR. */
+static bfd_boolean insn_with_csr = FALSE;
+
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
@@ -1473,6 +1476,52 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
return FALSE;
}
+enum csr_insn_type
+{
+ INSN_NOT_CSR,
+ INSN_CSRRW,
+ INSN_CSRRS,
+ INSN_CSRRC
+};
+
+static enum csr_insn_type
+riscv_csr_insn_type (insn_t insn)
+{
+ if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
+ || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
+ return INSN_CSRRW;
+ else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
+ || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
+ return INSN_CSRRS;
+ else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
+ || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
+ return INSN_CSRRC;
+ else
+ return INSN_NOT_CSR;
+}
+
+/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
+ CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
+ CSR address is 0x3. */
+
+static bfd_boolean
+riscv_csr_read_only_check (insn_t insn)
+{
+ int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
+ int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
+ int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
+ enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
+
+ if (readonly
+ && (((csr_insn == INSN_CSRRS
+ || csr_insn == INSN_CSRRC)
+ && rs1 != 0)
+ || csr_insn == INSN_CSRRW))
+ return FALSE;
+
+ return TRUE;
+}
+
/* This routine assembles an instruction into its binary format. As a
side effect, it sets the global variable imm_reloc to the type of
relocation to do if one of the operands is an address expression. */
@@ -1537,11 +1586,25 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
: insn->match) == 2
&& !riscv_opts.rvc)
break;
+
+ /* Check if we write a read-only CSR by the CSR
+ instruction. */
+ if (insn_with_csr
+ && !riscv_csr_read_only_check (ip->insn_opcode))
+ {
+ /* Don't parse the next insn in the riscv_opcode.
+ Otherwise, we will get multiple unexpected error
+ message. */
+ error = _("Read-only CSR is used");
+ insn_with_csr = FALSE;
+ goto out;
+ }
}
if (*s != '\0')
break;
/* Successful assembly. */
error = NULL;
+ insn_with_csr = FALSE;
goto out;
case 'C': /* RVC */
@@ -1886,6 +1949,7 @@ rvc_lui:
continue;
case 'E': /* Control register. */
+ insn_with_csr = TRUE;
if (reg_lookup (&s, RCLASS_CSR, ®no))
INSERT_OPERAND (CSR, *ip, regno);
else
@@ -2206,6 +2270,7 @@ jump:
}
s = argsStart;
error = _("illegal operands");
+ insn_with_csr = FALSE;
}
out:
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
new file mode 100644
index 0000000..9c93d8a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if
+#source: priv-reg-fail-read-only-01.s
+#error_output: priv-reg-fail-read-only-01.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
new file mode 100644
index 0000000..43beeb7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
@@ -0,0 +1,69 @@
+.*Assembler messages:
+.*Error: Read-only CSR is used `csrw cycle,a1'
+.*Error: Read-only CSR is used `csrw time,a1'
+.*Error: Read-only CSR is used `csrw instret,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter3,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter4,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter5,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter6,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter7,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter8,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter9,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter10,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter11,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter12,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter13,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter14,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter15,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter16,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter17,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter18,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter19,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter20,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter21,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter22,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter23,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter24,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter25,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter26,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter27,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter28,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter29,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter30,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter31,a1'
+.*Error: Read-only CSR is used `csrw cycleh,a1'
+.*Error: Read-only CSR is used `csrw timeh,a1'
+.*Error: Read-only CSR is used `csrw instreth,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter3h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter4h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter5h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter6h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter7h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter8h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter9h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter10h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter11h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter12h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter13h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter14h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter15h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter16h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter17h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter18h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter19h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter20h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter21h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter22h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter23h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter24h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter25h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter26h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter27h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter28h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter29h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter30h,a1'
+.*Error: Read-only CSR is used `csrw hpmcounter31h,a1'
+.*Error: Read-only CSR is used `csrw mvendorid,a1'
+.*Error: Read-only CSR is used `csrw marchid,a1'
+.*Error: Read-only CSR is used `csrw mimpid,a1'
+.*Error: Read-only CSR is used `csrw mhartid,a1'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
new file mode 100644
index 0000000..9e8937a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
@@ -0,0 +1,295 @@
+# From priv spec 1.9.1 to 1.12 registers.
+
+ .macro csr val
+ csrw \val, a1
+ .endm
+
+# User-Level CSR Addresses in 1.12.
+ csr ustatus
+ csr uie
+ csr utvec
+
+ csr uscratch
+ csr uepc
+ csr ucause
+ csr utval
+ csr uip
+
+ csr fflags
+ csr frm
+ csr fcsr
+
+ csr cycle
+ csr time
+ csr instret
+ csr hpmcounter3
+ csr hpmcounter4
+ csr hpmcounter5
+ csr hpmcounter6
+ csr hpmcounter7
+ csr hpmcounter8
+ csr hpmcounter9
+ csr hpmcounter10
+ csr hpmcounter11
+ csr hpmcounter12
+ csr hpmcounter13
+ csr hpmcounter14
+ csr hpmcounter15
+ csr hpmcounter16
+ csr hpmcounter17
+ csr hpmcounter18
+ csr hpmcounter19
+ csr hpmcounter20
+ csr hpmcounter21
+ csr hpmcounter22
+ csr hpmcounter23
+ csr hpmcounter24
+ csr hpmcounter25
+ csr hpmcounter26
+ csr hpmcounter27
+ csr hpmcounter28
+ csr hpmcounter29
+ csr hpmcounter30
+ csr hpmcounter31
+ csr cycleh
+ csr timeh
+ csr instreth
+ csr hpmcounter3h
+ csr hpmcounter4h
+ csr hpmcounter5h
+ csr hpmcounter6h
+ csr hpmcounter7h
+ csr hpmcounter8h
+ csr hpmcounter9h
+ csr hpmcounter10h
+ csr hpmcounter11h
+ csr hpmcounter12h
+ csr hpmcounter13h
+ csr hpmcounter14h
+ csr hpmcounter15h
+ csr hpmcounter16h
+ csr hpmcounter17h
+ csr hpmcounter18h
+ csr hpmcounter19h
+ csr hpmcounter20h
+ csr hpmcounter21h
+ csr hpmcounter22h
+ csr hpmcounter23h
+ csr hpmcounter24h
+ csr hpmcounter25h
+ csr hpmcounter26h
+ csr hpmcounter27h
+ csr hpmcounter28h
+ csr hpmcounter29h
+ csr hpmcounter30h
+ csr hpmcounter31h
+
+# Supervisor-level CSR Addresses in 1.12.
+ csr sstatus
+ csr sedeleg
+ csr sideleg
+ csr sie
+ csr stvec
+ csr scounteren
+
+ csr sscratch
+ csr sepc
+ csr scause
+ csr stval
+ csr sip
+
+ csr satp
+
+# Hypervisor-Level CSR Addresses in 1.12.
+ csr hstatus
+ csr hedeleg
+ csr hideleg
+ csr hcounteren
+
+ csr hgatp
+
+ csr htimedelta
+ csr htimedeltah
+
+ csr vsstatus
+ csr vsie
+ csr vstvec
+ csr vsscratch
+ csr vsepc
+ csr vscause
+ csr vstval
+ csr vsip
+ csr vsatp
+
+# Machine-Level CSR Addresses in 1.12.
+ csr mvendorid
+ csr marchid
+ csr mimpid
+ csr mhartid
+
+ csr mstatus
+ csr misa
+ csr medeleg
+ csr mideleg
+ csr mie
+ csr mtvec
+ csr mcounteren
+ csr mstatush
+
+ csr mscratch
+ csr mepc
+ csr mcause
+ csr mtval
+ csr mip
+
+ csr pmpcfg0
+ csr pmpcfg1
+ csr pmpcfg2
+ csr pmpcfg3
+ csr pmpaddr0
+ csr pmpaddr1
+ csr pmpaddr2
+ csr pmpaddr3
+ csr pmpaddr4
+ csr pmpaddr5
+ csr pmpaddr6
+ csr pmpaddr7
+ csr pmpaddr8
+ csr pmpaddr9
+ csr pmpaddr10
+ csr pmpaddr11
+ csr pmpaddr12
+ csr pmpaddr13
+ csr pmpaddr14
+ csr pmpaddr15
+
+ csr mcycle
+ csr minstret
+ csr mhpmcounter3
+ csr mhpmcounter4
+ csr mhpmcounter5
+ csr mhpmcounter6
+ csr mhpmcounter7
+ csr mhpmcounter8
+ csr mhpmcounter9
+ csr mhpmcounter10
+ csr mhpmcounter11
+ csr mhpmcounter12
+ csr mhpmcounter13
+ csr mhpmcounter14
+ csr mhpmcounter15
+ csr mhpmcounter16
+ csr mhpmcounter17
+ csr mhpmcounter18
+ csr mhpmcounter19
+ csr mhpmcounter20
+ csr mhpmcounter21
+ csr mhpmcounter22
+ csr mhpmcounter23
+ csr mhpmcounter24
+ csr mhpmcounter25
+ csr mhpmcounter26
+ csr mhpmcounter27
+ csr mhpmcounter28
+ csr mhpmcounter29
+ csr mhpmcounter30
+ csr mhpmcounter31
+ csr mcycleh
+ csr minstreth
+ csr mhpmcounter3h
+ csr mhpmcounter4h
+ csr mhpmcounter5h
+ csr mhpmcounter6h
+ csr mhpmcounter7h
+ csr mhpmcounter8h
+ csr mhpmcounter9h
+ csr mhpmcounter10h
+ csr mhpmcounter11h
+ csr mhpmcounter12h
+ csr mhpmcounter13h
+ csr mhpmcounter14h
+ csr mhpmcounter15h
+ csr mhpmcounter16h
+ csr mhpmcounter17h
+ csr mhpmcounter18h
+ csr mhpmcounter19h
+ csr mhpmcounter20h
+ csr mhpmcounter21h
+ csr mhpmcounter22h
+ csr mhpmcounter23h
+ csr mhpmcounter24h
+ csr mhpmcounter25h
+ csr mhpmcounter26h
+ csr mhpmcounter27h
+ csr mhpmcounter28h
+ csr mhpmcounter29h
+ csr mhpmcounter30h
+ csr mhpmcounter31h
+
+ csr mcountinhibit
+ csr mhpmevent3
+ csr mhpmevent4
+ csr mhpmevent5
+ csr mhpmevent6
+ csr mhpmevent7
+ csr mhpmevent8
+ csr mhpmevent9
+ csr mhpmevent10
+ csr mhpmevent11
+ csr mhpmevent12
+ csr mhpmevent13
+ csr mhpmevent14
+ csr mhpmevent15
+ csr mhpmevent16
+ csr mhpmevent17
+ csr mhpmevent18
+ csr mhpmevent19
+ csr mhpmevent20
+ csr mhpmevent21
+ csr mhpmevent22
+ csr mhpmevent23
+ csr mhpmevent24
+ csr mhpmevent25
+ csr mhpmevent26
+ csr mhpmevent27
+ csr mhpmevent28
+ csr mhpmevent29
+ csr mhpmevent30
+ csr mhpmevent31
+
+ csr tselect
+ csr tdata1
+ csr tdata2
+ csr tdata3
+
+ csr dcsr
+ csr dpc
+ csr dscratch0
+ csr dscratch1
+
+# Defined in 1.9.1, but alias for another CSR in 1.12.
+ csr ubadaddr # utval
+ csr sbadaddr # stval
+ csr sptbr # satp
+ csr hie # vsie
+ csr htvec # vstvec
+ csr hscratch # vsscratch
+ csr hepc # vsepc
+ csr hcause # vscause
+ csr hbadaddr # vstval
+ csr hip # vsip
+ csr mbadaddr # mtval
+ csr mucounteren # mcountinhibit
+
+# Defined in 1.9.1, but dropped in 1.10.
+ csr mscounteren
+ csr mhcounteren
+ csr mbase
+ csr mbound
+ csr mibase
+ csr mibound
+ csr mdbase
+ csr mdbound
+
+# Defined in 1.10, but dropped in 1.12.
+ csr dscratch # dscratch0
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
new file mode 100644
index 0000000..ede45c5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
@@ -0,0 +1,3 @@
+#as: -march=rv32if
+#source: priv-reg-fail-read-only-02.s
+#error_output: priv-reg-fail-read-only-02.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
new file mode 100644
index 0000000..dce8e0e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
@@ -0,0 +1,25 @@
+.*Assembler messages:
+.*Error: Read-only CSR is used `csrrw a0,cycle,a1'
+.*Error: Read-only CSR is used `csrrw a0,cycle,zero'
+.*Error: Read-only CSR is used `csrrw zero,cycle,a1'
+.*Error: Read-only CSR is used `csrrw zero,cycle,zero'
+.*Error: Read-only CSR is used `csrw cycle,a1'
+.*Error: Read-only CSR is used `csrw cycle,zero'
+.*Error: Read-only CSR is used `csrrwi a0,cycle,0xb'
+.*Error: Read-only CSR is used `csrrwi a0,cycle,0x0'
+.*Error: Read-only CSR is used `csrrwi zero,cycle,0xb'
+.*Error: Read-only CSR is used `csrrwi zero,cycle,0x0'
+.*Error: Read-only CSR is used `csrwi cycle,0xb'
+.*Error: Read-only CSR is used `csrwi cycle,0x0'
+.*Error: Read-only CSR is used `csrrs a0,cycle,a1'
+.*Error: Read-only CSR is used `csrrs zero,cycle,a1'
+.*Error: Read-only CSR is used `csrs cycle,a0'
+.*Error: Read-only CSR is used `csrrsi a0,cycle,0xb'
+.*Error: Read-only CSR is used `csrrsi zero,cycle,0xb'
+.*Error: Read-only CSR is used `csrsi cycle,0xb'
+.*Error: Read-only CSR is used `csrrc a0,cycle,a1'
+.*Error: Read-only CSR is used `csrrc zero,cycle,a1'
+.*Error: Read-only CSR is used `csrc cycle,a0'
+.*Error: Read-only CSR is used `csrrci a0,cycle,0xb'
+.*Error: Read-only CSR is used `csrrci zero,cycle,0xb'
+.*Error: Read-only CSR is used `csrci cycle,0xb'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
new file mode 100644
index 0000000..7afb26e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
@@ -0,0 +1,90 @@
+# CSRRW and CSRRWI always write CSR
+# CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when rs isn't zero.
+
+# csrrw rd, csr, rs
+ csrrw a0, ustatus, a1
+ csrrw a0, cycle, a1
+ csrrw a0, cycle, zero
+ csrrw zero, cycle, a1
+ csrrw zero, cycle, zero
+ fscsr a0, a1
+ fsrm a0, a1
+ fsflags a0, a1
+# csrrw zero, csr, rs
+ csrw ustatus, a1
+ csrw cycle, a1
+ csrw cycle, zero
+ fscsr a1
+ fsrm a1
+ fsflags a1
+# csrrwi rd, csr, imm
+ csrrwi a0, ustatus, 0xb
+ csrrwi a0, cycle, 0xb
+ csrrwi a0, cycle, 0x0
+ csrrwi zero, cycle, 0xb
+ csrrwi zero, cycle, 0x0
+# csrrwi zero, csr, imm
+ csrwi ustatus, 0xb
+ csrwi cycle, 0xb
+ csrwi cycle, 0x0
+
+# csrrs rd, csr, rs
+ csrrs a0, ustatus, a1
+ csrrs a0, cycle, a1
+ csrrs a0, cycle, zero
+ csrrs zero, cycle, a1
+ csrrs zero, cycle, zero
+# csrrs rd, csr, zero
+ csrr a0, ustatus
+ csrr a0, cycle
+ csrr zero, cycle
+ rdinstret a0
+ rdinstret zero
+ rdinstreth a0
+ rdinstreth zero
+ rdcycle a0
+ rdcycle zero
+ rdcycleh a0
+ rdcycleh zero
+ rdtime a0
+ rdtime zero
+ rdtimeh a0
+ rdtimeh zero
+ frcsr a0
+ frrm a0
+ frflags a0
+# csrrs zero, csr, rs
+ csrs ustatus, a0
+ csrs cycle, a0
+ csrs cycle, zero
+# csrrsi rd, csr, imm
+ csrrsi a0, ustatus, 0xb
+ csrrsi a0, cycle, 0xb
+ csrrsi a0, cycle, 0x0
+ csrrsi zero, cycle, 0xb
+ csrrsi zero, cycle, 0x0
+# csrrsi zero, csr, imm
+ csrsi ustatus, 0xb
+ csrsi cycle, 0xb
+ csrsi cycle, 0x0
+
+# csrrc a0, csr, a1
+ csrrc a0, ustatus, a1
+ csrrc a0, cycle, a1
+ csrrc a0, cycle, zero
+ csrrc zero, cycle, a1
+ csrrc zero, cycle, zero
+# csrrc zero, csr, rs
+ csrc ustatus, a0
+ csrc cycle, a0
+ csrc cycle, zero
+# csrrci rd, csr, imm
+ csrrci a0, ustatus, 0xb
+ csrrci a0, cycle, 0xb
+ csrrci a0, cycle, 0x0
+ csrrci zero, cycle, 0xb
+ csrrci zero, cycle, 0x0
+# csrrci zero, csr, imm
+ csrci ustatus, 0xb
+ csrci cycle, 0xb
+ csrci cycle, 0x0
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
` (2 preceding siblings ...)
2019-12-16 5:21 ` [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12 Nelson Chu
@ 2019-12-16 5:21 ` Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 1:27 ` Jim Wilson
2020-01-03 1:29 ` [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
2020-01-22 21:35 ` Palmer Dabbelt via binutils
5 siblings, 2 replies; 25+ messages in thread
From: Nelson Chu @ 2019-12-16 5:21 UTC (permalink / raw)
To: binutils
According to the riscv privilege spec, some CSR are only valid when rv32 or
the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
to record more informaton we need, and then check whether the CSR is valid
according to these information.
gas/
* config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
whether or not this CSR is legal in the current ISA string.
(riscv_csr_extra): New structure to hold all extra information of CSR.
(riscv_init_csr_hash): New function. According to the DECLARE_CSR and
DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
Call hash_reg_name to insert CSR address into reg_names_hash.
(md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
(reg_csr_lookup_internal, riscv_csr_class_check): New functions.
Decide whether the CSR is valid according to the `csr_extra_hash`.
* testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
file is `priv-reg-all.s`, and the ISA is rv32i without f-ext, so the
f-ext CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
source file is `priv-reg-all.s`, and the ISA is rv64if, so the
rv32-only CSR are not allowed.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
include/
* opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
record riscv_csr_class.
opcodes/
* riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
gdb/
* riscv-tdep.c: Updated since the DECLARE_CSR is changed.
* riscv-tdep.h: Likewise.
* features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
rv32-only CSR.
* features/riscv/64bit-csr.xml: Regernated.
binutils/
* dwarf.c: Updated since the DECLARE_CSR is changed.
---
binutils/dwarf.c | 2 +-
gas/config/tc-riscv.c | 88 +++-
gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 +
gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 4 +
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 +
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 +++
gdb/features/riscv/64bit-csr.xml | 67 ---
gdb/features/riscv/rebuild-csr-xml.sh | 10 +-
gdb/riscv-tdep.c | 6 +-
gdb/riscv-tdep.h | 2 +-
include/opcode/riscv-opc.h | 522 +++++++++++-----------
opcodes/riscv-dis.c | 2 +-
12 files changed, 436 insertions(+), 341 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index 06ef1f7..d7d1e14 100644
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -7609,7 +7609,7 @@ regname_internal_riscv (unsigned int regno)
document. */
switch (regno)
{
-#define DECLARE_CSR(NAME,VALUE) case VALUE + 4096: name = #NAME; break;
+#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 7ec1028..4c9ff52 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -455,6 +455,7 @@ enum reg_class
};
static struct hash_control *reg_names_hash = NULL;
+static struct hash_control *csr_extra_hash = NULL;
#define ENCODE_REG_HASH(cls, n) \
((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
@@ -480,6 +481,77 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
hash_reg_name (class, names[i], i);
}
+/* All RISC-V CSRs belong to one of these classes. */
+
+enum riscv_csr_class
+{
+ CSR_CLASS_NONE,
+
+ CSR_CLASS_I,
+ CSR_CLASS_I_32, /* rv32 only */
+ CSR_CLASS_F, /* f-ext only */
+};
+
+/* This structure holds all restricted conditions for a CSR. */
+
+typedef struct
+{
+ /* Class to which this CSR belongs. Used to decide whether or
+ not this CSR is legal in the current -march context. */
+ enum riscv_csr_class csr_class;
+} riscv_csr_extra;
+
+/* Init two hashes for CSR. */
+
+static void
+riscv_init_csr_hashes (const char *name,
+ unsigned address,
+ enum riscv_csr_class class)
+{
+ riscv_csr_extra *entry = XNEW (riscv_csr_extra);
+ entry->csr_class = class;
+
+ const char *hash_error =
+ hash_insert (csr_extra_hash, name, (void *) entry);
+ if (hash_error)
+ {
+ fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
+ name, hash_error);
+ /* Probably a memory allocation problem? Give up now. */
+ as_fatal (_("Broken assembler. No assembly attempted."));
+ }
+
+ hash_reg_name (RCLASS_CSR, name, address);
+}
+
+static bfd_boolean
+riscv_csr_class_check (enum riscv_csr_class csr_class)
+{
+ switch (csr_class)
+ {
+ case CSR_CLASS_I: return riscv_subset_supports ("i");
+ case CSR_CLASS_F: return riscv_subset_supports ("f");
+ case CSR_CLASS_I_32:
+ return (xlen == 32 && riscv_subset_supports ("i"));
+
+ default:
+ return FALSE;
+ }
+}
+
+static bfd_boolean
+reg_csr_lookup_internal (const char *s)
+{
+ riscv_csr_extra *r =
+ (riscv_csr_extra *) hash_find (csr_extra_hash, s);
+
+ if (r == NULL
+ || !riscv_csr_class_check (r->csr_class))
+ return FALSE;
+
+ return TRUE;
+}
+
static unsigned int
reg_lookup_internal (const char *s, enum reg_class class)
{
@@ -491,6 +563,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
return -1;
+ if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
+ return -1;
+
return DECODE_REG_NUM (r);
}
@@ -769,18 +844,19 @@ md_begin (void)
hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
-
/* Add "fp" as an alias for "s0". */
hash_reg_name (RCLASS_GPR, "fp", 8);
- opcode_names_hash = hash_new ();
- init_opcode_names_hash ();
-
-#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
-#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
+ /* Create and insert CSR hash tables. */
+ csr_extra_hash = hash_new ();
+#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
+#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
+ opcode_names_hash = hash_new ();
+ init_opcode_names_hash ();
+
/* Set the default alignment for the text section. */
record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
}
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
new file mode 100644
index 0000000..4c27f47
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: priv-reg-all.s
+#error_output: priv-reg-fail-fext.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
new file mode 100644
index 0000000..874358f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
@@ -0,0 +1,4 @@
+.*Assembler messages:
+.*Error: unknown CSR `fflags'
+.*Error: unknown CSR `frm'
+.*Error: unknown CSR `fcsr'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
new file mode 100644
index 0000000..88038bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
@@ -0,0 +1,3 @@
+#as: -march=rv64if
+#source: priv-reg-all.s
+#error_output: priv-reg-fail-rv32-only.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
new file mode 100644
index 0000000..83b2878
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
@@ -0,0 +1,68 @@
+.*Assembler messages:
+.*Error: unknown CSR `cycleh'
+.*Error: unknown CSR `timeh'
+.*Error: unknown CSR `instreth'
+.*Error: unknown CSR `hpmcounter3h'
+.*Error: unknown CSR `hpmcounter4h'
+.*Error: unknown CSR `hpmcounter5h'
+.*Error: unknown CSR `hpmcounter6h'
+.*Error: unknown CSR `hpmcounter7h'
+.*Error: unknown CSR `hpmcounter8h'
+.*Error: unknown CSR `hpmcounter9h'
+.*Error: unknown CSR `hpmcounter10h'
+.*Error: unknown CSR `hpmcounter11h'
+.*Error: unknown CSR `hpmcounter12h'
+.*Error: unknown CSR `hpmcounter13h'
+.*Error: unknown CSR `hpmcounter14h'
+.*Error: unknown CSR `hpmcounter15h'
+.*Error: unknown CSR `hpmcounter16h'
+.*Error: unknown CSR `hpmcounter17h'
+.*Error: unknown CSR `hpmcounter18h'
+.*Error: unknown CSR `hpmcounter19h'
+.*Error: unknown CSR `hpmcounter20h'
+.*Error: unknown CSR `hpmcounter21h'
+.*Error: unknown CSR `hpmcounter22h'
+.*Error: unknown CSR `hpmcounter23h'
+.*Error: unknown CSR `hpmcounter24h'
+.*Error: unknown CSR `hpmcounter25h'
+.*Error: unknown CSR `hpmcounter26h'
+.*Error: unknown CSR `hpmcounter27h'
+.*Error: unknown CSR `hpmcounter28h'
+.*Error: unknown CSR `hpmcounter29h'
+.*Error: unknown CSR `hpmcounter30h'
+.*Error: unknown CSR `hpmcounter31h'
+.*Error: unknown CSR `htimedeltah'
+.*Error: unknown CSR `mstatush'
+.*Error: unknown CSR `pmpcfg1'
+.*Error: unknown CSR `pmpcfg3'
+.*Error: unknown CSR `mcycleh'
+.*Error: unknown CSR `minstreth'
+.*Error: unknown CSR `mhpmcounter3h'
+.*Error: unknown CSR `mhpmcounter4h'
+.*Error: unknown CSR `mhpmcounter5h'
+.*Error: unknown CSR `mhpmcounter6h'
+.*Error: unknown CSR `mhpmcounter7h'
+.*Error: unknown CSR `mhpmcounter8h'
+.*Error: unknown CSR `mhpmcounter9h'
+.*Error: unknown CSR `mhpmcounter10h'
+.*Error: unknown CSR `mhpmcounter11h'
+.*Error: unknown CSR `mhpmcounter12h'
+.*Error: unknown CSR `mhpmcounter13h'
+.*Error: unknown CSR `mhpmcounter14h'
+.*Error: unknown CSR `mhpmcounter15h'
+.*Error: unknown CSR `mhpmcounter16h'
+.*Error: unknown CSR `mhpmcounter17h'
+.*Error: unknown CSR `mhpmcounter18h'
+.*Error: unknown CSR `mhpmcounter19h'
+.*Error: unknown CSR `mhpmcounter20h'
+.*Error: unknown CSR `mhpmcounter21h'
+.*Error: unknown CSR `mhpmcounter22h'
+.*Error: unknown CSR `mhpmcounter23h'
+.*Error: unknown CSR `mhpmcounter24h'
+.*Error: unknown CSR `mhpmcounter25h'
+.*Error: unknown CSR `mhpmcounter26h'
+.*Error: unknown CSR `mhpmcounter27h'
+.*Error: unknown CSR `mhpmcounter28h'
+.*Error: unknown CSR `mhpmcounter29h'
+.*Error: unknown CSR `mhpmcounter30h'
+.*Error: unknown CSR `mhpmcounter31h'
diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
index b32b413..1e87e07 100644
--- a/gdb/features/riscv/64bit-csr.xml
+++ b/gdb/features/riscv/64bit-csr.xml
@@ -50,38 +50,6 @@
<reg name="hpmcounter29" bitsize="64"/>
<reg name="hpmcounter30" bitsize="64"/>
<reg name="hpmcounter31" bitsize="64"/>
- <reg name="cycleh" bitsize="64"/>
- <reg name="timeh" bitsize="64"/>
- <reg name="instreth" bitsize="64"/>
- <reg name="hpmcounter3h" bitsize="64"/>
- <reg name="hpmcounter4h" bitsize="64"/>
- <reg name="hpmcounter5h" bitsize="64"/>
- <reg name="hpmcounter6h" bitsize="64"/>
- <reg name="hpmcounter7h" bitsize="64"/>
- <reg name="hpmcounter8h" bitsize="64"/>
- <reg name="hpmcounter9h" bitsize="64"/>
- <reg name="hpmcounter10h" bitsize="64"/>
- <reg name="hpmcounter11h" bitsize="64"/>
- <reg name="hpmcounter12h" bitsize="64"/>
- <reg name="hpmcounter13h" bitsize="64"/>
- <reg name="hpmcounter14h" bitsize="64"/>
- <reg name="hpmcounter15h" bitsize="64"/>
- <reg name="hpmcounter16h" bitsize="64"/>
- <reg name="hpmcounter17h" bitsize="64"/>
- <reg name="hpmcounter18h" bitsize="64"/>
- <reg name="hpmcounter19h" bitsize="64"/>
- <reg name="hpmcounter20h" bitsize="64"/>
- <reg name="hpmcounter21h" bitsize="64"/>
- <reg name="hpmcounter22h" bitsize="64"/>
- <reg name="hpmcounter23h" bitsize="64"/>
- <reg name="hpmcounter24h" bitsize="64"/>
- <reg name="hpmcounter25h" bitsize="64"/>
- <reg name="hpmcounter26h" bitsize="64"/>
- <reg name="hpmcounter27h" bitsize="64"/>
- <reg name="hpmcounter28h" bitsize="64"/>
- <reg name="hpmcounter29h" bitsize="64"/>
- <reg name="hpmcounter30h" bitsize="64"/>
- <reg name="hpmcounter31h" bitsize="64"/>
<reg name="sstatus" bitsize="64"/>
<reg name="sedeleg" bitsize="64"/>
<reg name="sideleg" bitsize="64"/>
@@ -111,9 +79,7 @@
<reg name="mtval" bitsize="64"/>
<reg name="mip" bitsize="64"/>
<reg name="pmpcfg0" bitsize="64"/>
- <reg name="pmpcfg1" bitsize="64"/>
<reg name="pmpcfg2" bitsize="64"/>
- <reg name="pmpcfg3" bitsize="64"/>
<reg name="pmpaddr0" bitsize="64"/>
<reg name="pmpaddr1" bitsize="64"/>
<reg name="pmpaddr2" bitsize="64"/>
@@ -161,37 +127,6 @@
<reg name="mhpmcounter29" bitsize="64"/>
<reg name="mhpmcounter30" bitsize="64"/>
<reg name="mhpmcounter31" bitsize="64"/>
- <reg name="mcycleh" bitsize="64"/>
- <reg name="minstreth" bitsize="64"/>
- <reg name="mhpmcounter3h" bitsize="64"/>
- <reg name="mhpmcounter4h" bitsize="64"/>
- <reg name="mhpmcounter5h" bitsize="64"/>
- <reg name="mhpmcounter6h" bitsize="64"/>
- <reg name="mhpmcounter7h" bitsize="64"/>
- <reg name="mhpmcounter8h" bitsize="64"/>
- <reg name="mhpmcounter9h" bitsize="64"/>
- <reg name="mhpmcounter10h" bitsize="64"/>
- <reg name="mhpmcounter11h" bitsize="64"/>
- <reg name="mhpmcounter12h" bitsize="64"/>
- <reg name="mhpmcounter13h" bitsize="64"/>
- <reg name="mhpmcounter14h" bitsize="64"/>
- <reg name="mhpmcounter15h" bitsize="64"/>
- <reg name="mhpmcounter16h" bitsize="64"/>
- <reg name="mhpmcounter17h" bitsize="64"/>
- <reg name="mhpmcounter18h" bitsize="64"/>
- <reg name="mhpmcounter19h" bitsize="64"/>
- <reg name="mhpmcounter20h" bitsize="64"/>
- <reg name="mhpmcounter21h" bitsize="64"/>
- <reg name="mhpmcounter22h" bitsize="64"/>
- <reg name="mhpmcounter23h" bitsize="64"/>
- <reg name="mhpmcounter24h" bitsize="64"/>
- <reg name="mhpmcounter25h" bitsize="64"/>
- <reg name="mhpmcounter26h" bitsize="64"/>
- <reg name="mhpmcounter27h" bitsize="64"/>
- <reg name="mhpmcounter28h" bitsize="64"/>
- <reg name="mhpmcounter29h" bitsize="64"/>
- <reg name="mhpmcounter30h" bitsize="64"/>
- <reg name="mhpmcounter31h" bitsize="64"/>
<reg name="mhpmevent3" bitsize="64"/>
<reg name="mhpmevent4" bitsize="64"/>
<reg name="mhpmevent5" bitsize="64"/>
@@ -233,7 +168,6 @@
<reg name="hcounteren" bitsize="64"/>
<reg name="hgatp" bitsize="64"/>
<reg name="htimedelta" bitsize="64"/>
- <reg name="htimedeltah" bitsize="64"/>
<reg name="vsstatus" bitsize="64"/>
<reg name="vsie" bitsize="64"/>
<reg name="vstvec" bitsize="64"/>
@@ -243,7 +177,6 @@
<reg name="vstval" bitsize="64"/>
<reg name="vsip" bitsize="64"/>
<reg name="vsatp" bitsize="64"/>
- <reg name="mstatush" bitsize="64"/>
<reg name="mcountinhibit" bitsize="64"/>
<reg name="dscratch0" bitsize="64"/>
<reg name="dscratch1" bitsize="64"/>
diff --git a/gdb/features/riscv/rebuild-csr-xml.sh b/gdb/features/riscv/rebuild-csr-xml.sh
index a3d957c..79fb3cb 100755
--- a/gdb/features/riscv/rebuild-csr-xml.sh
+++ b/gdb/features/riscv/rebuild-csr-xml.sh
@@ -19,10 +19,18 @@ function gen_csr_xml ()
<feature name="org.gnu.gdb.riscv.csr">
EOF
+if [ "$bitsize" = "64" ]; then
grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
- | sed -e "s!DECLARE_CSR(\(.*\), .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
+ | sed /CSR_CLASS_.*_32/d \
+ | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
echo "</feature>"
+else
+ grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
+ | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
+
+ echo "</feature>"
+fi
}
gen_csr_xml 32 > ${RISCV_FEATURE_DIR}/32bit-csr.xml
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index a8b057f..63915d2 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature =
{
"org.gnu.gdb.riscv.csr",
{
-#define DECLARE_CSR(NAME,VALUE) \
+#define DECLARE_CSR(NAME,VALUE,CLASS) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
@@ -534,7 +534,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
{
-#define DECLARE_CSR(NAME,VALUE) \
+#define DECLARE_CSR(NAME,VALUE,CLASS) \
case RISCV_ ## VALUE ## _REGNUM: return # NAME;
switch (regnum)
@@ -870,7 +870,7 @@ riscv_is_regnum_a_named_csr (int regnum)
switch (regnum)
{
-#define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
+#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
return true;
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 4268839..290ef9f 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -44,7 +44,7 @@ enum
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
-#define DECLARE_CSR(name, num) \
+#define DECLARE_CSR(name, num, class) \
RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ee3d976..3809958 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -1128,284 +1128,284 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
#endif
#ifdef DECLARE_CSR
-DECLARE_CSR(ustatus, CSR_USTATUS)
-DECLARE_CSR(uie, CSR_UIE)
-DECLARE_CSR(utvec, CSR_UTVEC)
-DECLARE_CSR(uscratch, CSR_USCRATCH)
-DECLARE_CSR(uepc, CSR_UEPC)
-DECLARE_CSR(ucause, CSR_UCAUSE)
-DECLARE_CSR(utval, CSR_UTVAL)
-DECLARE_CSR(uip, CSR_UIP)
-DECLARE_CSR(fflags, CSR_FFLAGS)
-DECLARE_CSR(frm, CSR_FRM)
-DECLARE_CSR(fcsr, CSR_FCSR)
-DECLARE_CSR(cycle, CSR_CYCLE)
-DECLARE_CSR(time, CSR_TIME)
-DECLARE_CSR(instret, CSR_INSTRET)
-DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
-DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
-DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
-DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
-DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
-DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
-DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
-DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
-DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
-DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
-DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
-DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
-DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
-DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
-DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
-DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
-DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
-DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
-DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
-DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
-DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
-DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
-DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
-DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
-DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
-DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
-DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
-DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
-DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
-DECLARE_CSR(cycleh, CSR_CYCLEH)
-DECLARE_CSR(timeh, CSR_TIMEH)
-DECLARE_CSR(instreth, CSR_INSTRETH)
-DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
-DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
-DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
-DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
-DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
-DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
-DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
-DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
-DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
-DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
-DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
-DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
-DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
-DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
-DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
-DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
-DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
-DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
-DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
-DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
-DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
-DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
-DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
-DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
-DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
-DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
-DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
-DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
-DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
-DECLARE_CSR(sstatus, CSR_SSTATUS)
-DECLARE_CSR(sedeleg, CSR_SEDELEG)
-DECLARE_CSR(sideleg, CSR_SIDELEG)
-DECLARE_CSR(sie, CSR_SIE)
-DECLARE_CSR(stvec, CSR_STVEC)
-DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
-DECLARE_CSR(sscratch, CSR_SSCRATCH)
-DECLARE_CSR(sepc, CSR_SEPC)
-DECLARE_CSR(scause, CSR_SCAUSE)
-DECLARE_CSR(stval, CSR_STVAL)
-DECLARE_CSR(sip, CSR_SIP)
-DECLARE_CSR(satp, CSR_SATP)
-DECLARE_CSR(mvendorid, CSR_MVENDORID)
-DECLARE_CSR(marchid, CSR_MARCHID)
-DECLARE_CSR(mimpid, CSR_MIMPID)
-DECLARE_CSR(mhartid, CSR_MHARTID)
-DECLARE_CSR(mstatus, CSR_MSTATUS)
-DECLARE_CSR(misa, CSR_MISA)
-DECLARE_CSR(medeleg, CSR_MEDELEG)
-DECLARE_CSR(mideleg, CSR_MIDELEG)
-DECLARE_CSR(mie, CSR_MIE)
-DECLARE_CSR(mtvec, CSR_MTVEC)
-DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
-DECLARE_CSR(mscratch, CSR_MSCRATCH)
-DECLARE_CSR(mepc, CSR_MEPC)
-DECLARE_CSR(mcause, CSR_MCAUSE)
-DECLARE_CSR(mtval, CSR_MTVAL)
-DECLARE_CSR(mip, CSR_MIP)
-DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
-DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
-DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
-DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
-DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
-DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
-DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
-DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
-DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
-DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
-DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
-DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
-DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
-DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
-DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
-DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
-DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
-DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
-DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
-DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
-DECLARE_CSR(mcycle, CSR_MCYCLE)
-DECLARE_CSR(minstret, CSR_MINSTRET)
-DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
-DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
-DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
-DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
-DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
-DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
-DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
-DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
-DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
-DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
-DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
-DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
-DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
-DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
-DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
-DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
-DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
-DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
-DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
-DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
-DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
-DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
-DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
-DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
-DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
-DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
-DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
-DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
-DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
-DECLARE_CSR(mcycleh, CSR_MCYCLEH)
-DECLARE_CSR(minstreth, CSR_MINSTRETH)
-DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
-DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
-DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
-DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
-DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
-DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
-DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
-DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
-DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
-DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
-DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
-DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
-DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
-DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
-DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
-DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
-DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
-DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
-DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
-DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
-DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
-DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
-DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
-DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
-DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
-DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
-DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
-DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
-DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
-DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
-DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
-DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
-DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
-DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
-DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
-DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
-DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
-DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
-DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
-DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
-DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
-DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
-DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
-DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
-DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
-DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
-DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
-DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
-DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
-DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
-DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
-DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
-DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
-DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
-DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
-DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
-DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
-DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
-DECLARE_CSR(tselect, CSR_TSELECT)
-DECLARE_CSR(tdata1, CSR_TDATA1)
-DECLARE_CSR(tdata2, CSR_TDATA2)
-DECLARE_CSR(tdata3, CSR_TDATA3)
-DECLARE_CSR(dcsr, CSR_DCSR)
-DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I)
+DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I)
+DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I)
+DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I)
+DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I)
+DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I)
+DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I)
+DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I)
+DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F)
+DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F)
+DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F)
+DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I)
+DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I)
+DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I)
+DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32)
+DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32)
+DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32)
+DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I)
+DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I)
+DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I)
+DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I)
+DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I)
+DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I)
+DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I)
+DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I)
+DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I)
+DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I)
+DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I)
+DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I)
+DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I)
+DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I)
+DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I)
+DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I)
+DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I)
+DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I)
+DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I)
+DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I)
+DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I)
+DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I)
+DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I)
+DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I)
+DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I)
+DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I)
+DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I)
+DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32)
+DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I)
+DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I)
+DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I)
+DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
+DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
+DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
+DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
/* These registers are present in priv spec 1.12. */
-DECLARE_CSR(hstatus, CSR_HSTATUS)
-DECLARE_CSR(hedeleg, CSR_HEDELEG)
-DECLARE_CSR(hideleg, CSR_HIDELEG)
-DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
-DECLARE_CSR(hgatp, CSR_HGATP)
-DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
-DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
-DECLARE_CSR(vsstatus, CSR_VSSTATUS)
-DECLARE_CSR(vsie, CSR_VSIE)
-DECLARE_CSR(vstvec, CSR_VSTVEC)
-DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
-DECLARE_CSR(vsepc, CSR_VSEPC)
-DECLARE_CSR(vscause, CSR_VSCAUSE)
-DECLARE_CSR(vstval, CSR_VSTVAL)
-DECLARE_CSR(vsip, CSR_VSIP)
-DECLARE_CSR(vsatp, CSR_VSATP)
-DECLARE_CSR(mstatush, CSR_MSTATUSH)
-DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
-DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
-DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
+DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
+DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
+DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I)
+DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I_32)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I)
+DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I)
+DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I)
+DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I)
+DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I)
+DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I)
+DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I)
+DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I)
+DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
-DECLARE_CSR(mbase, CSR_MBASE)
-DECLARE_CSR(mbound, CSR_MBOUND)
-DECLARE_CSR(mibase, CSR_MIBASE)
-DECLARE_CSR(mibound, CSR_MIBOUND)
-DECLARE_CSR(mdbase, CSR_MDBASE)
-DECLARE_CSR(mdbound, CSR_MDBOUND)
-DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
-DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
+DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I)
+DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I)
+DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
+DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
+DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
+DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
+DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
+DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
#endif
#ifdef DECLARE_CSR_ALIAS
/* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
-DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
+DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I)
/* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
-DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
+DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
/* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
-DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
+DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
-DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
+DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
/* Hie is 0x204 in 1.9.1, but 0x204 is vsie in 1.12. */
-DECLARE_CSR_ALIAS(hie, CSR_VSIE)
+DECLARE_CSR_ALIAS(hie, CSR_VSIE, CSR_CLASS_I)
/* Htvec is 0x205 in 1.9.1, but 0x205 is vstvec in 1.12. */
-DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC)
+DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC, CSR_CLASS_I)
/* Hscratch is 0x240 in 1.9.1, but 0x240 is vsscratch in 1.12. */
-DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH)
+DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH, CSR_CLASS_I)
/* Hepc is 0x241 in 1.9.1, but 0x241 is vsepc in 1.12. */
-DECLARE_CSR_ALIAS(hepc, CSR_VSEPC)
+DECLARE_CSR_ALIAS(hepc, CSR_VSEPC, CSR_CLASS_I)
/* Hcause is 0x242 in 1.9.1, but 0x242 is vscause in 1.12. */
-DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE)
+DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE, CSR_CLASS_I)
/* Hbadaddr is 0x243 in 1.9.1, but 0x243 is vstval in 1.12. */
-DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL)
+DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL, CSR_CLASS_I)
/* Hip is 0x244 in 1.9.1, but 0x244 is vsip in 1.12. */
-DECLARE_CSR_ALIAS(hip, CSR_VSIP)
+DECLARE_CSR_ALIAS(hip, CSR_VSIP, CSR_CLASS_I)
/* Mucounteren is 0x320 in 1.9.1, but 0x320 is mcountinhibit in 1.12. */
-DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT)
+DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.12. */
-DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0)
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 40893c3..9674d3a 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -326,7 +326,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
unsigned int csr = EXTRACT_OPERAND (CSR, l);
switch (csr)
{
-#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
2019-12-16 5:21 ` [PATCH v3 4/4] RISC-V: Disable the CSR checking by default Nelson Chu
@ 2019-12-16 5:21 ` Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 0:19 ` Jim Wilson
2019-12-16 5:21 ` [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking Nelson Chu
` (2 subsequent siblings)
5 siblings, 2 replies; 25+ messages in thread
From: Nelson Chu @ 2019-12-16 5:21 UTC (permalink / raw)
To: binutils
gas/
* testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s Update
the CSR to privilege spec 1.12.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
* testsuite/gas/riscv/bad-csr.d: Likewise.
* testsuite/gas/riscv/bad-csr.l: Likewise.
* testsuite/gas/riscv/satp.s: Deleted. Duplicate of priv-reg-all.s
* testsuite/gas/riscv/satp.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Updated.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
include/
* opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.
gdb/
* features/riscv/32bit-csr.xml: Regenerated.
* features/riscv/64bit-csr.xml: Regenerated.
---
gas/testsuite/gas/riscv/bad-csr.d | 3 -
gas/testsuite/gas/riscv/bad-csr.l | 2 -
gas/testsuite/gas/riscv/bad-csr.s | 1 -
gas/testsuite/gas/riscv/csr-dw-regnums.d | 52 ++--
gas/testsuite/gas/riscv/csr-dw-regnums.s | 53 ++--
gas/testsuite/gas/riscv/priv-reg-all.d | 270 +++++++++++++++++++
gas/testsuite/gas/riscv/priv-reg-all.s | 295 +++++++++++++++++++++
.../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
.../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
.../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
gas/testsuite/gas/riscv/priv-reg.d | 253 ------------------
gas/testsuite/gas/riscv/priv-reg.s | 269 -------------------
gas/testsuite/gas/riscv/satp.d | 11 -
gas/testsuite/gas/riscv/satp.s | 3 -
gdb/features/riscv/32bit-csr.xml | 26 +-
gdb/features/riscv/64bit-csr.xml | 26 +-
include/opcode/riscv-opc.h | 83 ++++--
17 files changed, 735 insertions(+), 618 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.s
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
delete mode 100644 gas/testsuite/gas/riscv/priv-reg.s
delete mode 100644 gas/testsuite/gas/riscv/satp.d
delete mode 100644 gas/testsuite/gas/riscv/satp.s
diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
deleted file mode 100644
index 6863123..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as:
-#source: bad-csr.s
-#error_output: bad-csr.l
diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
deleted file mode 100644
index a0bb8a6..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
deleted file mode 100644
index 6e6d27e..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.s
+++ /dev/null
@@ -1 +0,0 @@
- csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index 597747c..14d1300 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -104,6 +104,22 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
DW_CFA_offset_extended_sf: r4420 \(sip\) at cfa\+1296
DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
+ DW_CFA_offset_extended_sf: r5632 \(hstatus\) at cfa\+6144
+ DW_CFA_offset_extended_sf: r5634 \(hedeleg\) at cfa\+6152
+ DW_CFA_offset_extended_sf: r5635 \(hideleg\) at cfa\+6156
+ DW_CFA_offset_extended_sf: r5638 \(hcounteren\) at cfa\+6168
+ DW_CFA_offset_extended_sf: r5760 \(hgatp\) at cfa\+6656
+ DW_CFA_offset_extended_sf: r5637 \(htimedelta\) at cfa\+6164
+ DW_CFA_offset_extended_sf: r5653 \(htimedeltah\) at cfa\+6228
+ DW_CFA_offset_extended_sf: r4608 \(vsstatus\) at cfa\+2048
+ DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
+ DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
+ DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
+ DW_CFA_offset_extended_sf: r4673 \(vsepc) at cfa\+2308
+ DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
+ DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
+ DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
+ DW_CFA_offset_extended_sf: r4736 \(vsatp\) at cfa\+2560
DW_CFA_offset_extended_sf: r7953 \(mvendorid\) at cfa\+15428
DW_CFA_offset_extended_sf: r7954 \(marchid\) at cfa\+15432
DW_CFA_offset_extended_sf: r7955 \(mimpid\) at cfa\+15436
@@ -202,6 +218,7 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
+ DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
@@ -237,29 +254,28 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
- DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
- DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
- DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
- DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
- DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064
- DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068
- DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304
- DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308
- DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312
- DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316
- DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320
+ DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
+ DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
+ DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+ DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
+ DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
+ DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
+ DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
+ DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
+ DW_CFA_offset_extended_sf: r4673 \(vsepc\) at cfa\+2308
+ DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
+ DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
+ DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
+ DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+ DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
+ DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
+ DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+320
DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584
DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588
DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592
DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
- DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
- DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
- DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
- DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
- DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
- DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
- DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+ DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
DW_CFA_nop
#...
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index b29e9da..93f293f 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -94,6 +94,22 @@ _start:
.cfi_offset stval, 1292
.cfi_offset sip, 1296
.cfi_offset satp, 1536
+ .cfi_offset hstatus, 6144
+ .cfi_offset hedeleg, 6152
+ .cfi_offset hideleg, 6156
+ .cfi_offset hcounteren, 6168
+ .cfi_offset hgatp, 6656
+ .cfi_offset htimedelta, 6164
+ .cfi_offset htimedeltah, 6228
+ .cfi_offset vsstatus, 2048
+ .cfi_offset vsie, 2064
+ .cfi_offset vstvec, 2068
+ .cfi_offset vsscratch, 2304
+ .cfi_offset vsepc, 2308
+ .cfi_offset vscause, 2312
+ .cfi_offset vstval, 2316
+ .cfi_offset vsip, 2320
+ .cfi_offset vsatp, 2560
.cfi_offset mvendorid, 15428
.cfi_offset marchid, 15432
.cfi_offset mimpid, 15436
@@ -105,6 +121,7 @@ _start:
.cfi_offset mie, 3088
.cfi_offset mtvec, 3092
.cfi_offset mcounteren, 3096
+ .cfi_offset mstatush, 3136
.cfi_offset mscratch, 3328
.cfi_offset mepc, 3332
.cfi_offset mcause, 3336
@@ -192,6 +209,7 @@ _start:
.cfi_offset mhpmcounter29h, 11892
.cfi_offset mhpmcounter30h, 11896
.cfi_offset mhpmcounter31h, 11900
+ .cfi_offset mcountinhibit, 3200
.cfi_offset mhpmevent3, 3212
.cfi_offset mhpmevent4, 3216
.cfi_offset mhpmevent5, 3220
@@ -227,29 +245,28 @@ _start:
.cfi_offset tdata3, 7820
.cfi_offset dcsr, 7872
.cfi_offset dpc, 7876
- .cfi_offset dscratch, 7880
- .cfi_offset hstatus, 2048
- .cfi_offset hedeleg, 2056
- .cfi_offset hideleg, 2060
- .cfi_offset hie, 2064
- .cfi_offset htvec, 2068
- .cfi_offset hscratch, 2304
- .cfi_offset hepc, 2308
- .cfi_offset hcause, 2312
- .cfi_offset hbadaddr, 2316
- .cfi_offset hip, 2320
+ .cfi_offset dscratch0, 7880
+ .cfi_offset dscratch1, 7884
+ .cfi_offset ubadaddr, 268 # utval
+ .cfi_offset sbadaddr, 1292 # stval
+ .cfi_offset sptbr, 1536 # satp
+ .cfi_offset hie, 2064 # vsie
+ .cfi_offset htvec, 2068 # vstvec
+ .cfi_offset hscratch, 2304 # vsscratch
+ .cfi_offset hepc, 2308 # vsepc
+ .cfi_offset hcause, 2312 # vscause
+ .cfi_offset hbadaddr, 2316 # vstval
+ .cfi_offset hip, 2320 # vsip
+ .cfi_offset mbadaddr, 3340 # mtval
+ .cfi_offset mucounteren, 3200 # mcountinhibit
+ .cfi_offset mscounteren, 3204
+ .cfi_offset mhcounteren, 3208
.cfi_offset mbase, 3584
.cfi_offset mbound, 3588
.cfi_offset mibase, 3592
.cfi_offset mibound, 3596
.cfi_offset mdbase, 3600
.cfi_offset mdbound, 3604
- .cfi_offset mucounteren, 3200
- .cfi_offset mscounteren, 3204
- .cfi_offset mhcounteren, 3208
- .cfi_offset ubadaddr, 268
- .cfi_offset sbadaddr, 1292
- .cfi_offset sptbr, 1536
- .cfi_offset mbadaddr, 3340
+ .cfi_offset dscratch, 7880 # dscratch0
nop
.cfi_endproc
diff --git a/gas/testsuite/gas/riscv/priv-reg-all.d b/gas/testsuite/gas/riscv/priv-reg-all.d
new file mode 100644
index 0000000..d86e8c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-all.d
@@ -0,0 +1,270 @@
+#as: -march=rv32if
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
+.*:[ ]+00402573[ ]+csrr[ ]+a0,uie
+.*:[ ]+00502573[ ]+csrr[ ]+a0,utvec
+.*:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
+.*:[ ]+04102573[ ]+csrr[ ]+a0,uepc
+.*:[ ]+04202573[ ]+csrr[ ]+a0,ucause
+.*:[ ]+04302573[ ]+csrr[ ]+a0,utval
+.*:[ ]+04402573[ ]+csrr[ ]+a0,uip
+.*:[ ]+00102573[ ]+frflags[ ]+a0
+.*:[ ]+00202573[ ]+frrm[ ]+a0
+.*:[ ]+00302573[ ]+frcsr[ ]+a0
+.*:[ ]+c0002573[ ]+rdcycle[ ]+a0
+.*:[ ]+c0102573[ ]+rdtime[ ]+a0
+.*:[ ]+c0202573[ ]+rdinstret[ ]+a0
+.*:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
+.*:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
+.*:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
+.*:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
+.*:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
+.*:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
+.*:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
+.*:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
+.*:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
+.*:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
+.*:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
+.*:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
+.*:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
+.*:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
+.*:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
+.*:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
+.*:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
+.*:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
+.*:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
+.*:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
+.*:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
+.*:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
+.*:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
+.*:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
+.*:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
+.*:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
+.*:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
+.*:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
+.*:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
+.*:[ ]+c8002573[ ]+rdcycleh[ ]+a0
+.*:[ ]+c8102573[ ]+rdtimeh[ ]+a0
+.*:[ ]+c8202573[ ]+rdinstreth[ ]+a0
+.*:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
+.*:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
+.*:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
+.*:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
+.*:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
+.*:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
+.*:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
+.*:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
+.*:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
+.*:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
+.*:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
+.*:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
+.*:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
+.*:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
+.*:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
+.*:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
+.*:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
+.*:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
+.*:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
+.*:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
+.*:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
+.*:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
+.*:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
+.*:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
+.*:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
+.*:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
+.*:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
+.*:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
+.*:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
+.*:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
+.*:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
+.*:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
+.*:[ ]+10402573[ ]+csrr[ ]+a0,sie
+.*:[ ]+10502573[ ]+csrr[ ]+a0,stvec
+.*:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
+.*:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
+.*:[ ]+14102573[ ]+csrr[ ]+a0,sepc
+.*:[ ]+14202573[ ]+csrr[ ]+a0,scause
+.*:[ ]+14302573[ ]+csrr[ ]+a0,stval
+.*:[ ]+14402573[ ]+csrr[ ]+a0,sip
+.*:[ ]+18002573[ ]+csrr[ ]+a0,satp
+.*:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
+.*:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
+.*:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
+.*:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
+.*:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
+.*:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
+.*:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah
+.*:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
+.*:[ ]+20402573[ ]+csrr[ ]+a0,vsie
+.*:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
+.*:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
+.*:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
+.*:[ ]+24202573[ ]+csrr[ ]+a0,vscause
+.*:[ ]+24302573[ ]+csrr[ ]+a0,vstval
+.*:[ ]+24402573[ ]+csrr[ ]+a0,vsip
+.*:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
+.*:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
+.*:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
+.*:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
+.*:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
+.*:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
+.*:[ ]+30102573[ ]+csrr[ ]+a0,misa
+.*:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
+.*:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
+.*:[ ]+30402573[ ]+csrr[ ]+a0,mie
+.*:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
+.*:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
+.*:[ ]+31002573[ ]+csrr[ ]+a0,mstatush
+.*:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
+.*:[ ]+34102573[ ]+csrr[ ]+a0,mepc
+.*:[ ]+34202573[ ]+csrr[ ]+a0,mcause
+.*:[ ]+34302573[ ]+csrr[ ]+a0,mtval
+.*:[ ]+34402573[ ]+csrr[ ]+a0,mip
+.*:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
+.*:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
+.*:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
+.*:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
+.*:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
+.*:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
+.*:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
+.*:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
+.*:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
+.*:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
+.*:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
+.*:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
+.*:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
+.*:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
+.*:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
+.*:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
+.*:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
+.*:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
+.*:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
+.*:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
+.*:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
+.*:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
+.*:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
+.*:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
+.*:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
+.*:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
+.*:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
+.*:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
+.*:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
+.*:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
+.*:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
+.*:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
+.*:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
+.*:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
+.*:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
+.*:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
+.*:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
+.*:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
+.*:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
+.*:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
+.*:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
+.*:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
+.*:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
+.*:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
+.*:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
+.*:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
+.*:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
+.*:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
+.*:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
+.*:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
+.*:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
+.*:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
+.*:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
+.*:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
+.*:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
+.*:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
+.*:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
+.*:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
+.*:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
+.*:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
+.*:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
+.*:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
+.*:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
+.*:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
+.*:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
+.*:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
+.*:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
+.*:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
+.*:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
+.*:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
+.*:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
+.*:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
+.*:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
+.*:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
+.*:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
+.*:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
+.*:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
+.*:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
+.*:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
+.*:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
+.*:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
+.*:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
+.*:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
+.*:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
+.*:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
+.*:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
+.*:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
+.*:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
+.*:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
+.*:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
+.*:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
+.*:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
+.*:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
+.*:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
+.*:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
+.*:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
+.*:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
+.*:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
+.*:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
+.*:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
+.*:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
+.*:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
+.*:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
+.*:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
+.*:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
+.*:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
+.*:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
+.*:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
+.*:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
+.*:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
+.*:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
+.*:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
+.*:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
+.*:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
+.*:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
+.*:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
+.*:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
+.*:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
+.*:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
+.*:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
+.*:[ ]+04302573[ ]+csrr[ ]+a0,utval
+.*:[ ]+14302573[ ]+csrr[ ]+a0,stval
+.*:[ ]+18002573[ ]+csrr[ ]+a0,satp
+.*:[ ]+20402573[ ]+csrr[ ]+a0,vsie
+.*:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
+.*:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
+.*:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
+.*:[ ]+24202573[ ]+csrr[ ]+a0,vscause
+.*:[ ]+24302573[ ]+csrr[ ]+a0,vstval
+.*:[ ]+24402573[ ]+csrr[ ]+a0,vsip
+.*:[ ]+34302573[ ]+csrr[ ]+a0,mtval
+.*:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
+.*:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
+.*:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
+.*:[ ]+38002573[ ]+csrr[ ]+a0,mbase
+.*:[ ]+38102573[ ]+csrr[ ]+a0,mbound
+.*:[ ]+38202573[ ]+csrr[ ]+a0,mibase
+.*:[ ]+38302573[ ]+csrr[ ]+a0,mibound
+.*:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
+.*:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
+.*:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
diff --git a/gas/testsuite/gas/riscv/priv-reg-all.s b/gas/testsuite/gas/riscv/priv-reg-all.s
new file mode 100644
index 0000000..4dc6716
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-all.s
@@ -0,0 +1,295 @@
+# From priv spec 1.9.1 to 1.12 registers.
+
+ .macro csr val
+ csrr a0,\val
+ .endm
+
+# User-Level CSR Addresses in 1.12.
+ csr ustatus
+ csr uie
+ csr utvec
+
+ csr uscratch
+ csr uepc
+ csr ucause
+ csr utval
+ csr uip
+
+ csr fflags
+ csr frm
+ csr fcsr
+
+ csr cycle
+ csr time
+ csr instret
+ csr hpmcounter3
+ csr hpmcounter4
+ csr hpmcounter5
+ csr hpmcounter6
+ csr hpmcounter7
+ csr hpmcounter8
+ csr hpmcounter9
+ csr hpmcounter10
+ csr hpmcounter11
+ csr hpmcounter12
+ csr hpmcounter13
+ csr hpmcounter14
+ csr hpmcounter15
+ csr hpmcounter16
+ csr hpmcounter17
+ csr hpmcounter18
+ csr hpmcounter19
+ csr hpmcounter20
+ csr hpmcounter21
+ csr hpmcounter22
+ csr hpmcounter23
+ csr hpmcounter24
+ csr hpmcounter25
+ csr hpmcounter26
+ csr hpmcounter27
+ csr hpmcounter28
+ csr hpmcounter29
+ csr hpmcounter30
+ csr hpmcounter31
+ csr cycleh
+ csr timeh
+ csr instreth
+ csr hpmcounter3h
+ csr hpmcounter4h
+ csr hpmcounter5h
+ csr hpmcounter6h
+ csr hpmcounter7h
+ csr hpmcounter8h
+ csr hpmcounter9h
+ csr hpmcounter10h
+ csr hpmcounter11h
+ csr hpmcounter12h
+ csr hpmcounter13h
+ csr hpmcounter14h
+ csr hpmcounter15h
+ csr hpmcounter16h
+ csr hpmcounter17h
+ csr hpmcounter18h
+ csr hpmcounter19h
+ csr hpmcounter20h
+ csr hpmcounter21h
+ csr hpmcounter22h
+ csr hpmcounter23h
+ csr hpmcounter24h
+ csr hpmcounter25h
+ csr hpmcounter26h
+ csr hpmcounter27h
+ csr hpmcounter28h
+ csr hpmcounter29h
+ csr hpmcounter30h
+ csr hpmcounter31h
+
+# Supervisor-level CSR Addresses in 1.12.
+ csr sstatus
+ csr sedeleg
+ csr sideleg
+ csr sie
+ csr stvec
+ csr scounteren
+
+ csr sscratch
+ csr sepc
+ csr scause
+ csr stval
+ csr sip
+
+ csr satp
+
+# Hypervisor-Level CSR Addresses in 1.12.
+ csr hstatus
+ csr hedeleg
+ csr hideleg
+ csr hcounteren
+
+ csr hgatp
+
+ csr htimedelta
+ csr htimedeltah
+
+ csr vsstatus
+ csr vsie
+ csr vstvec
+ csr vsscratch
+ csr vsepc
+ csr vscause
+ csr vstval
+ csr vsip
+ csr vsatp
+
+# Machine-Level CSR Addresses in 1.12.
+ csr mvendorid
+ csr marchid
+ csr mimpid
+ csr mhartid
+
+ csr mstatus
+ csr misa
+ csr medeleg
+ csr mideleg
+ csr mie
+ csr mtvec
+ csr mcounteren
+ csr mstatush
+
+ csr mscratch
+ csr mepc
+ csr mcause
+ csr mtval
+ csr mip
+
+ csr pmpcfg0
+ csr pmpcfg1
+ csr pmpcfg2
+ csr pmpcfg3
+ csr pmpaddr0
+ csr pmpaddr1
+ csr pmpaddr2
+ csr pmpaddr3
+ csr pmpaddr4
+ csr pmpaddr5
+ csr pmpaddr6
+ csr pmpaddr7
+ csr pmpaddr8
+ csr pmpaddr9
+ csr pmpaddr10
+ csr pmpaddr11
+ csr pmpaddr12
+ csr pmpaddr13
+ csr pmpaddr14
+ csr pmpaddr15
+
+ csr mcycle
+ csr minstret
+ csr mhpmcounter3
+ csr mhpmcounter4
+ csr mhpmcounter5
+ csr mhpmcounter6
+ csr mhpmcounter7
+ csr mhpmcounter8
+ csr mhpmcounter9
+ csr mhpmcounter10
+ csr mhpmcounter11
+ csr mhpmcounter12
+ csr mhpmcounter13
+ csr mhpmcounter14
+ csr mhpmcounter15
+ csr mhpmcounter16
+ csr mhpmcounter17
+ csr mhpmcounter18
+ csr mhpmcounter19
+ csr mhpmcounter20
+ csr mhpmcounter21
+ csr mhpmcounter22
+ csr mhpmcounter23
+ csr mhpmcounter24
+ csr mhpmcounter25
+ csr mhpmcounter26
+ csr mhpmcounter27
+ csr mhpmcounter28
+ csr mhpmcounter29
+ csr mhpmcounter30
+ csr mhpmcounter31
+ csr mcycleh
+ csr minstreth
+ csr mhpmcounter3h
+ csr mhpmcounter4h
+ csr mhpmcounter5h
+ csr mhpmcounter6h
+ csr mhpmcounter7h
+ csr mhpmcounter8h
+ csr mhpmcounter9h
+ csr mhpmcounter10h
+ csr mhpmcounter11h
+ csr mhpmcounter12h
+ csr mhpmcounter13h
+ csr mhpmcounter14h
+ csr mhpmcounter15h
+ csr mhpmcounter16h
+ csr mhpmcounter17h
+ csr mhpmcounter18h
+ csr mhpmcounter19h
+ csr mhpmcounter20h
+ csr mhpmcounter21h
+ csr mhpmcounter22h
+ csr mhpmcounter23h
+ csr mhpmcounter24h
+ csr mhpmcounter25h
+ csr mhpmcounter26h
+ csr mhpmcounter27h
+ csr mhpmcounter28h
+ csr mhpmcounter29h
+ csr mhpmcounter30h
+ csr mhpmcounter31h
+
+ csr mcountinhibit
+ csr mhpmevent3
+ csr mhpmevent4
+ csr mhpmevent5
+ csr mhpmevent6
+ csr mhpmevent7
+ csr mhpmevent8
+ csr mhpmevent9
+ csr mhpmevent10
+ csr mhpmevent11
+ csr mhpmevent12
+ csr mhpmevent13
+ csr mhpmevent14
+ csr mhpmevent15
+ csr mhpmevent16
+ csr mhpmevent17
+ csr mhpmevent18
+ csr mhpmevent19
+ csr mhpmevent20
+ csr mhpmevent21
+ csr mhpmevent22
+ csr mhpmevent23
+ csr mhpmevent24
+ csr mhpmevent25
+ csr mhpmevent26
+ csr mhpmevent27
+ csr mhpmevent28
+ csr mhpmevent29
+ csr mhpmevent30
+ csr mhpmevent31
+
+ csr tselect
+ csr tdata1
+ csr tdata2
+ csr tdata3
+
+ csr dcsr
+ csr dpc
+ csr dscratch0
+ csr dscratch1
+
+# Defined in 1.9.1, but alias for another CSR in 1.12.
+ csr ubadaddr # utval
+ csr sbadaddr # stval
+ csr sptbr # satp
+ csr hie # vsie
+ csr htvec # vstvec
+ csr hscratch # vsscratch
+ csr hepc # vsepc
+ csr hcause # vscause
+ csr hbadaddr # vstval
+ csr hip # vsip
+ csr mbadaddr # mtval
+ csr mucounteren # mcountinhibit
+
+# Defined in 1.9.1, but dropped in 1.10.
+ csr mscounteren
+ csr mhcounteren
+ csr mbase
+ csr mbound
+ csr mibase
+ csr mibound
+ csr mdbase
+ csr mdbound
+
+# Defined in 1.10, but dropped in 1.12.
+ csr dscratch # dscratch0
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
new file mode 100644
index 0000000..9bb3f82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
@@ -0,0 +1,3 @@
+#as:
+#source: priv-reg-fail-nonexistent.s
+#error_output: priv-reg-fail-nonexistent.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
new file mode 100644
index 0000000..a0bb8a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
new file mode 100644
index 0000000..6e6d27e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
@@ -0,0 +1 @@
+ csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
deleted file mode 100644
index d8ec868..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ /dev/null
@@ -1,253 +0,0 @@
-#as: -march=rv32i
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <.text>:
-[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
-[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
-[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
-[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
-[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
-[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
-[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
-[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
-[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
-[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
-[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
-[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
-[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
-[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
-[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
-[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
-[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
-[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
-[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
-[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
-[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
-[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
-[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
-[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
-[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
-[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
-[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
-[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
-[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
-[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
-[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
-[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
-[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
-[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
-[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
-[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
-[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
-[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
-[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
-[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
-[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
-[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
-[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
-[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
-[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
-[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
-[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
-[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
-[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
-[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
-[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
-[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
-[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
-[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
-[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
-[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
-[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
-[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
-[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
-[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
-[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
-[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
-[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
-[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
-[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
-[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
-[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
-[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
-[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
-[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
-[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
-[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
-[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
-[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
-[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
-[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
-[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
-[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
-[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
-[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
-[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
-[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
-[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
-[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
-[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
-[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
-[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
-[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
-[ ]+170:[ ]+24102573[ ]+csrr[ ]+a0,hepc
-[ ]+174:[ ]+24202573[ ]+csrr[ ]+a0,hcause
-[ ]+178:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
-[ ]+17c:[ ]+24402573[ ]+csrr[ ]+a0,hip
-[ ]+180:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
-[ ]+184:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
-[ ]+188:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
-[ ]+18c:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
-[ ]+190:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
-[ ]+194:[ ]+30102573[ ]+csrr[ ]+a0,misa
-[ ]+198:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
-[ ]+19c:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
-[ ]+1a0:[ ]+30402573[ ]+csrr[ ]+a0,mie
-[ ]+1a4:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
-[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
-[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
-[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
-[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
-[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
-[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
-[ ]+1c4:[ ]+38202573[ ]+csrr[ ]+a0,mibase
-[ ]+1c8:[ ]+38302573[ ]+csrr[ ]+a0,mibound
-[ ]+1cc:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
-[ ]+1d0:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
-[ ]+1d4:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
-[ ]+1d8:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
-[ ]+1dc:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
-[ ]+1e0:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
-[ ]+1e4:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
-[ ]+1e8:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
-[ ]+1ec:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
-[ ]+1f0:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
-[ ]+1f4:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
-[ ]+1f8:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
-[ ]+1fc:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
-[ ]+200:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
-[ ]+204:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
-[ ]+208:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
-[ ]+20c:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
-[ ]+210:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
-[ ]+214:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
-[ ]+218:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
-[ ]+21c:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
-[ ]+220:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
-[ ]+224:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
-[ ]+228:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
-[ ]+22c:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
-[ ]+230:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
-[ ]+234:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
-[ ]+238:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
-[ ]+23c:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
-[ ]+240:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
-[ ]+244:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
-[ ]+248:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
-[ ]+24c:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
-[ ]+250:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
-[ ]+254:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
-[ ]+258:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
-[ ]+25c:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
-[ ]+260:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
-[ ]+264:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
-[ ]+268:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
-[ ]+26c:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
-[ ]+270:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
-[ ]+274:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
-[ ]+278:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
-[ ]+27c:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
-[ ]+280:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
-[ ]+284:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
-[ ]+288:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
-[ ]+28c:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
-[ ]+290:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
-[ ]+294:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
-[ ]+298:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
-[ ]+29c:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
-[ ]+2a0:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
-[ ]+2a4:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
-[ ]+2a8:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
-[ ]+2ac:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
-[ ]+2b0:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
-[ ]+2b4:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
-[ ]+2b8:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
-[ ]+2bc:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
-[ ]+2c0:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
-[ ]+2c4:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
-[ ]+2c8:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
-[ ]+2cc:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
-[ ]+2d0:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
-[ ]+2d4:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
-[ ]+2d8:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
-[ ]+2dc:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
-[ ]+2e0:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
-[ ]+2e4:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
-[ ]+2e8:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
-[ ]+2ec:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
-[ ]+2f0:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
-[ ]+2f4:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
-[ ]+2f8:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
-[ ]+2fc:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
-[ ]+300:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
-[ ]+304:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
-[ ]+308:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
-[ ]+30c:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
-[ ]+310:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
-[ ]+314:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
-[ ]+318:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
-[ ]+31c:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
-[ ]+320:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
-[ ]+324:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
-[ ]+328:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
-[ ]+32c:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
-[ ]+330:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
-[ ]+334:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
-[ ]+338:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
-[ ]+33c:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
-[ ]+340:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
-[ ]+344:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
-[ ]+348:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+34c:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+350:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+354:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+358:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+35c:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+360:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
-[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
-[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
-[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
-[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
-[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
-[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
-[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
-[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
-[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
-[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
-[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
-[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
-[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
-[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
-[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
-[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
-[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
-[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
-[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
-[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
-[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
-[ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
deleted file mode 100644
index 72d97f9..0000000
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ /dev/null
@@ -1,269 +0,0 @@
- .macro csr val
- csrr a0,\val
- .endm
-# 1.9.1 registers
- csr ustatus
- csr uie
- csr utvec
-
- csr uscratch
- csr uepc
- csr ucause
- csr ubadaddr
- csr uip
-
- csr fflags
- csr frm
- csr fcsr
-
- csr cycle
- csr time
- csr instret
- csr hpmcounter3
- csr hpmcounter4
- csr hpmcounter5
- csr hpmcounter6
- csr hpmcounter7
- csr hpmcounter8
- csr hpmcounter9
- csr hpmcounter10
- csr hpmcounter11
- csr hpmcounter12
- csr hpmcounter13
- csr hpmcounter14
- csr hpmcounter15
- csr hpmcounter16
- csr hpmcounter17
- csr hpmcounter18
- csr hpmcounter19
- csr hpmcounter20
- csr hpmcounter21
- csr hpmcounter22
- csr hpmcounter23
- csr hpmcounter24
- csr hpmcounter25
- csr hpmcounter26
- csr hpmcounter27
- csr hpmcounter28
- csr hpmcounter29
- csr hpmcounter30
- csr hpmcounter31
- csr cycleh
- csr timeh
- csr instreth
- csr hpmcounter3h
- csr hpmcounter4h
- csr hpmcounter5h
- csr hpmcounter6h
- csr hpmcounter7h
- csr hpmcounter8h
- csr hpmcounter9h
- csr hpmcounter10h
- csr hpmcounter11h
- csr hpmcounter12h
- csr hpmcounter13h
- csr hpmcounter14h
- csr hpmcounter15h
- csr hpmcounter16h
- csr hpmcounter17h
- csr hpmcounter18h
- csr hpmcounter19h
- csr hpmcounter20h
- csr hpmcounter21h
- csr hpmcounter22h
- csr hpmcounter23h
- csr hpmcounter24h
- csr hpmcounter25h
- csr hpmcounter26h
- csr hpmcounter27h
- csr hpmcounter28h
- csr hpmcounter29h
- csr hpmcounter30h
- csr hpmcounter31h
-
- csr sstatus
- csr sedeleg
- csr sideleg
- csr sie
- csr stvec
-
- csr sscratch
- csr sepc
- csr scause
- csr sbadaddr
- csr sip
-
- csr sptbr
-
- csr hstatus
- csr hedeleg
- csr hideleg
- csr hie
- csr htvec
-
- csr hscratch
- csr hepc
- csr hcause
- csr hbadaddr
- csr hip
-
- csr mvendorid
- csr marchid
- csr mimpid
- csr mhartid
-
- csr mstatus
- csr misa
- csr medeleg
- csr mideleg
- csr mie
- csr mtvec
-
- csr mscratch
- csr mepc
- csr mcause
- csr mbadaddr
- csr mip
-
- csr mbase
- csr mbound
- csr mibase
- csr mibound
- csr mdbase
- csr mdbound
-
- csr mcycle
- csr minstret
- csr mhpmcounter3
- csr mhpmcounter4
- csr mhpmcounter5
- csr mhpmcounter6
- csr mhpmcounter7
- csr mhpmcounter8
- csr mhpmcounter9
- csr mhpmcounter10
- csr mhpmcounter11
- csr mhpmcounter12
- csr mhpmcounter13
- csr mhpmcounter14
- csr mhpmcounter15
- csr mhpmcounter16
- csr mhpmcounter17
- csr mhpmcounter18
- csr mhpmcounter19
- csr mhpmcounter20
- csr mhpmcounter21
- csr mhpmcounter22
- csr mhpmcounter23
- csr mhpmcounter24
- csr mhpmcounter25
- csr mhpmcounter26
- csr mhpmcounter27
- csr mhpmcounter28
- csr mhpmcounter29
- csr mhpmcounter30
- csr mhpmcounter31
- csr mcycleh
- csr minstreth
- csr mhpmcounter3h
- csr mhpmcounter4h
- csr mhpmcounter5h
- csr mhpmcounter6h
- csr mhpmcounter7h
- csr mhpmcounter8h
- csr mhpmcounter9h
- csr mhpmcounter10h
- csr mhpmcounter11h
- csr mhpmcounter12h
- csr mhpmcounter13h
- csr mhpmcounter14h
- csr mhpmcounter15h
- csr mhpmcounter16h
- csr mhpmcounter17h
- csr mhpmcounter18h
- csr mhpmcounter19h
- csr mhpmcounter20h
- csr mhpmcounter21h
- csr mhpmcounter22h
- csr mhpmcounter23h
- csr mhpmcounter24h
- csr mhpmcounter25h
- csr mhpmcounter26h
- csr mhpmcounter27h
- csr mhpmcounter28h
- csr mhpmcounter29h
- csr mhpmcounter30h
- csr mhpmcounter31h
-
- csr mucounteren
- csr mscounteren
- csr mhcounteren
-
- csr mhpmevent3
- csr mhpmevent4
- csr mhpmevent5
- csr mhpmevent6
- csr mhpmevent7
- csr mhpmevent8
- csr mhpmevent9
- csr mhpmevent10
- csr mhpmevent11
- csr mhpmevent12
- csr mhpmevent13
- csr mhpmevent14
- csr mhpmevent15
- csr mhpmevent16
- csr mhpmevent17
- csr mhpmevent18
- csr mhpmevent19
- csr mhpmevent20
- csr mhpmevent21
- csr mhpmevent22
- csr mhpmevent23
- csr mhpmevent24
- csr mhpmevent25
- csr mhpmevent26
- csr mhpmevent27
- csr mhpmevent28
- csr mhpmevent29
- csr mhpmevent30
- csr mhpmevent31
-
- csr tselect
- csr tdata1
- csr tdata2
- csr tdata3
-
- csr dcsr
- csr dpc
- csr dscratch
-# 1.10 registers
- csr utval
-
- csr scounteren
- csr stval
- csr satp
-
- csr mcounteren
- csr mtval
-
- csr pmpcfg0
- csr pmpcfg1
- csr pmpcfg2
- csr pmpcfg3
- csr pmpaddr0
- csr pmpaddr1
- csr pmpaddr2
- csr pmpaddr3
- csr pmpaddr4
- csr pmpaddr5
- csr pmpaddr6
- csr pmpaddr7
- csr pmpaddr8
- csr pmpaddr9
- csr pmpaddr10
- csr pmpaddr11
- csr pmpaddr12
- csr pmpaddr13
- csr pmpaddr14
- csr pmpaddr15
diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
deleted file mode 100644
index 823601c..0000000
--- a/gas/testsuite/gas/riscv/satp.d
+++ /dev/null
@@ -1,11 +0,0 @@
-#as:
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
-[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
deleted file mode 100644
index f8aa766..0000000
--- a/gas/testsuite/gas/riscv/satp.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- csrr t0, satp
- csrr t0, sptbr
diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
index da1bf19..a9ea54d 100644
--- a/gdb/features/riscv/32bit-csr.xml
+++ b/gdb/features/riscv/32bit-csr.xml
@@ -227,24 +227,32 @@
<reg name="tdata3" bitsize="32"/>
<reg name="dcsr" bitsize="32"/>
<reg name="dpc" bitsize="32"/>
- <reg name="dscratch" bitsize="32"/>
<reg name="hstatus" bitsize="32"/>
<reg name="hedeleg" bitsize="32"/>
<reg name="hideleg" bitsize="32"/>
- <reg name="hie" bitsize="32"/>
- <reg name="htvec" bitsize="32"/>
- <reg name="hscratch" bitsize="32"/>
- <reg name="hepc" bitsize="32"/>
- <reg name="hcause" bitsize="32"/>
- <reg name="hbadaddr" bitsize="32"/>
- <reg name="hip" bitsize="32"/>
+ <reg name="hcounteren" bitsize="32"/>
+ <reg name="hgatp" bitsize="32"/>
+ <reg name="htimedelta" bitsize="32"/>
+ <reg name="htimedeltah" bitsize="32"/>
+ <reg name="vsstatus" bitsize="32"/>
+ <reg name="vsie" bitsize="32"/>
+ <reg name="vstvec" bitsize="32"/>
+ <reg name="vsscratch" bitsize="32"/>
+ <reg name="vsepc" bitsize="32"/>
+ <reg name="vscause" bitsize="32"/>
+ <reg name="vstval" bitsize="32"/>
+ <reg name="vsip" bitsize="32"/>
+ <reg name="vsatp" bitsize="32"/>
+ <reg name="mstatush" bitsize="32"/>
+ <reg name="mcountinhibit" bitsize="32"/>
+ <reg name="dscratch0" bitsize="32"/>
+ <reg name="dscratch1" bitsize="32"/>
<reg name="mbase" bitsize="32"/>
<reg name="mbound" bitsize="32"/>
<reg name="mibase" bitsize="32"/>
<reg name="mibound" bitsize="32"/>
<reg name="mdbase" bitsize="32"/>
<reg name="mdbound" bitsize="32"/>
- <reg name="mucounteren" bitsize="32"/>
<reg name="mscounteren" bitsize="32"/>
<reg name="mhcounteren" bitsize="32"/>
</feature>
diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
index 6aa4bed..b32b413 100644
--- a/gdb/features/riscv/64bit-csr.xml
+++ b/gdb/features/riscv/64bit-csr.xml
@@ -227,24 +227,32 @@
<reg name="tdata3" bitsize="64"/>
<reg name="dcsr" bitsize="64"/>
<reg name="dpc" bitsize="64"/>
- <reg name="dscratch" bitsize="64"/>
<reg name="hstatus" bitsize="64"/>
<reg name="hedeleg" bitsize="64"/>
<reg name="hideleg" bitsize="64"/>
- <reg name="hie" bitsize="64"/>
- <reg name="htvec" bitsize="64"/>
- <reg name="hscratch" bitsize="64"/>
- <reg name="hepc" bitsize="64"/>
- <reg name="hcause" bitsize="64"/>
- <reg name="hbadaddr" bitsize="64"/>
- <reg name="hip" bitsize="64"/>
+ <reg name="hcounteren" bitsize="64"/>
+ <reg name="hgatp" bitsize="64"/>
+ <reg name="htimedelta" bitsize="64"/>
+ <reg name="htimedeltah" bitsize="64"/>
+ <reg name="vsstatus" bitsize="64"/>
+ <reg name="vsie" bitsize="64"/>
+ <reg name="vstvec" bitsize="64"/>
+ <reg name="vsscratch" bitsize="64"/>
+ <reg name="vsepc" bitsize="64"/>
+ <reg name="vscause" bitsize="64"/>
+ <reg name="vstval" bitsize="64"/>
+ <reg name="vsip" bitsize="64"/>
+ <reg name="vsatp" bitsize="64"/>
+ <reg name="mstatush" bitsize="64"/>
+ <reg name="mcountinhibit" bitsize="64"/>
+ <reg name="dscratch0" bitsize="64"/>
+ <reg name="dscratch1" bitsize="64"/>
<reg name="mbase" bitsize="64"/>
<reg name="mbound" bitsize="64"/>
<reg name="mibase" bitsize="64"/>
<reg name="mibound" bitsize="64"/>
<reg name="mdbase" bitsize="64"/>
<reg name="mdbound" bitsize="64"/>
- <reg name="mucounteren" bitsize="64"/>
<reg name="mscounteren" bitsize="64"/>
<reg name="mhcounteren" bitsize="64"/>
</feature>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index f09200c..ee3d976 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -795,18 +795,31 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
+/* These registers are present in priv spec 1.12. */
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGATP 0x680
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HTIMEDELTAH 0x615
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
+#define CSR_MSTATUSH 0x310
+#define CSR_MCOUNTINHIBIT 0x320
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
-#define CSR_HSTATUS 0x200
-#define CSR_HEDELEG 0x202
-#define CSR_HIDELEG 0x203
-#define CSR_HIE 0x204
-#define CSR_HTVEC 0x205
-#define CSR_HSCRATCH 0x240
-#define CSR_HEPC 0x241
-#define CSR_HCAUSE 0x242
-#define CSR_HBADADDR 0x243
-#define CSR_HIP 0x244
+/* CSR_HSTATUS is 0x200 in 1.9.1, dropped in 1.10, but 0x600 in 1.12. */
+/* CSR_HEDELEG is 0x202 in 1.9.1, dropped in 1.10, but 0x602 in 1.12. */
+/* CSR_HIDELEG is 0x203 in 1.9.1, dropped in 1.10, but 0x603 in 1.12. */
/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -814,7 +827,6 @@
#define CSR_MIBOUND 0x383
#define CSR_MDBASE 0x384
#define CSR_MDBOUND 0x385
-#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
#define CAUSE_MISALIGNED_FETCH 0x0
@@ -1336,25 +1348,34 @@ DECLARE_CSR(tdata2, CSR_TDATA2)
DECLARE_CSR(tdata3, CSR_TDATA3)
DECLARE_CSR(dcsr, CSR_DCSR)
DECLARE_CSR(dpc, CSR_DPC)
-DECLARE_CSR(dscratch, CSR_DSCRATCH)
-/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
+/* These registers are present in priv spec 1.12. */
DECLARE_CSR(hstatus, CSR_HSTATUS)
DECLARE_CSR(hedeleg, CSR_HEDELEG)
DECLARE_CSR(hideleg, CSR_HIDELEG)
-DECLARE_CSR(hie, CSR_HIE)
-DECLARE_CSR(htvec, CSR_HTVEC)
-DECLARE_CSR(hscratch, CSR_HSCRATCH)
-DECLARE_CSR(hepc, CSR_HEPC)
-DECLARE_CSR(hcause, CSR_HCAUSE)
-DECLARE_CSR(hbadaddr, CSR_HBADADDR)
-DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS)
+DECLARE_CSR(vsie, CSR_VSIE)
+DECLARE_CSR(vstvec, CSR_VSTVEC)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
+DECLARE_CSR(vsepc, CSR_VSEPC)
+DECLARE_CSR(vscause, CSR_VSCAUSE)
+DECLARE_CSR(vstval, CSR_VSTVAL)
+DECLARE_CSR(vsip, CSR_VSIP)
+DECLARE_CSR(vsatp, CSR_VSATP)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
+/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
DECLARE_CSR(mbase, CSR_MBASE)
DECLARE_CSR(mbound, CSR_MBOUND)
DECLARE_CSR(mibase, CSR_MIBASE)
DECLARE_CSR(mibound, CSR_MIBOUND)
DECLARE_CSR(mdbase, CSR_MDBASE)
DECLARE_CSR(mdbound, CSR_MDBOUND)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
#endif
@@ -1367,6 +1388,24 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
+/* Hie is 0x204 in 1.9.1, but 0x204 is vsie in 1.12. */
+DECLARE_CSR_ALIAS(hie, CSR_VSIE)
+/* Htvec is 0x205 in 1.9.1, but 0x205 is vstvec in 1.12. */
+DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC)
+/* Hscratch is 0x240 in 1.9.1, but 0x240 is vsscratch in 1.12. */
+DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH)
+/* Hepc is 0x241 in 1.9.1, but 0x241 is vsepc in 1.12. */
+DECLARE_CSR_ALIAS(hepc, CSR_VSEPC)
+/* Hcause is 0x242 in 1.9.1, but 0x242 is vscause in 1.12. */
+DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE)
+/* Hbadaddr is 0x243 in 1.9.1, but 0x243 is vstval in 1.12. */
+DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL)
+/* Hip is 0x244 in 1.9.1, but 0x244 is vsip in 1.12. */
+DECLARE_CSR_ALIAS(hip, CSR_VSIP)
+/* Mucounteren is 0x320 in 1.9.1, but 0x320 is mcountinhibit in 1.12. */
+DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT)
+/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.12. */
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
--
2.7.4
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
` (3 preceding siblings ...)
2019-12-16 5:21 ` [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking Nelson Chu
@ 2020-01-03 1:29 ` Nelson Chu
2020-01-22 21:35 ` Palmer Dabbelt via binutils
5 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-01-03 1:29 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Jim Wilson, Andrew Waterman, Kito Cheng
Kind reminder :)
Any comments or suggestions?
Thanks
Best Regards
Nelson
On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Dear Palmer,
>
> I'm on the master branch, but failed to notice that my internal build environment
> add the --disable-gdb configure option to disable the GDB build. I'm really sorry
> for this. After attaching the v3 patches, I can build riscv-gdb now. However,
> the csr checking only work for the assembler so far. I extend the DECLARE_CSR
> to record more informaton (`class`), but these information are unused in GDB.
> Therefore, I just fix the GDB build failed by allowing more arguments for
> DECLARE_CSR.
>
> Thanks and best regards
> Nelson
>
>
> Fix the build failed for GDB.
>
> * [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
> Same as the previous one.
>
> * [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
> Upadte the gdb/riscv-tdep.h and gdb/riscv-tdep.c since the DECLARE_CSR is changed.
>
> * [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
> Same as the previous one.
>
> * [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
> Same as the previous one.
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PING] [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
2019-12-16 5:21 ` [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking Nelson Chu
@ 2020-01-03 1:31 ` Nelson Chu
2020-02-01 1:27 ` Jim Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-01-03 1:31 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Jim Wilson, Andrew Waterman, Kito Cheng
PING :)
On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> According to the riscv privilege spec, some CSR are only valid when rv32 or
> the specific extension is set. We extend the DECLARE_CSR and DECLARE_CSR_ALIAS
> to record more informaton we need, and then check whether the CSR is valid
> according to these information.
>
> gas/
> * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
> whether or not this CSR is legal in the current ISA string.
> (riscv_csr_extra): New structure to hold all extra information of CSR.
> (riscv_init_csr_hash): New function. According to the DECLARE_CSR and
> DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
> Call hash_reg_name to insert CSR address into reg_names_hash.
> (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
> (reg_csr_lookup_internal, riscv_csr_class_check): New functions.
> Decide whether the CSR is valid according to the `csr_extra_hash`.
> * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
> file is `priv-reg-all.s`, and the ISA is rv32i without f-ext, so the
> f-ext CSR are not allowed.
> * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
> source file is `priv-reg-all.s`, and the ISA is rv64if, so the
> rv32-only CSR are not allowed.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
>
> include/
> * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
> record riscv_csr_class.
>
> opcodes/
> * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
>
> gdb/
> * riscv-tdep.c: Updated since the DECLARE_CSR is changed.
> * riscv-tdep.h: Likewise.
> * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
> rv32-only CSR.
> * features/riscv/64bit-csr.xml: Regernated.
>
> binutils/
> * dwarf.c: Updated since the DECLARE_CSR is changed.
> ---
> binutils/dwarf.c | 2 +-
> gas/config/tc-riscv.c | 88 +++-
> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 +
> gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 4 +
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 +
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 +++
> gdb/features/riscv/64bit-csr.xml | 67 ---
> gdb/features/riscv/rebuild-csr-xml.sh | 10 +-
> gdb/riscv-tdep.c | 6 +-
> gdb/riscv-tdep.h | 2 +-
> include/opcode/riscv-opc.h | 522 +++++++++++-----------
> opcodes/riscv-dis.c | 2 +-
> 12 files changed, 436 insertions(+), 341 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
>
> diff --git a/binutils/dwarf.c b/binutils/dwarf.c
> index 06ef1f7..d7d1e14 100644
> --- a/binutils/dwarf.c
> +++ b/binutils/dwarf.c
> @@ -7609,7 +7609,7 @@ regname_internal_riscv (unsigned int regno)
> document. */
> switch (regno)
> {
> -#define DECLARE_CSR(NAME,VALUE) case VALUE + 4096: name = #NAME; break;
> +#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break;
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 7ec1028..4c9ff52 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -455,6 +455,7 @@ enum reg_class
> };
>
> static struct hash_control *reg_names_hash = NULL;
> +static struct hash_control *csr_extra_hash = NULL;
>
> #define ENCODE_REG_HASH(cls, n) \
> ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
> @@ -480,6 +481,77 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n)
> hash_reg_name (class, names[i], i);
> }
>
> +/* All RISC-V CSRs belong to one of these classes. */
> +
> +enum riscv_csr_class
> +{
> + CSR_CLASS_NONE,
> +
> + CSR_CLASS_I,
> + CSR_CLASS_I_32, /* rv32 only */
> + CSR_CLASS_F, /* f-ext only */
> +};
> +
> +/* This structure holds all restricted conditions for a CSR. */
> +
> +typedef struct
> +{
> + /* Class to which this CSR belongs. Used to decide whether or
> + not this CSR is legal in the current -march context. */
> + enum riscv_csr_class csr_class;
> +} riscv_csr_extra;
> +
> +/* Init two hashes for CSR. */
> +
> +static void
> +riscv_init_csr_hashes (const char *name,
> + unsigned address,
> + enum riscv_csr_class class)
> +{
> + riscv_csr_extra *entry = XNEW (riscv_csr_extra);
> + entry->csr_class = class;
> +
> + const char *hash_error =
> + hash_insert (csr_extra_hash, name, (void *) entry);
> + if (hash_error)
> + {
> + fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
> + name, hash_error);
> + /* Probably a memory allocation problem? Give up now. */
> + as_fatal (_("Broken assembler. No assembly attempted."));
> + }
> +
> + hash_reg_name (RCLASS_CSR, name, address);
> +}
> +
> +static bfd_boolean
> +riscv_csr_class_check (enum riscv_csr_class csr_class)
> +{
> + switch (csr_class)
> + {
> + case CSR_CLASS_I: return riscv_subset_supports ("i");
> + case CSR_CLASS_F: return riscv_subset_supports ("f");
> + case CSR_CLASS_I_32:
> + return (xlen == 32 && riscv_subset_supports ("i"));
> +
> + default:
> + return FALSE;
> + }
> +}
> +
> +static bfd_boolean
> +reg_csr_lookup_internal (const char *s)
> +{
> + riscv_csr_extra *r =
> + (riscv_csr_extra *) hash_find (csr_extra_hash, s);
> +
> + if (r == NULL
> + || !riscv_csr_class_check (r->csr_class))
> + return FALSE;
> +
> + return TRUE;
> +}
> +
> static unsigned int
> reg_lookup_internal (const char *s, enum reg_class class)
> {
> @@ -491,6 +563,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
> if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
> return -1;
>
> + if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
> + return -1;
> +
> return DECODE_REG_NUM (r);
> }
>
> @@ -769,18 +844,19 @@ md_begin (void)
> hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR);
> hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR);
> hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR);
> -
> /* Add "fp" as an alias for "s0". */
> hash_reg_name (RCLASS_GPR, "fp", 8);
>
> - opcode_names_hash = hash_new ();
> - init_opcode_names_hash ();
> -
> -#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
> -#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
> + /* Create and insert CSR hash tables. */
> + csr_extra_hash = hash_new ();
> +#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class);
> +#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class);
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
>
> + opcode_names_hash = hash_new ();
> + init_opcode_names_hash ();
> +
> /* Set the default alignment for the text section. */
> record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
> }
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> new file mode 100644
> index 0000000..4c27f47
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i
> +#source: priv-reg-all.s
> +#error_output: priv-reg-fail-fext.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> new file mode 100644
> index 0000000..874358f
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l
> @@ -0,0 +1,4 @@
> +.*Assembler messages:
> +.*Error: unknown CSR `fflags'
> +.*Error: unknown CSR `frm'
> +.*Error: unknown CSR `fcsr'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> new file mode 100644
> index 0000000..88038bd
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64if
> +#source: priv-reg-all.s
> +#error_output: priv-reg-fail-rv32-only.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> new file mode 100644
> index 0000000..83b2878
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> @@ -0,0 +1,68 @@
> +.*Assembler messages:
> +.*Error: unknown CSR `cycleh'
> +.*Error: unknown CSR `timeh'
> +.*Error: unknown CSR `instreth'
> +.*Error: unknown CSR `hpmcounter3h'
> +.*Error: unknown CSR `hpmcounter4h'
> +.*Error: unknown CSR `hpmcounter5h'
> +.*Error: unknown CSR `hpmcounter6h'
> +.*Error: unknown CSR `hpmcounter7h'
> +.*Error: unknown CSR `hpmcounter8h'
> +.*Error: unknown CSR `hpmcounter9h'
> +.*Error: unknown CSR `hpmcounter10h'
> +.*Error: unknown CSR `hpmcounter11h'
> +.*Error: unknown CSR `hpmcounter12h'
> +.*Error: unknown CSR `hpmcounter13h'
> +.*Error: unknown CSR `hpmcounter14h'
> +.*Error: unknown CSR `hpmcounter15h'
> +.*Error: unknown CSR `hpmcounter16h'
> +.*Error: unknown CSR `hpmcounter17h'
> +.*Error: unknown CSR `hpmcounter18h'
> +.*Error: unknown CSR `hpmcounter19h'
> +.*Error: unknown CSR `hpmcounter20h'
> +.*Error: unknown CSR `hpmcounter21h'
> +.*Error: unknown CSR `hpmcounter22h'
> +.*Error: unknown CSR `hpmcounter23h'
> +.*Error: unknown CSR `hpmcounter24h'
> +.*Error: unknown CSR `hpmcounter25h'
> +.*Error: unknown CSR `hpmcounter26h'
> +.*Error: unknown CSR `hpmcounter27h'
> +.*Error: unknown CSR `hpmcounter28h'
> +.*Error: unknown CSR `hpmcounter29h'
> +.*Error: unknown CSR `hpmcounter30h'
> +.*Error: unknown CSR `hpmcounter31h'
> +.*Error: unknown CSR `htimedeltah'
> +.*Error: unknown CSR `mstatush'
> +.*Error: unknown CSR `pmpcfg1'
> +.*Error: unknown CSR `pmpcfg3'
> +.*Error: unknown CSR `mcycleh'
> +.*Error: unknown CSR `minstreth'
> +.*Error: unknown CSR `mhpmcounter3h'
> +.*Error: unknown CSR `mhpmcounter4h'
> +.*Error: unknown CSR `mhpmcounter5h'
> +.*Error: unknown CSR `mhpmcounter6h'
> +.*Error: unknown CSR `mhpmcounter7h'
> +.*Error: unknown CSR `mhpmcounter8h'
> +.*Error: unknown CSR `mhpmcounter9h'
> +.*Error: unknown CSR `mhpmcounter10h'
> +.*Error: unknown CSR `mhpmcounter11h'
> +.*Error: unknown CSR `mhpmcounter12h'
> +.*Error: unknown CSR `mhpmcounter13h'
> +.*Error: unknown CSR `mhpmcounter14h'
> +.*Error: unknown CSR `mhpmcounter15h'
> +.*Error: unknown CSR `mhpmcounter16h'
> +.*Error: unknown CSR `mhpmcounter17h'
> +.*Error: unknown CSR `mhpmcounter18h'
> +.*Error: unknown CSR `mhpmcounter19h'
> +.*Error: unknown CSR `mhpmcounter20h'
> +.*Error: unknown CSR `mhpmcounter21h'
> +.*Error: unknown CSR `mhpmcounter22h'
> +.*Error: unknown CSR `mhpmcounter23h'
> +.*Error: unknown CSR `mhpmcounter24h'
> +.*Error: unknown CSR `mhpmcounter25h'
> +.*Error: unknown CSR `mhpmcounter26h'
> +.*Error: unknown CSR `mhpmcounter27h'
> +.*Error: unknown CSR `mhpmcounter28h'
> +.*Error: unknown CSR `mhpmcounter29h'
> +.*Error: unknown CSR `mhpmcounter30h'
> +.*Error: unknown CSR `mhpmcounter31h'
> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> index b32b413..1e87e07 100644
> --- a/gdb/features/riscv/64bit-csr.xml
> +++ b/gdb/features/riscv/64bit-csr.xml
> @@ -50,38 +50,6 @@
> <reg name="hpmcounter29" bitsize="64"/>
> <reg name="hpmcounter30" bitsize="64"/>
> <reg name="hpmcounter31" bitsize="64"/>
> - <reg name="cycleh" bitsize="64"/>
> - <reg name="timeh" bitsize="64"/>
> - <reg name="instreth" bitsize="64"/>
> - <reg name="hpmcounter3h" bitsize="64"/>
> - <reg name="hpmcounter4h" bitsize="64"/>
> - <reg name="hpmcounter5h" bitsize="64"/>
> - <reg name="hpmcounter6h" bitsize="64"/>
> - <reg name="hpmcounter7h" bitsize="64"/>
> - <reg name="hpmcounter8h" bitsize="64"/>
> - <reg name="hpmcounter9h" bitsize="64"/>
> - <reg name="hpmcounter10h" bitsize="64"/>
> - <reg name="hpmcounter11h" bitsize="64"/>
> - <reg name="hpmcounter12h" bitsize="64"/>
> - <reg name="hpmcounter13h" bitsize="64"/>
> - <reg name="hpmcounter14h" bitsize="64"/>
> - <reg name="hpmcounter15h" bitsize="64"/>
> - <reg name="hpmcounter16h" bitsize="64"/>
> - <reg name="hpmcounter17h" bitsize="64"/>
> - <reg name="hpmcounter18h" bitsize="64"/>
> - <reg name="hpmcounter19h" bitsize="64"/>
> - <reg name="hpmcounter20h" bitsize="64"/>
> - <reg name="hpmcounter21h" bitsize="64"/>
> - <reg name="hpmcounter22h" bitsize="64"/>
> - <reg name="hpmcounter23h" bitsize="64"/>
> - <reg name="hpmcounter24h" bitsize="64"/>
> - <reg name="hpmcounter25h" bitsize="64"/>
> - <reg name="hpmcounter26h" bitsize="64"/>
> - <reg name="hpmcounter27h" bitsize="64"/>
> - <reg name="hpmcounter28h" bitsize="64"/>
> - <reg name="hpmcounter29h" bitsize="64"/>
> - <reg name="hpmcounter30h" bitsize="64"/>
> - <reg name="hpmcounter31h" bitsize="64"/>
> <reg name="sstatus" bitsize="64"/>
> <reg name="sedeleg" bitsize="64"/>
> <reg name="sideleg" bitsize="64"/>
> @@ -111,9 +79,7 @@
> <reg name="mtval" bitsize="64"/>
> <reg name="mip" bitsize="64"/>
> <reg name="pmpcfg0" bitsize="64"/>
> - <reg name="pmpcfg1" bitsize="64"/>
> <reg name="pmpcfg2" bitsize="64"/>
> - <reg name="pmpcfg3" bitsize="64"/>
> <reg name="pmpaddr0" bitsize="64"/>
> <reg name="pmpaddr1" bitsize="64"/>
> <reg name="pmpaddr2" bitsize="64"/>
> @@ -161,37 +127,6 @@
> <reg name="mhpmcounter29" bitsize="64"/>
> <reg name="mhpmcounter30" bitsize="64"/>
> <reg name="mhpmcounter31" bitsize="64"/>
> - <reg name="mcycleh" bitsize="64"/>
> - <reg name="minstreth" bitsize="64"/>
> - <reg name="mhpmcounter3h" bitsize="64"/>
> - <reg name="mhpmcounter4h" bitsize="64"/>
> - <reg name="mhpmcounter5h" bitsize="64"/>
> - <reg name="mhpmcounter6h" bitsize="64"/>
> - <reg name="mhpmcounter7h" bitsize="64"/>
> - <reg name="mhpmcounter8h" bitsize="64"/>
> - <reg name="mhpmcounter9h" bitsize="64"/>
> - <reg name="mhpmcounter10h" bitsize="64"/>
> - <reg name="mhpmcounter11h" bitsize="64"/>
> - <reg name="mhpmcounter12h" bitsize="64"/>
> - <reg name="mhpmcounter13h" bitsize="64"/>
> - <reg name="mhpmcounter14h" bitsize="64"/>
> - <reg name="mhpmcounter15h" bitsize="64"/>
> - <reg name="mhpmcounter16h" bitsize="64"/>
> - <reg name="mhpmcounter17h" bitsize="64"/>
> - <reg name="mhpmcounter18h" bitsize="64"/>
> - <reg name="mhpmcounter19h" bitsize="64"/>
> - <reg name="mhpmcounter20h" bitsize="64"/>
> - <reg name="mhpmcounter21h" bitsize="64"/>
> - <reg name="mhpmcounter22h" bitsize="64"/>
> - <reg name="mhpmcounter23h" bitsize="64"/>
> - <reg name="mhpmcounter24h" bitsize="64"/>
> - <reg name="mhpmcounter25h" bitsize="64"/>
> - <reg name="mhpmcounter26h" bitsize="64"/>
> - <reg name="mhpmcounter27h" bitsize="64"/>
> - <reg name="mhpmcounter28h" bitsize="64"/>
> - <reg name="mhpmcounter29h" bitsize="64"/>
> - <reg name="mhpmcounter30h" bitsize="64"/>
> - <reg name="mhpmcounter31h" bitsize="64"/>
> <reg name="mhpmevent3" bitsize="64"/>
> <reg name="mhpmevent4" bitsize="64"/>
> <reg name="mhpmevent5" bitsize="64"/>
> @@ -233,7 +168,6 @@
> <reg name="hcounteren" bitsize="64"/>
> <reg name="hgatp" bitsize="64"/>
> <reg name="htimedelta" bitsize="64"/>
> - <reg name="htimedeltah" bitsize="64"/>
> <reg name="vsstatus" bitsize="64"/>
> <reg name="vsie" bitsize="64"/>
> <reg name="vstvec" bitsize="64"/>
> @@ -243,7 +177,6 @@
> <reg name="vstval" bitsize="64"/>
> <reg name="vsip" bitsize="64"/>
> <reg name="vsatp" bitsize="64"/>
> - <reg name="mstatush" bitsize="64"/>
> <reg name="mcountinhibit" bitsize="64"/>
> <reg name="dscratch0" bitsize="64"/>
> <reg name="dscratch1" bitsize="64"/>
> diff --git a/gdb/features/riscv/rebuild-csr-xml.sh b/gdb/features/riscv/rebuild-csr-xml.sh
> index a3d957c..79fb3cb 100755
> --- a/gdb/features/riscv/rebuild-csr-xml.sh
> +++ b/gdb/features/riscv/rebuild-csr-xml.sh
> @@ -19,10 +19,18 @@ function gen_csr_xml ()
> <feature name="org.gnu.gdb.riscv.csr">
> EOF
>
> +if [ "$bitsize" = "64" ]; then
> grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
> - | sed -e "s!DECLARE_CSR(\(.*\), .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
> + | sed /CSR_CLASS_.*_32/d \
> + | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
>
> echo "</feature>"
> +else
> + grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \
> + | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!"
> +
> + echo "</feature>"
> +fi
> }
>
> gen_csr_xml 32 > ${RISCV_FEATURE_DIR}/32bit-csr.xml
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index a8b057f..63915d2 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature =
> {
> "org.gnu.gdb.riscv.csr",
> {
> -#define DECLARE_CSR(NAME,VALUE) \
> +#define DECLARE_CSR(NAME,VALUE,CLASS) \
> { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> @@ -534,7 +534,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
>
> if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
> {
> -#define DECLARE_CSR(NAME,VALUE) \
> +#define DECLARE_CSR(NAME,VALUE,CLASS) \
> case RISCV_ ## VALUE ## _REGNUM: return # NAME;
>
> switch (regnum)
> @@ -870,7 +870,7 @@ riscv_is_regnum_a_named_csr (int regnum)
>
> switch (regnum)
> {
> -#define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
> +#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM:
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> return true;
> diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
> index 4268839..290ef9f 100644
> --- a/gdb/riscv-tdep.h
> +++ b/gdb/riscv-tdep.h
> @@ -44,7 +44,7 @@ enum
> RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
>
> RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
> -#define DECLARE_CSR(name, num) \
> +#define DECLARE_CSR(name, num, class) \
> RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index ee3d976..3809958 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -1128,284 +1128,284 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
> DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
> #endif
> #ifdef DECLARE_CSR
> -DECLARE_CSR(ustatus, CSR_USTATUS)
> -DECLARE_CSR(uie, CSR_UIE)
> -DECLARE_CSR(utvec, CSR_UTVEC)
> -DECLARE_CSR(uscratch, CSR_USCRATCH)
> -DECLARE_CSR(uepc, CSR_UEPC)
> -DECLARE_CSR(ucause, CSR_UCAUSE)
> -DECLARE_CSR(utval, CSR_UTVAL)
> -DECLARE_CSR(uip, CSR_UIP)
> -DECLARE_CSR(fflags, CSR_FFLAGS)
> -DECLARE_CSR(frm, CSR_FRM)
> -DECLARE_CSR(fcsr, CSR_FCSR)
> -DECLARE_CSR(cycle, CSR_CYCLE)
> -DECLARE_CSR(time, CSR_TIME)
> -DECLARE_CSR(instret, CSR_INSTRET)
> -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
> -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
> -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
> -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
> -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
> -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
> -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
> -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
> -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
> -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
> -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
> -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
> -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
> -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
> -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
> -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
> -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
> -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
> -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
> -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
> -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
> -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
> -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
> -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
> -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
> -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
> -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
> -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
> -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
> -DECLARE_CSR(cycleh, CSR_CYCLEH)
> -DECLARE_CSR(timeh, CSR_TIMEH)
> -DECLARE_CSR(instreth, CSR_INSTRETH)
> -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
> -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
> -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
> -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
> -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
> -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
> -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
> -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
> -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
> -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
> -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
> -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
> -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
> -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
> -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
> -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
> -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
> -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
> -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
> -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
> -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
> -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
> -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
> -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
> -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
> -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
> -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
> -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
> -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
> -DECLARE_CSR(sstatus, CSR_SSTATUS)
> -DECLARE_CSR(sedeleg, CSR_SEDELEG)
> -DECLARE_CSR(sideleg, CSR_SIDELEG)
> -DECLARE_CSR(sie, CSR_SIE)
> -DECLARE_CSR(stvec, CSR_STVEC)
> -DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
> -DECLARE_CSR(sscratch, CSR_SSCRATCH)
> -DECLARE_CSR(sepc, CSR_SEPC)
> -DECLARE_CSR(scause, CSR_SCAUSE)
> -DECLARE_CSR(stval, CSR_STVAL)
> -DECLARE_CSR(sip, CSR_SIP)
> -DECLARE_CSR(satp, CSR_SATP)
> -DECLARE_CSR(mvendorid, CSR_MVENDORID)
> -DECLARE_CSR(marchid, CSR_MARCHID)
> -DECLARE_CSR(mimpid, CSR_MIMPID)
> -DECLARE_CSR(mhartid, CSR_MHARTID)
> -DECLARE_CSR(mstatus, CSR_MSTATUS)
> -DECLARE_CSR(misa, CSR_MISA)
> -DECLARE_CSR(medeleg, CSR_MEDELEG)
> -DECLARE_CSR(mideleg, CSR_MIDELEG)
> -DECLARE_CSR(mie, CSR_MIE)
> -DECLARE_CSR(mtvec, CSR_MTVEC)
> -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
> -DECLARE_CSR(mscratch, CSR_MSCRATCH)
> -DECLARE_CSR(mepc, CSR_MEPC)
> -DECLARE_CSR(mcause, CSR_MCAUSE)
> -DECLARE_CSR(mtval, CSR_MTVAL)
> -DECLARE_CSR(mip, CSR_MIP)
> -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
> -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
> -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
> -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
> -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
> -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
> -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
> -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
> -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
> -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
> -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
> -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
> -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
> -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
> -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
> -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
> -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
> -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
> -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
> -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
> -DECLARE_CSR(mcycle, CSR_MCYCLE)
> -DECLARE_CSR(minstret, CSR_MINSTRET)
> -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
> -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
> -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
> -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
> -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
> -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
> -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
> -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
> -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
> -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
> -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
> -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
> -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
> -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
> -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
> -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
> -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
> -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
> -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
> -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
> -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
> -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
> -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
> -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
> -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
> -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
> -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
> -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
> -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
> -DECLARE_CSR(mcycleh, CSR_MCYCLEH)
> -DECLARE_CSR(minstreth, CSR_MINSTRETH)
> -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
> -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
> -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
> -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
> -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
> -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
> -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
> -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
> -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
> -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
> -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
> -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
> -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
> -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
> -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
> -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
> -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
> -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
> -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
> -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
> -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
> -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
> -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
> -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
> -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
> -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
> -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
> -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
> -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
> -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
> -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
> -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
> -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
> -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
> -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
> -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
> -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
> -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
> -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
> -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
> -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
> -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
> -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
> -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
> -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
> -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
> -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
> -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
> -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
> -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
> -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
> -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
> -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
> -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
> -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
> -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
> -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
> -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
> -DECLARE_CSR(tselect, CSR_TSELECT)
> -DECLARE_CSR(tdata1, CSR_TDATA1)
> -DECLARE_CSR(tdata2, CSR_TDATA2)
> -DECLARE_CSR(tdata3, CSR_TDATA3)
> -DECLARE_CSR(dcsr, CSR_DCSR)
> -DECLARE_CSR(dpc, CSR_DPC)
> +DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I)
> +DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I)
> +DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I)
> +DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I)
> +DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I)
> +DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I)
> +DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I)
> +DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F)
> +DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F)
> +DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F)
> +DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I)
> +DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I)
> +DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I)
> +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I)
> +DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32)
> +DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32)
> +DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32)
> +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32)
> +DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I)
> +DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I)
> +DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I)
> +DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I)
> +DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I)
> +DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I)
> +DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I)
> +DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I)
> +DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I)
> +DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I)
> +DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I)
> +DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I)
> +DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I)
> +DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I)
> +DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I)
> +DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I)
> +DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I)
> +DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I)
> +DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I)
> +DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I)
> +DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I)
> +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I)
> +DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I)
> +DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I)
> +DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I)
> +DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I)
> +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I)
> +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32)
> +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I)
> +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32)
> +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I)
> +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I)
> +DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I)
> +DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I)
> +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I)
> +DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32)
> +DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I)
> +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I)
> +DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I)
> +DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I)
> +DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> +DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> +DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> +DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> /* These registers are present in priv spec 1.12. */
> -DECLARE_CSR(hstatus, CSR_HSTATUS)
> -DECLARE_CSR(hedeleg, CSR_HEDELEG)
> -DECLARE_CSR(hideleg, CSR_HIDELEG)
> -DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
> -DECLARE_CSR(hgatp, CSR_HGATP)
> -DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
> -DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
> -DECLARE_CSR(vsstatus, CSR_VSSTATUS)
> -DECLARE_CSR(vsie, CSR_VSIE)
> -DECLARE_CSR(vstvec, CSR_VSTVEC)
> -DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
> -DECLARE_CSR(vsepc, CSR_VSEPC)
> -DECLARE_CSR(vscause, CSR_VSCAUSE)
> -DECLARE_CSR(vstval, CSR_VSTVAL)
> -DECLARE_CSR(vsip, CSR_VSIP)
> -DECLARE_CSR(vsatp, CSR_VSATP)
> -DECLARE_CSR(mstatush, CSR_MSTATUSH)
> -DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
> -DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
> -DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
> +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I)
> +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I)
> +DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I)
> +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I)
> +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I_32)
> +DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I)
> +DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I)
> +DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I)
> +DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I)
> +DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I)
> +DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I)
> +DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I)
> +DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I)
> +DECLARE_CSR(mstatush, CSR_MSTATUSH, CSR_CLASS_I_32)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> -DECLARE_CSR(mbase, CSR_MBASE)
> -DECLARE_CSR(mbound, CSR_MBOUND)
> -DECLARE_CSR(mibase, CSR_MIBASE)
> -DECLARE_CSR(mibound, CSR_MIBOUND)
> -DECLARE_CSR(mdbase, CSR_MDBASE)
> -DECLARE_CSR(mdbound, CSR_MDBOUND)
> -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
> -DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
> +DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I)
> +DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I)
> +DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> +DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> +DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> +DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> +DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> #endif
> #ifdef DECLARE_CSR_ALIAS
> /* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
> -DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
> +DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I)
> /* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */
> -DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
> +DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> /* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */
> -DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
> +DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> -DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
> +DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> /* Hie is 0x204 in 1.9.1, but 0x204 is vsie in 1.12. */
> -DECLARE_CSR_ALIAS(hie, CSR_VSIE)
> +DECLARE_CSR_ALIAS(hie, CSR_VSIE, CSR_CLASS_I)
> /* Htvec is 0x205 in 1.9.1, but 0x205 is vstvec in 1.12. */
> -DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC)
> +DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC, CSR_CLASS_I)
> /* Hscratch is 0x240 in 1.9.1, but 0x240 is vsscratch in 1.12. */
> -DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH)
> +DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH, CSR_CLASS_I)
> /* Hepc is 0x241 in 1.9.1, but 0x241 is vsepc in 1.12. */
> -DECLARE_CSR_ALIAS(hepc, CSR_VSEPC)
> +DECLARE_CSR_ALIAS(hepc, CSR_VSEPC, CSR_CLASS_I)
> /* Hcause is 0x242 in 1.9.1, but 0x242 is vscause in 1.12. */
> -DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE)
> +DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE, CSR_CLASS_I)
> /* Hbadaddr is 0x243 in 1.9.1, but 0x243 is vstval in 1.12. */
> -DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL)
> +DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL, CSR_CLASS_I)
> /* Hip is 0x244 in 1.9.1, but 0x244 is vsip in 1.12. */
> -DECLARE_CSR_ALIAS(hip, CSR_VSIP)
> +DECLARE_CSR_ALIAS(hip, CSR_VSIP, CSR_CLASS_I)
> /* Mucounteren is 0x320 in 1.9.1, but 0x320 is mcountinhibit in 1.12. */
> -DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT)
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> /* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.12. */
> -DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0)
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 40893c3..9674d3a 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -326,7 +326,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
> unsigned int csr = EXTRACT_OPERAND (CSR, l);
> switch (csr)
> {
> -#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
> +#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break;
> #include "opcode/riscv-opc.h"
> #undef DECLARE_CSR
> }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PING] [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
@ 2020-01-03 1:31 ` Nelson Chu
2020-02-01 2:38 ` Jim Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-01-03 1:31 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Jim Wilson, Andrew Waterman, Kito Cheng
PING :)
On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write CSR
> when RS1 isn't zero. The CSR is read only if the [11:10] bits of CSR address
> is 0x3. The read-only CSR can not be written by the CSR instructions.
>
> gas/
> * config/tc-riscv.c (insn_with_csr): New boolean to indicate we are
> assembling instruction with CSR.
> (enum csr_insn_type): New enum is used to classify the CSR instruction.
> (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
> are used to check if we write a read-only CSR by the CSR instruction.
> (riscv_ip): Call riscv_csr_read_only_check after parsing all arguments.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
> all CSR for the read-only CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
> all CSR instructions for the read-only CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
> ---
> gas/config/tc-riscv.c | 65 +++++
> .../gas/riscv/priv-reg-fail-read-only-01.d | 3 +
> .../gas/riscv/priv-reg-fail-read-only-01.l | 69 +++++
> .../gas/riscv/priv-reg-fail-read-only-01.s | 295 +++++++++++++++++++++
> .../gas/riscv/priv-reg-fail-read-only-02.d | 3 +
> .../gas/riscv/priv-reg-fail-read-only-02.l | 25 ++
> .../gas/riscv/priv-reg-fail-read-only-02.s | 90 +++++++
> 7 files changed, 550 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 4c9ff52..592864b 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -195,6 +195,9 @@ static bfd_boolean start_assemble = FALSE;
> /* Indicate arch attribute is explictly set. */
> static bfd_boolean explicit_arch_attr = FALSE;
>
> +/* Indicate we are assembling instruction with CSR. */
> +static bfd_boolean insn_with_csr = FALSE;
> +
> /* Macros for encoding relaxation state for RVC branches and far jumps. */
> #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
> ((relax_substateT) \
> @@ -1473,6 +1476,52 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
> return FALSE;
> }
>
> +enum csr_insn_type
> +{
> + INSN_NOT_CSR,
> + INSN_CSRRW,
> + INSN_CSRRS,
> + INSN_CSRRC
> +};
> +
> +static enum csr_insn_type
> +riscv_csr_insn_type (insn_t insn)
> +{
> + if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0
> + || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0)
> + return INSN_CSRRW;
> + else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0
> + || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0)
> + return INSN_CSRRS;
> + else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0
> + || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0)
> + return INSN_CSRRC;
> + else
> + return INSN_NOT_CSR;
> +}
> +
> +/* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
> + CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
> + CSR address is 0x3. */
> +
> +static bfd_boolean
> +riscv_csr_read_only_check (insn_t insn)
> +{
> + int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR;
> + int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1;
> + int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3);
> + enum csr_insn_type csr_insn = riscv_csr_insn_type (insn);
> +
> + if (readonly
> + && (((csr_insn == INSN_CSRRS
> + || csr_insn == INSN_CSRRC)
> + && rs1 != 0)
> + || csr_insn == INSN_CSRRW))
> + return FALSE;
> +
> + return TRUE;
> +}
> +
> /* This routine assembles an instruction into its binary format. As a
> side effect, it sets the global variable imm_reloc to the type of
> relocation to do if one of the operands is an address expression. */
> @@ -1537,11 +1586,25 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> : insn->match) == 2
> && !riscv_opts.rvc)
> break;
> +
> + /* Check if we write a read-only CSR by the CSR
> + instruction. */
> + if (insn_with_csr
> + && !riscv_csr_read_only_check (ip->insn_opcode))
> + {
> + /* Don't parse the next insn in the riscv_opcode.
> + Otherwise, we will get multiple unexpected error
> + message. */
> + error = _("Read-only CSR is used");
> + insn_with_csr = FALSE;
> + goto out;
> + }
> }
> if (*s != '\0')
> break;
> /* Successful assembly. */
> error = NULL;
> + insn_with_csr = FALSE;
> goto out;
>
> case 'C': /* RVC */
> @@ -1886,6 +1949,7 @@ rvc_lui:
> continue;
>
> case 'E': /* Control register. */
> + insn_with_csr = TRUE;
> if (reg_lookup (&s, RCLASS_CSR, ®no))
> INSERT_OPERAND (CSR, *ip, regno);
> else
> @@ -2206,6 +2270,7 @@ jump:
> }
> s = argsStart;
> error = _("illegal operands");
> + insn_with_csr = FALSE;
> }
>
> out:
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> new file mode 100644
> index 0000000..9c93d8a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if
> +#source: priv-reg-fail-read-only-01.s
> +#error_output: priv-reg-fail-read-only-01.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> new file mode 100644
> index 0000000..43beeb7
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l
> @@ -0,0 +1,69 @@
> +.*Assembler messages:
> +.*Error: Read-only CSR is used `csrw cycle,a1'
> +.*Error: Read-only CSR is used `csrw time,a1'
> +.*Error: Read-only CSR is used `csrw instret,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter3,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter4,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter5,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter6,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter7,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter8,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter9,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter10,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter11,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter12,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter13,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter14,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter15,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter16,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter17,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter18,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter19,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter20,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter21,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter22,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter23,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter24,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter25,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter26,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter27,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter28,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter29,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter30,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter31,a1'
> +.*Error: Read-only CSR is used `csrw cycleh,a1'
> +.*Error: Read-only CSR is used `csrw timeh,a1'
> +.*Error: Read-only CSR is used `csrw instreth,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter3h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter4h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter5h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter6h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter7h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter8h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter9h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter10h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter11h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter12h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter13h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter14h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter15h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter16h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter17h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter18h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter19h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter20h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter21h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter22h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter23h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter24h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter25h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter26h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter27h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter28h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter29h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter30h,a1'
> +.*Error: Read-only CSR is used `csrw hpmcounter31h,a1'
> +.*Error: Read-only CSR is used `csrw mvendorid,a1'
> +.*Error: Read-only CSR is used `csrw marchid,a1'
> +.*Error: Read-only CSR is used `csrw mimpid,a1'
> +.*Error: Read-only CSR is used `csrw mhartid,a1'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> new file mode 100644
> index 0000000..9e8937a
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> @@ -0,0 +1,295 @@
> +# From priv spec 1.9.1 to 1.12 registers.
> +
> + .macro csr val
> + csrw \val, a1
> + .endm
> +
> +# User-Level CSR Addresses in 1.12.
> + csr ustatus
> + csr uie
> + csr utvec
> +
> + csr uscratch
> + csr uepc
> + csr ucause
> + csr utval
> + csr uip
> +
> + csr fflags
> + csr frm
> + csr fcsr
> +
> + csr cycle
> + csr time
> + csr instret
> + csr hpmcounter3
> + csr hpmcounter4
> + csr hpmcounter5
> + csr hpmcounter6
> + csr hpmcounter7
> + csr hpmcounter8
> + csr hpmcounter9
> + csr hpmcounter10
> + csr hpmcounter11
> + csr hpmcounter12
> + csr hpmcounter13
> + csr hpmcounter14
> + csr hpmcounter15
> + csr hpmcounter16
> + csr hpmcounter17
> + csr hpmcounter18
> + csr hpmcounter19
> + csr hpmcounter20
> + csr hpmcounter21
> + csr hpmcounter22
> + csr hpmcounter23
> + csr hpmcounter24
> + csr hpmcounter25
> + csr hpmcounter26
> + csr hpmcounter27
> + csr hpmcounter28
> + csr hpmcounter29
> + csr hpmcounter30
> + csr hpmcounter31
> + csr cycleh
> + csr timeh
> + csr instreth
> + csr hpmcounter3h
> + csr hpmcounter4h
> + csr hpmcounter5h
> + csr hpmcounter6h
> + csr hpmcounter7h
> + csr hpmcounter8h
> + csr hpmcounter9h
> + csr hpmcounter10h
> + csr hpmcounter11h
> + csr hpmcounter12h
> + csr hpmcounter13h
> + csr hpmcounter14h
> + csr hpmcounter15h
> + csr hpmcounter16h
> + csr hpmcounter17h
> + csr hpmcounter18h
> + csr hpmcounter19h
> + csr hpmcounter20h
> + csr hpmcounter21h
> + csr hpmcounter22h
> + csr hpmcounter23h
> + csr hpmcounter24h
> + csr hpmcounter25h
> + csr hpmcounter26h
> + csr hpmcounter27h
> + csr hpmcounter28h
> + csr hpmcounter29h
> + csr hpmcounter30h
> + csr hpmcounter31h
> +
> +# Supervisor-level CSR Addresses in 1.12.
> + csr sstatus
> + csr sedeleg
> + csr sideleg
> + csr sie
> + csr stvec
> + csr scounteren
> +
> + csr sscratch
> + csr sepc
> + csr scause
> + csr stval
> + csr sip
> +
> + csr satp
> +
> +# Hypervisor-Level CSR Addresses in 1.12.
> + csr hstatus
> + csr hedeleg
> + csr hideleg
> + csr hcounteren
> +
> + csr hgatp
> +
> + csr htimedelta
> + csr htimedeltah
> +
> + csr vsstatus
> + csr vsie
> + csr vstvec
> + csr vsscratch
> + csr vsepc
> + csr vscause
> + csr vstval
> + csr vsip
> + csr vsatp
> +
> +# Machine-Level CSR Addresses in 1.12.
> + csr mvendorid
> + csr marchid
> + csr mimpid
> + csr mhartid
> +
> + csr mstatus
> + csr misa
> + csr medeleg
> + csr mideleg
> + csr mie
> + csr mtvec
> + csr mcounteren
> + csr mstatush
> +
> + csr mscratch
> + csr mepc
> + csr mcause
> + csr mtval
> + csr mip
> +
> + csr pmpcfg0
> + csr pmpcfg1
> + csr pmpcfg2
> + csr pmpcfg3
> + csr pmpaddr0
> + csr pmpaddr1
> + csr pmpaddr2
> + csr pmpaddr3
> + csr pmpaddr4
> + csr pmpaddr5
> + csr pmpaddr6
> + csr pmpaddr7
> + csr pmpaddr8
> + csr pmpaddr9
> + csr pmpaddr10
> + csr pmpaddr11
> + csr pmpaddr12
> + csr pmpaddr13
> + csr pmpaddr14
> + csr pmpaddr15
> +
> + csr mcycle
> + csr minstret
> + csr mhpmcounter3
> + csr mhpmcounter4
> + csr mhpmcounter5
> + csr mhpmcounter6
> + csr mhpmcounter7
> + csr mhpmcounter8
> + csr mhpmcounter9
> + csr mhpmcounter10
> + csr mhpmcounter11
> + csr mhpmcounter12
> + csr mhpmcounter13
> + csr mhpmcounter14
> + csr mhpmcounter15
> + csr mhpmcounter16
> + csr mhpmcounter17
> + csr mhpmcounter18
> + csr mhpmcounter19
> + csr mhpmcounter20
> + csr mhpmcounter21
> + csr mhpmcounter22
> + csr mhpmcounter23
> + csr mhpmcounter24
> + csr mhpmcounter25
> + csr mhpmcounter26
> + csr mhpmcounter27
> + csr mhpmcounter28
> + csr mhpmcounter29
> + csr mhpmcounter30
> + csr mhpmcounter31
> + csr mcycleh
> + csr minstreth
> + csr mhpmcounter3h
> + csr mhpmcounter4h
> + csr mhpmcounter5h
> + csr mhpmcounter6h
> + csr mhpmcounter7h
> + csr mhpmcounter8h
> + csr mhpmcounter9h
> + csr mhpmcounter10h
> + csr mhpmcounter11h
> + csr mhpmcounter12h
> + csr mhpmcounter13h
> + csr mhpmcounter14h
> + csr mhpmcounter15h
> + csr mhpmcounter16h
> + csr mhpmcounter17h
> + csr mhpmcounter18h
> + csr mhpmcounter19h
> + csr mhpmcounter20h
> + csr mhpmcounter21h
> + csr mhpmcounter22h
> + csr mhpmcounter23h
> + csr mhpmcounter24h
> + csr mhpmcounter25h
> + csr mhpmcounter26h
> + csr mhpmcounter27h
> + csr mhpmcounter28h
> + csr mhpmcounter29h
> + csr mhpmcounter30h
> + csr mhpmcounter31h
> +
> + csr mcountinhibit
> + csr mhpmevent3
> + csr mhpmevent4
> + csr mhpmevent5
> + csr mhpmevent6
> + csr mhpmevent7
> + csr mhpmevent8
> + csr mhpmevent9
> + csr mhpmevent10
> + csr mhpmevent11
> + csr mhpmevent12
> + csr mhpmevent13
> + csr mhpmevent14
> + csr mhpmevent15
> + csr mhpmevent16
> + csr mhpmevent17
> + csr mhpmevent18
> + csr mhpmevent19
> + csr mhpmevent20
> + csr mhpmevent21
> + csr mhpmevent22
> + csr mhpmevent23
> + csr mhpmevent24
> + csr mhpmevent25
> + csr mhpmevent26
> + csr mhpmevent27
> + csr mhpmevent28
> + csr mhpmevent29
> + csr mhpmevent30
> + csr mhpmevent31
> +
> + csr tselect
> + csr tdata1
> + csr tdata2
> + csr tdata3
> +
> + csr dcsr
> + csr dpc
> + csr dscratch0
> + csr dscratch1
> +
> +# Defined in 1.9.1, but alias for another CSR in 1.12.
> + csr ubadaddr # utval
> + csr sbadaddr # stval
> + csr sptbr # satp
> + csr hie # vsie
> + csr htvec # vstvec
> + csr hscratch # vsscratch
> + csr hepc # vsepc
> + csr hcause # vscause
> + csr hbadaddr # vstval
> + csr hip # vsip
> + csr mbadaddr # mtval
> + csr mucounteren # mcountinhibit
> +
> +# Defined in 1.9.1, but dropped in 1.10.
> + csr mscounteren
> + csr mhcounteren
> + csr mbase
> + csr mbound
> + csr mibase
> + csr mibound
> + csr mdbase
> + csr mdbound
> +
> +# Defined in 1.10, but dropped in 1.12.
> + csr dscratch # dscratch0
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> new file mode 100644
> index 0000000..ede45c5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32if
> +#source: priv-reg-fail-read-only-02.s
> +#error_output: priv-reg-fail-read-only-02.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
> new file mode 100644
> index 0000000..dce8e0e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.l
> @@ -0,0 +1,25 @@
> +.*Assembler messages:
> +.*Error: Read-only CSR is used `csrrw a0,cycle,a1'
> +.*Error: Read-only CSR is used `csrrw a0,cycle,zero'
> +.*Error: Read-only CSR is used `csrrw zero,cycle,a1'
> +.*Error: Read-only CSR is used `csrrw zero,cycle,zero'
> +.*Error: Read-only CSR is used `csrw cycle,a1'
> +.*Error: Read-only CSR is used `csrw cycle,zero'
> +.*Error: Read-only CSR is used `csrrwi a0,cycle,0xb'
> +.*Error: Read-only CSR is used `csrrwi a0,cycle,0x0'
> +.*Error: Read-only CSR is used `csrrwi zero,cycle,0xb'
> +.*Error: Read-only CSR is used `csrrwi zero,cycle,0x0'
> +.*Error: Read-only CSR is used `csrwi cycle,0xb'
> +.*Error: Read-only CSR is used `csrwi cycle,0x0'
> +.*Error: Read-only CSR is used `csrrs a0,cycle,a1'
> +.*Error: Read-only CSR is used `csrrs zero,cycle,a1'
> +.*Error: Read-only CSR is used `csrs cycle,a0'
> +.*Error: Read-only CSR is used `csrrsi a0,cycle,0xb'
> +.*Error: Read-only CSR is used `csrrsi zero,cycle,0xb'
> +.*Error: Read-only CSR is used `csrsi cycle,0xb'
> +.*Error: Read-only CSR is used `csrrc a0,cycle,a1'
> +.*Error: Read-only CSR is used `csrrc zero,cycle,a1'
> +.*Error: Read-only CSR is used `csrc cycle,a0'
> +.*Error: Read-only CSR is used `csrrci a0,cycle,0xb'
> +.*Error: Read-only CSR is used `csrrci zero,cycle,0xb'
> +.*Error: Read-only CSR is used `csrci cycle,0xb'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
> new file mode 100644
> index 0000000..7afb26e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.s
> @@ -0,0 +1,90 @@
> +# CSRRW and CSRRWI always write CSR
> +# CSRRS, CSRRC, CSRRSI and CSRRCI write CSR when rs isn't zero.
> +
> +# csrrw rd, csr, rs
> + csrrw a0, ustatus, a1
> + csrrw a0, cycle, a1
> + csrrw a0, cycle, zero
> + csrrw zero, cycle, a1
> + csrrw zero, cycle, zero
> + fscsr a0, a1
> + fsrm a0, a1
> + fsflags a0, a1
> +# csrrw zero, csr, rs
> + csrw ustatus, a1
> + csrw cycle, a1
> + csrw cycle, zero
> + fscsr a1
> + fsrm a1
> + fsflags a1
> +# csrrwi rd, csr, imm
> + csrrwi a0, ustatus, 0xb
> + csrrwi a0, cycle, 0xb
> + csrrwi a0, cycle, 0x0
> + csrrwi zero, cycle, 0xb
> + csrrwi zero, cycle, 0x0
> +# csrrwi zero, csr, imm
> + csrwi ustatus, 0xb
> + csrwi cycle, 0xb
> + csrwi cycle, 0x0
> +
> +# csrrs rd, csr, rs
> + csrrs a0, ustatus, a1
> + csrrs a0, cycle, a1
> + csrrs a0, cycle, zero
> + csrrs zero, cycle, a1
> + csrrs zero, cycle, zero
> +# csrrs rd, csr, zero
> + csrr a0, ustatus
> + csrr a0, cycle
> + csrr zero, cycle
> + rdinstret a0
> + rdinstret zero
> + rdinstreth a0
> + rdinstreth zero
> + rdcycle a0
> + rdcycle zero
> + rdcycleh a0
> + rdcycleh zero
> + rdtime a0
> + rdtime zero
> + rdtimeh a0
> + rdtimeh zero
> + frcsr a0
> + frrm a0
> + frflags a0
> +# csrrs zero, csr, rs
> + csrs ustatus, a0
> + csrs cycle, a0
> + csrs cycle, zero
> +# csrrsi rd, csr, imm
> + csrrsi a0, ustatus, 0xb
> + csrrsi a0, cycle, 0xb
> + csrrsi a0, cycle, 0x0
> + csrrsi zero, cycle, 0xb
> + csrrsi zero, cycle, 0x0
> +# csrrsi zero, csr, imm
> + csrsi ustatus, 0xb
> + csrsi cycle, 0xb
> + csrsi cycle, 0x0
> +
> +# csrrc a0, csr, a1
> + csrrc a0, ustatus, a1
> + csrrc a0, cycle, a1
> + csrrc a0, cycle, zero
> + csrrc zero, cycle, a1
> + csrrc zero, cycle, zero
> +# csrrc zero, csr, rs
> + csrc ustatus, a0
> + csrc cycle, a0
> + csrc cycle, zero
> +# csrrci rd, csr, imm
> + csrrci a0, ustatus, 0xb
> + csrrci a0, cycle, 0xb
> + csrrci a0, cycle, 0x0
> + csrrci zero, cycle, 0xb
> + csrrci zero, cycle, 0x0
> +# csrrci zero, csr, imm
> + csrci ustatus, 0xb
> + csrci cycle, 0xb
> + csrci cycle, 0x0
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PING] [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2019-12-16 5:21 ` [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12 Nelson Chu
@ 2020-01-03 1:31 ` Nelson Chu
2020-02-01 0:19 ` Jim Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-01-03 1:31 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Jim Wilson, Andrew Waterman, Kito Cheng
PING :)
On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> gas/
> * testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s Update
> the CSR to privilege spec 1.12.
> * testsuite/gas/riscv/priv-reg.d: Likewise.
> * testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
> * testsuite/gas/riscv/bad-csr.d: Likewise.
> * testsuite/gas/riscv/bad-csr.l: Likewise.
> * testsuite/gas/riscv/satp.s: Deleted. Duplicate of priv-reg-all.s
> * testsuite/gas/riscv/satp.d: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.s: Updated.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
>
> include/
> * opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.
>
> gdb/
> * features/riscv/32bit-csr.xml: Regenerated.
> * features/riscv/64bit-csr.xml: Regenerated.
> ---
> gas/testsuite/gas/riscv/bad-csr.d | 3 -
> gas/testsuite/gas/riscv/bad-csr.l | 2 -
> gas/testsuite/gas/riscv/bad-csr.s | 1 -
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 52 ++--
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 53 ++--
> gas/testsuite/gas/riscv/priv-reg-all.d | 270 +++++++++++++++++++
> gas/testsuite/gas/riscv/priv-reg-all.s | 295 +++++++++++++++++++++
> .../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
> .../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
> .../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
> gas/testsuite/gas/riscv/priv-reg.d | 253 ------------------
> gas/testsuite/gas/riscv/priv-reg.s | 269 -------------------
> gas/testsuite/gas/riscv/satp.d | 11 -
> gas/testsuite/gas/riscv/satp.s | 3 -
> gdb/features/riscv/32bit-csr.xml | 26 +-
> gdb/features/riscv/64bit-csr.xml | 26 +-
> include/opcode/riscv-opc.h | 83 ++++--
> 17 files changed, 735 insertions(+), 618 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-all.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> delete mode 100644 gas/testsuite/gas/riscv/priv-reg.d
> delete mode 100644 gas/testsuite/gas/riscv/priv-reg.s
> delete mode 100644 gas/testsuite/gas/riscv/satp.d
> delete mode 100644 gas/testsuite/gas/riscv/satp.s
>
> diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
> deleted file mode 100644
> index 6863123..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as:
> -#source: bad-csr.s
> -#error_output: bad-csr.l
> diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
> deleted file mode 100644
> index a0bb8a6..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
> deleted file mode 100644
> index 6e6d27e..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.s
> +++ /dev/null
> @@ -1 +0,0 @@
> - csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index 597747c..14d1300 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -104,6 +104,22 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> DW_CFA_offset_extended_sf: r4420 \(sip\) at cfa\+1296
> DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> + DW_CFA_offset_extended_sf: r5632 \(hstatus\) at cfa\+6144
> + DW_CFA_offset_extended_sf: r5634 \(hedeleg\) at cfa\+6152
> + DW_CFA_offset_extended_sf: r5635 \(hideleg\) at cfa\+6156
> + DW_CFA_offset_extended_sf: r5638 \(hcounteren\) at cfa\+6168
> + DW_CFA_offset_extended_sf: r5760 \(hgatp\) at cfa\+6656
> + DW_CFA_offset_extended_sf: r5637 \(htimedelta\) at cfa\+6164
> + DW_CFA_offset_extended_sf: r5653 \(htimedeltah\) at cfa\+6228
> + DW_CFA_offset_extended_sf: r4608 \(vsstatus\) at cfa\+2048
> + DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
> + DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
> + DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
> + DW_CFA_offset_extended_sf: r4673 \(vsepc) at cfa\+2308
> + DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
> + DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
> + DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
> + DW_CFA_offset_extended_sf: r4736 \(vsatp\) at cfa\+2560
> DW_CFA_offset_extended_sf: r7953 \(mvendorid\) at cfa\+15428
> DW_CFA_offset_extended_sf: r7954 \(marchid\) at cfa\+15432
> DW_CFA_offset_extended_sf: r7955 \(mimpid\) at cfa\+15436
> @@ -202,6 +218,7 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
> DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
> DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
> DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
> DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
> @@ -237,29 +254,28 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
> DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
> DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
> - DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
> - DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
> - DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
> - DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
> - DW_CFA_offset_extended_sf: r4612 \(hie\) at cfa\+2064
> - DW_CFA_offset_extended_sf: r4613 \(htvec\) at cfa\+2068
> - DW_CFA_offset_extended_sf: r4672 \(hscratch\) at cfa\+2304
> - DW_CFA_offset_extended_sf: r4673 \(hepc\) at cfa\+2308
> - DW_CFA_offset_extended_sf: r4674 \(hcause\) at cfa\+2312
> - DW_CFA_offset_extended_sf: r4675 \(hbadaddr\) at cfa\+2316
> - DW_CFA_offset_extended_sf: r4676 \(hip\) at cfa\+2320
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
> + DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> + DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> + DW_CFA_offset_extended_sf: r4612 \(vsie\) at cfa\+2064
> + DW_CFA_offset_extended_sf: r4613 \(vstvec\) at cfa\+2068
> + DW_CFA_offset_extended_sf: r4672 \(vsscratch\) at cfa\+2304
> + DW_CFA_offset_extended_sf: r4673 \(vsepc\) at cfa\+2308
> + DW_CFA_offset_extended_sf: r4674 \(vscause\) at cfa\+2312
> + DW_CFA_offset_extended_sf: r4675 \(vstval\) at cfa\+2316
> + DW_CFA_offset_extended_sf: r4676 \(vsip\) at cfa\+2320
> + DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> + DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> + DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+320
> DW_CFA_offset_extended_sf: r4992 \(mbase\) at cfa\+3584
> DW_CFA_offset_extended_sf: r4993 \(mbound\) at cfa\+3588
> DW_CFA_offset_extended_sf: r4994 \(mibase\) at cfa\+3592
> DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
> DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
> DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
> - DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
> - DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> - DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
> - DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
> - DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> - DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> - DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> DW_CFA_nop
> #...
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index b29e9da..93f293f 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -94,6 +94,22 @@ _start:
> .cfi_offset stval, 1292
> .cfi_offset sip, 1296
> .cfi_offset satp, 1536
> + .cfi_offset hstatus, 6144
> + .cfi_offset hedeleg, 6152
> + .cfi_offset hideleg, 6156
> + .cfi_offset hcounteren, 6168
> + .cfi_offset hgatp, 6656
> + .cfi_offset htimedelta, 6164
> + .cfi_offset htimedeltah, 6228
> + .cfi_offset vsstatus, 2048
> + .cfi_offset vsie, 2064
> + .cfi_offset vstvec, 2068
> + .cfi_offset vsscratch, 2304
> + .cfi_offset vsepc, 2308
> + .cfi_offset vscause, 2312
> + .cfi_offset vstval, 2316
> + .cfi_offset vsip, 2320
> + .cfi_offset vsatp, 2560
> .cfi_offset mvendorid, 15428
> .cfi_offset marchid, 15432
> .cfi_offset mimpid, 15436
> @@ -105,6 +121,7 @@ _start:
> .cfi_offset mie, 3088
> .cfi_offset mtvec, 3092
> .cfi_offset mcounteren, 3096
> + .cfi_offset mstatush, 3136
> .cfi_offset mscratch, 3328
> .cfi_offset mepc, 3332
> .cfi_offset mcause, 3336
> @@ -192,6 +209,7 @@ _start:
> .cfi_offset mhpmcounter29h, 11892
> .cfi_offset mhpmcounter30h, 11896
> .cfi_offset mhpmcounter31h, 11900
> + .cfi_offset mcountinhibit, 3200
> .cfi_offset mhpmevent3, 3212
> .cfi_offset mhpmevent4, 3216
> .cfi_offset mhpmevent5, 3220
> @@ -227,29 +245,28 @@ _start:
> .cfi_offset tdata3, 7820
> .cfi_offset dcsr, 7872
> .cfi_offset dpc, 7876
> - .cfi_offset dscratch, 7880
> - .cfi_offset hstatus, 2048
> - .cfi_offset hedeleg, 2056
> - .cfi_offset hideleg, 2060
> - .cfi_offset hie, 2064
> - .cfi_offset htvec, 2068
> - .cfi_offset hscratch, 2304
> - .cfi_offset hepc, 2308
> - .cfi_offset hcause, 2312
> - .cfi_offset hbadaddr, 2316
> - .cfi_offset hip, 2320
> + .cfi_offset dscratch0, 7880
> + .cfi_offset dscratch1, 7884
> + .cfi_offset ubadaddr, 268 # utval
> + .cfi_offset sbadaddr, 1292 # stval
> + .cfi_offset sptbr, 1536 # satp
> + .cfi_offset hie, 2064 # vsie
> + .cfi_offset htvec, 2068 # vstvec
> + .cfi_offset hscratch, 2304 # vsscratch
> + .cfi_offset hepc, 2308 # vsepc
> + .cfi_offset hcause, 2312 # vscause
> + .cfi_offset hbadaddr, 2316 # vstval
> + .cfi_offset hip, 2320 # vsip
> + .cfi_offset mbadaddr, 3340 # mtval
> + .cfi_offset mucounteren, 3200 # mcountinhibit
> + .cfi_offset mscounteren, 3204
> + .cfi_offset mhcounteren, 3208
> .cfi_offset mbase, 3584
> .cfi_offset mbound, 3588
> .cfi_offset mibase, 3592
> .cfi_offset mibound, 3596
> .cfi_offset mdbase, 3600
> .cfi_offset mdbound, 3604
> - .cfi_offset mucounteren, 3200
> - .cfi_offset mscounteren, 3204
> - .cfi_offset mhcounteren, 3208
> - .cfi_offset ubadaddr, 268
> - .cfi_offset sbadaddr, 1292
> - .cfi_offset sptbr, 1536
> - .cfi_offset mbadaddr, 3340
> + .cfi_offset dscratch, 7880 # dscratch0
> nop
> .cfi_endproc
> diff --git a/gas/testsuite/gas/riscv/priv-reg-all.d b/gas/testsuite/gas/riscv/priv-reg-all.d
> new file mode 100644
> index 0000000..d86e8c4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-all.d
> @@ -0,0 +1,270 @@
> +#as: -march=rv32if
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> +.*:[ ]+00402573[ ]+csrr[ ]+a0,uie
> +.*:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> +.*:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> +.*:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> +.*:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> +.*:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +.*:[ ]+04402573[ ]+csrr[ ]+a0,uip
> +.*:[ ]+00102573[ ]+frflags[ ]+a0
> +.*:[ ]+00202573[ ]+frrm[ ]+a0
> +.*:[ ]+00302573[ ]+frcsr[ ]+a0
> +.*:[ ]+c0002573[ ]+rdcycle[ ]+a0
> +.*:[ ]+c0102573[ ]+rdtime[ ]+a0
> +.*:[ ]+c0202573[ ]+rdinstret[ ]+a0
> +.*:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> +.*:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> +.*:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> +.*:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> +.*:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> +.*:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> +.*:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> +.*:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> +.*:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> +.*:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> +.*:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> +.*:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> +.*:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> +.*:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> +.*:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> +.*:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> +.*:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> +.*:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> +.*:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> +.*:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> +.*:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> +.*:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> +.*:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> +.*:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> +.*:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> +.*:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> +.*:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> +.*:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> +.*:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> +.*:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> +.*:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> +.*:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> +.*:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> +.*:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> +.*:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> +.*:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> +.*:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> +.*:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> +.*:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> +.*:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> +.*:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> +.*:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> +.*:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> +.*:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> +.*:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> +.*:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> +.*:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> +.*:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> +.*:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> +.*:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> +.*:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> +.*:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> +.*:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> +.*:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> +.*:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> +.*:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> +.*:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> +.*:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> +.*:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> +.*:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> +.*:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> +.*:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> +.*:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> +.*:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> +.*:[ ]+10402573[ ]+csrr[ ]+a0,sie
> +.*:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> +.*:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> +.*:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> +.*:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> +.*:[ ]+14202573[ ]+csrr[ ]+a0,scause
> +.*:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +.*:[ ]+14402573[ ]+csrr[ ]+a0,sip
> +.*:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +.*:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
> +.*:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
> +.*:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
> +.*:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
> +.*:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
> +.*:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
> +.*:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah
> +.*:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
> +.*:[ ]+20402573[ ]+csrr[ ]+a0,vsie
> +.*:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
> +.*:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
> +.*:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
> +.*:[ ]+24202573[ ]+csrr[ ]+a0,vscause
> +.*:[ ]+24302573[ ]+csrr[ ]+a0,vstval
> +.*:[ ]+24402573[ ]+csrr[ ]+a0,vsip
> +.*:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
> +.*:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> +.*:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> +.*:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> +.*:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> +.*:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> +.*:[ ]+30102573[ ]+csrr[ ]+a0,misa
> +.*:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> +.*:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> +.*:[ ]+30402573[ ]+csrr[ ]+a0,mie
> +.*:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> +.*:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> +.*:[ ]+31002573[ ]+csrr[ ]+a0,mstatush
> +.*:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> +.*:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> +.*:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> +.*:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +.*:[ ]+34402573[ ]+csrr[ ]+a0,mip
> +.*:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> +.*:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> +.*:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> +.*:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> +.*:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> +.*:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> +.*:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> +.*:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> +.*:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> +.*:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> +.*:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> +.*:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> +.*:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> +.*:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> +.*:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> +.*:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> +.*:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> +.*:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> +.*:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> +.*:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> +.*:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> +.*:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> +.*:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> +.*:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> +.*:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> +.*:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> +.*:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> +.*:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> +.*:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> +.*:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> +.*:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> +.*:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> +.*:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> +.*:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> +.*:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> +.*:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> +.*:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> +.*:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> +.*:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> +.*:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> +.*:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> +.*:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> +.*:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> +.*:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> +.*:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> +.*:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> +.*:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> +.*:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> +.*:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> +.*:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> +.*:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> +.*:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> +.*:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> +.*:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> +.*:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> +.*:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> +.*:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> +.*:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> +.*:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> +.*:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> +.*:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> +.*:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> +.*:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> +.*:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> +.*:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> +.*:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> +.*:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> +.*:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> +.*:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> +.*:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> +.*:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> +.*:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> +.*:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> +.*:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> +.*:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> +.*:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> +.*:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> +.*:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> +.*:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> +.*:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> +.*:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> +.*:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> +.*:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +.*:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> +.*:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> +.*:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> +.*:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> +.*:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> +.*:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> +.*:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> +.*:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> +.*:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> +.*:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> +.*:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> +.*:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> +.*:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> +.*:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> +.*:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> +.*:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> +.*:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> +.*:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> +.*:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> +.*:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> +.*:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> +.*:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> +.*:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> +.*:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> +.*:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> +.*:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> +.*:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> +.*:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> +.*:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> +.*:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> +.*:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> +.*:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> +.*:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> +.*:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> +.*:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> +.*:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +.*:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> +.*:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +.*:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +.*:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +.*:[ ]+20402573[ ]+csrr[ ]+a0,vsie
> +.*:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
> +.*:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
> +.*:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
> +.*:[ ]+24202573[ ]+csrr[ ]+a0,vscause
> +.*:[ ]+24302573[ ]+csrr[ ]+a0,vstval
> +.*:[ ]+24402573[ ]+csrr[ ]+a0,vsip
> +.*:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +.*:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +.*:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> +.*:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> +.*:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> +.*:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> +.*:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> +.*:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> +.*:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> +.*:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> +.*:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> diff --git a/gas/testsuite/gas/riscv/priv-reg-all.s b/gas/testsuite/gas/riscv/priv-reg-all.s
> new file mode 100644
> index 0000000..4dc6716
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-all.s
> @@ -0,0 +1,295 @@
> +# From priv spec 1.9.1 to 1.12 registers.
> +
> + .macro csr val
> + csrr a0,\val
> + .endm
> +
> +# User-Level CSR Addresses in 1.12.
> + csr ustatus
> + csr uie
> + csr utvec
> +
> + csr uscratch
> + csr uepc
> + csr ucause
> + csr utval
> + csr uip
> +
> + csr fflags
> + csr frm
> + csr fcsr
> +
> + csr cycle
> + csr time
> + csr instret
> + csr hpmcounter3
> + csr hpmcounter4
> + csr hpmcounter5
> + csr hpmcounter6
> + csr hpmcounter7
> + csr hpmcounter8
> + csr hpmcounter9
> + csr hpmcounter10
> + csr hpmcounter11
> + csr hpmcounter12
> + csr hpmcounter13
> + csr hpmcounter14
> + csr hpmcounter15
> + csr hpmcounter16
> + csr hpmcounter17
> + csr hpmcounter18
> + csr hpmcounter19
> + csr hpmcounter20
> + csr hpmcounter21
> + csr hpmcounter22
> + csr hpmcounter23
> + csr hpmcounter24
> + csr hpmcounter25
> + csr hpmcounter26
> + csr hpmcounter27
> + csr hpmcounter28
> + csr hpmcounter29
> + csr hpmcounter30
> + csr hpmcounter31
> + csr cycleh
> + csr timeh
> + csr instreth
> + csr hpmcounter3h
> + csr hpmcounter4h
> + csr hpmcounter5h
> + csr hpmcounter6h
> + csr hpmcounter7h
> + csr hpmcounter8h
> + csr hpmcounter9h
> + csr hpmcounter10h
> + csr hpmcounter11h
> + csr hpmcounter12h
> + csr hpmcounter13h
> + csr hpmcounter14h
> + csr hpmcounter15h
> + csr hpmcounter16h
> + csr hpmcounter17h
> + csr hpmcounter18h
> + csr hpmcounter19h
> + csr hpmcounter20h
> + csr hpmcounter21h
> + csr hpmcounter22h
> + csr hpmcounter23h
> + csr hpmcounter24h
> + csr hpmcounter25h
> + csr hpmcounter26h
> + csr hpmcounter27h
> + csr hpmcounter28h
> + csr hpmcounter29h
> + csr hpmcounter30h
> + csr hpmcounter31h
> +
> +# Supervisor-level CSR Addresses in 1.12.
> + csr sstatus
> + csr sedeleg
> + csr sideleg
> + csr sie
> + csr stvec
> + csr scounteren
> +
> + csr sscratch
> + csr sepc
> + csr scause
> + csr stval
> + csr sip
> +
> + csr satp
> +
> +# Hypervisor-Level CSR Addresses in 1.12.
> + csr hstatus
> + csr hedeleg
> + csr hideleg
> + csr hcounteren
> +
> + csr hgatp
> +
> + csr htimedelta
> + csr htimedeltah
> +
> + csr vsstatus
> + csr vsie
> + csr vstvec
> + csr vsscratch
> + csr vsepc
> + csr vscause
> + csr vstval
> + csr vsip
> + csr vsatp
> +
> +# Machine-Level CSR Addresses in 1.12.
> + csr mvendorid
> + csr marchid
> + csr mimpid
> + csr mhartid
> +
> + csr mstatus
> + csr misa
> + csr medeleg
> + csr mideleg
> + csr mie
> + csr mtvec
> + csr mcounteren
> + csr mstatush
> +
> + csr mscratch
> + csr mepc
> + csr mcause
> + csr mtval
> + csr mip
> +
> + csr pmpcfg0
> + csr pmpcfg1
> + csr pmpcfg2
> + csr pmpcfg3
> + csr pmpaddr0
> + csr pmpaddr1
> + csr pmpaddr2
> + csr pmpaddr3
> + csr pmpaddr4
> + csr pmpaddr5
> + csr pmpaddr6
> + csr pmpaddr7
> + csr pmpaddr8
> + csr pmpaddr9
> + csr pmpaddr10
> + csr pmpaddr11
> + csr pmpaddr12
> + csr pmpaddr13
> + csr pmpaddr14
> + csr pmpaddr15
> +
> + csr mcycle
> + csr minstret
> + csr mhpmcounter3
> + csr mhpmcounter4
> + csr mhpmcounter5
> + csr mhpmcounter6
> + csr mhpmcounter7
> + csr mhpmcounter8
> + csr mhpmcounter9
> + csr mhpmcounter10
> + csr mhpmcounter11
> + csr mhpmcounter12
> + csr mhpmcounter13
> + csr mhpmcounter14
> + csr mhpmcounter15
> + csr mhpmcounter16
> + csr mhpmcounter17
> + csr mhpmcounter18
> + csr mhpmcounter19
> + csr mhpmcounter20
> + csr mhpmcounter21
> + csr mhpmcounter22
> + csr mhpmcounter23
> + csr mhpmcounter24
> + csr mhpmcounter25
> + csr mhpmcounter26
> + csr mhpmcounter27
> + csr mhpmcounter28
> + csr mhpmcounter29
> + csr mhpmcounter30
> + csr mhpmcounter31
> + csr mcycleh
> + csr minstreth
> + csr mhpmcounter3h
> + csr mhpmcounter4h
> + csr mhpmcounter5h
> + csr mhpmcounter6h
> + csr mhpmcounter7h
> + csr mhpmcounter8h
> + csr mhpmcounter9h
> + csr mhpmcounter10h
> + csr mhpmcounter11h
> + csr mhpmcounter12h
> + csr mhpmcounter13h
> + csr mhpmcounter14h
> + csr mhpmcounter15h
> + csr mhpmcounter16h
> + csr mhpmcounter17h
> + csr mhpmcounter18h
> + csr mhpmcounter19h
> + csr mhpmcounter20h
> + csr mhpmcounter21h
> + csr mhpmcounter22h
> + csr mhpmcounter23h
> + csr mhpmcounter24h
> + csr mhpmcounter25h
> + csr mhpmcounter26h
> + csr mhpmcounter27h
> + csr mhpmcounter28h
> + csr mhpmcounter29h
> + csr mhpmcounter30h
> + csr mhpmcounter31h
> +
> + csr mcountinhibit
> + csr mhpmevent3
> + csr mhpmevent4
> + csr mhpmevent5
> + csr mhpmevent6
> + csr mhpmevent7
> + csr mhpmevent8
> + csr mhpmevent9
> + csr mhpmevent10
> + csr mhpmevent11
> + csr mhpmevent12
> + csr mhpmevent13
> + csr mhpmevent14
> + csr mhpmevent15
> + csr mhpmevent16
> + csr mhpmevent17
> + csr mhpmevent18
> + csr mhpmevent19
> + csr mhpmevent20
> + csr mhpmevent21
> + csr mhpmevent22
> + csr mhpmevent23
> + csr mhpmevent24
> + csr mhpmevent25
> + csr mhpmevent26
> + csr mhpmevent27
> + csr mhpmevent28
> + csr mhpmevent29
> + csr mhpmevent30
> + csr mhpmevent31
> +
> + csr tselect
> + csr tdata1
> + csr tdata2
> + csr tdata3
> +
> + csr dcsr
> + csr dpc
> + csr dscratch0
> + csr dscratch1
> +
> +# Defined in 1.9.1, but alias for another CSR in 1.12.
> + csr ubadaddr # utval
> + csr sbadaddr # stval
> + csr sptbr # satp
> + csr hie # vsie
> + csr htvec # vstvec
> + csr hscratch # vsscratch
> + csr hepc # vsepc
> + csr hcause # vscause
> + csr hbadaddr # vstval
> + csr hip # vsip
> + csr mbadaddr # mtval
> + csr mucounteren # mcountinhibit
> +
> +# Defined in 1.9.1, but dropped in 1.10.
> + csr mscounteren
> + csr mhcounteren
> + csr mbase
> + csr mbound
> + csr mibase
> + csr mibound
> + csr mdbase
> + csr mdbound
> +
> +# Defined in 1.10, but dropped in 1.12.
> + csr dscratch # dscratch0
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> new file mode 100644
> index 0000000..9bb3f82
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> @@ -0,0 +1,3 @@
> +#as:
> +#source: priv-reg-fail-nonexistent.s
> +#error_output: priv-reg-fail-nonexistent.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> new file mode 100644
> index 0000000..a0bb8a6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> new file mode 100644
> index 0000000..6e6d27e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> @@ -0,0 +1 @@
> + csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> deleted file mode 100644
> index d8ec868..0000000
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ /dev/null
> @@ -1,253 +0,0 @@
> -#as: -march=rv32i
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <.text>:
> -[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> -[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
> -[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> -[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> -[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> -[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> -[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
> -[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
> -[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
> -[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
> -[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
> -[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
> -[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
> -[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> -[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> -[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> -[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> -[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> -[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> -[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> -[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> -[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> -[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> -[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> -[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> -[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> -[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> -[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> -[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> -[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> -[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> -[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> -[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> -[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> -[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> -[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> -[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> -[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> -[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> -[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> -[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> -[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> -[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> -[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> -[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> -[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> -[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> -[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> -[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> -[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> -[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> -[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> -[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> -[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> -[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> -[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> -[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> -[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> -[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> -[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> -[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> -[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> -[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> -[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> -[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> -[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> -[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> -[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> -[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> -[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> -[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> -[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> -[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> -[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> -[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> -[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> -[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> -[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
> -[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> -[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> -[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> -[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
> -[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
> -[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> -[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> -[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> -[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
> -[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> -[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> -[ ]+170:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> -[ ]+174:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> -[ ]+178:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> -[ ]+17c:[ ]+24402573[ ]+csrr[ ]+a0,hip
> -[ ]+180:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> -[ ]+184:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> -[ ]+188:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> -[ ]+18c:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> -[ ]+190:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> -[ ]+194:[ ]+30102573[ ]+csrr[ ]+a0,misa
> -[ ]+198:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> -[ ]+19c:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> -[ ]+1a0:[ ]+30402573[ ]+csrr[ ]+a0,mie
> -[ ]+1a4:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> -[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> -[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> -[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> -[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
> -[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> -[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> -[ ]+1c4:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> -[ ]+1c8:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> -[ ]+1cc:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> -[ ]+1d0:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> -[ ]+1d4:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> -[ ]+1d8:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> -[ ]+1dc:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> -[ ]+1e0:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> -[ ]+1e4:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> -[ ]+1e8:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> -[ ]+1ec:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> -[ ]+1f0:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> -[ ]+1f4:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> -[ ]+1f8:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> -[ ]+1fc:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> -[ ]+200:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> -[ ]+204:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> -[ ]+208:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> -[ ]+20c:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> -[ ]+210:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> -[ ]+214:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> -[ ]+218:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> -[ ]+21c:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> -[ ]+220:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> -[ ]+224:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> -[ ]+228:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> -[ ]+22c:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> -[ ]+230:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> -[ ]+234:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> -[ ]+238:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> -[ ]+23c:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> -[ ]+240:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> -[ ]+244:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> -[ ]+248:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> -[ ]+24c:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> -[ ]+250:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> -[ ]+254:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> -[ ]+258:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> -[ ]+25c:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> -[ ]+260:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> -[ ]+264:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> -[ ]+268:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> -[ ]+26c:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> -[ ]+270:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> -[ ]+274:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> -[ ]+278:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> -[ ]+27c:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> -[ ]+280:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> -[ ]+284:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> -[ ]+288:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> -[ ]+28c:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> -[ ]+290:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> -[ ]+294:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> -[ ]+298:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> -[ ]+29c:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> -[ ]+2a0:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> -[ ]+2a4:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> -[ ]+2a8:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> -[ ]+2ac:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> -[ ]+2b0:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> -[ ]+2b4:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> -[ ]+2b8:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> -[ ]+2bc:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> -[ ]+2c0:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> -[ ]+2c4:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> -[ ]+2c8:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> -[ ]+2cc:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
> -[ ]+2d0:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> -[ ]+2d4:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> -[ ]+2d8:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> -[ ]+2dc:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> -[ ]+2e0:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> -[ ]+2e4:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> -[ ]+2e8:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> -[ ]+2ec:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> -[ ]+2f0:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> -[ ]+2f4:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> -[ ]+2f8:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> -[ ]+2fc:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> -[ ]+300:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> -[ ]+304:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> -[ ]+308:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> -[ ]+30c:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> -[ ]+310:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> -[ ]+314:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> -[ ]+318:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> -[ ]+31c:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> -[ ]+320:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> -[ ]+324:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> -[ ]+328:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> -[ ]+32c:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> -[ ]+330:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> -[ ]+334:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> -[ ]+338:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> -[ ]+33c:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> -[ ]+340:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> -[ ]+344:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> -[ ]+348:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> -[ ]+34c:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> -[ ]+350:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> -[ ]+354:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> -[ ]+358:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> -[ ]+35c:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> -[ ]+360:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> -[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
> -[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> -[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> -[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> -[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> -[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> -[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> -[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> -[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> -[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> -[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> -[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> -[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> -[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> -[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> -[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> -[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> -[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> -[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> -[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> -[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> -[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> -[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> -[ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> deleted file mode 100644
> index 72d97f9..0000000
> --- a/gas/testsuite/gas/riscv/priv-reg.s
> +++ /dev/null
> @@ -1,269 +0,0 @@
> - .macro csr val
> - csrr a0,\val
> - .endm
> -# 1.9.1 registers
> - csr ustatus
> - csr uie
> - csr utvec
> -
> - csr uscratch
> - csr uepc
> - csr ucause
> - csr ubadaddr
> - csr uip
> -
> - csr fflags
> - csr frm
> - csr fcsr
> -
> - csr cycle
> - csr time
> - csr instret
> - csr hpmcounter3
> - csr hpmcounter4
> - csr hpmcounter5
> - csr hpmcounter6
> - csr hpmcounter7
> - csr hpmcounter8
> - csr hpmcounter9
> - csr hpmcounter10
> - csr hpmcounter11
> - csr hpmcounter12
> - csr hpmcounter13
> - csr hpmcounter14
> - csr hpmcounter15
> - csr hpmcounter16
> - csr hpmcounter17
> - csr hpmcounter18
> - csr hpmcounter19
> - csr hpmcounter20
> - csr hpmcounter21
> - csr hpmcounter22
> - csr hpmcounter23
> - csr hpmcounter24
> - csr hpmcounter25
> - csr hpmcounter26
> - csr hpmcounter27
> - csr hpmcounter28
> - csr hpmcounter29
> - csr hpmcounter30
> - csr hpmcounter31
> - csr cycleh
> - csr timeh
> - csr instreth
> - csr hpmcounter3h
> - csr hpmcounter4h
> - csr hpmcounter5h
> - csr hpmcounter6h
> - csr hpmcounter7h
> - csr hpmcounter8h
> - csr hpmcounter9h
> - csr hpmcounter10h
> - csr hpmcounter11h
> - csr hpmcounter12h
> - csr hpmcounter13h
> - csr hpmcounter14h
> - csr hpmcounter15h
> - csr hpmcounter16h
> - csr hpmcounter17h
> - csr hpmcounter18h
> - csr hpmcounter19h
> - csr hpmcounter20h
> - csr hpmcounter21h
> - csr hpmcounter22h
> - csr hpmcounter23h
> - csr hpmcounter24h
> - csr hpmcounter25h
> - csr hpmcounter26h
> - csr hpmcounter27h
> - csr hpmcounter28h
> - csr hpmcounter29h
> - csr hpmcounter30h
> - csr hpmcounter31h
> -
> - csr sstatus
> - csr sedeleg
> - csr sideleg
> - csr sie
> - csr stvec
> -
> - csr sscratch
> - csr sepc
> - csr scause
> - csr sbadaddr
> - csr sip
> -
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> -
> - csr mvendorid
> - csr marchid
> - csr mimpid
> - csr mhartid
> -
> - csr mstatus
> - csr misa
> - csr medeleg
> - csr mideleg
> - csr mie
> - csr mtvec
> -
> - csr mscratch
> - csr mepc
> - csr mcause
> - csr mbadaddr
> - csr mip
> -
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> -
> - csr mcycle
> - csr minstret
> - csr mhpmcounter3
> - csr mhpmcounter4
> - csr mhpmcounter5
> - csr mhpmcounter6
> - csr mhpmcounter7
> - csr mhpmcounter8
> - csr mhpmcounter9
> - csr mhpmcounter10
> - csr mhpmcounter11
> - csr mhpmcounter12
> - csr mhpmcounter13
> - csr mhpmcounter14
> - csr mhpmcounter15
> - csr mhpmcounter16
> - csr mhpmcounter17
> - csr mhpmcounter18
> - csr mhpmcounter19
> - csr mhpmcounter20
> - csr mhpmcounter21
> - csr mhpmcounter22
> - csr mhpmcounter23
> - csr mhpmcounter24
> - csr mhpmcounter25
> - csr mhpmcounter26
> - csr mhpmcounter27
> - csr mhpmcounter28
> - csr mhpmcounter29
> - csr mhpmcounter30
> - csr mhpmcounter31
> - csr mcycleh
> - csr minstreth
> - csr mhpmcounter3h
> - csr mhpmcounter4h
> - csr mhpmcounter5h
> - csr mhpmcounter6h
> - csr mhpmcounter7h
> - csr mhpmcounter8h
> - csr mhpmcounter9h
> - csr mhpmcounter10h
> - csr mhpmcounter11h
> - csr mhpmcounter12h
> - csr mhpmcounter13h
> - csr mhpmcounter14h
> - csr mhpmcounter15h
> - csr mhpmcounter16h
> - csr mhpmcounter17h
> - csr mhpmcounter18h
> - csr mhpmcounter19h
> - csr mhpmcounter20h
> - csr mhpmcounter21h
> - csr mhpmcounter22h
> - csr mhpmcounter23h
> - csr mhpmcounter24h
> - csr mhpmcounter25h
> - csr mhpmcounter26h
> - csr mhpmcounter27h
> - csr mhpmcounter28h
> - csr mhpmcounter29h
> - csr mhpmcounter30h
> - csr mhpmcounter31h
> -
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> - csr mhpmevent3
> - csr mhpmevent4
> - csr mhpmevent5
> - csr mhpmevent6
> - csr mhpmevent7
> - csr mhpmevent8
> - csr mhpmevent9
> - csr mhpmevent10
> - csr mhpmevent11
> - csr mhpmevent12
> - csr mhpmevent13
> - csr mhpmevent14
> - csr mhpmevent15
> - csr mhpmevent16
> - csr mhpmevent17
> - csr mhpmevent18
> - csr mhpmevent19
> - csr mhpmevent20
> - csr mhpmevent21
> - csr mhpmevent22
> - csr mhpmevent23
> - csr mhpmevent24
> - csr mhpmevent25
> - csr mhpmevent26
> - csr mhpmevent27
> - csr mhpmevent28
> - csr mhpmevent29
> - csr mhpmevent30
> - csr mhpmevent31
> -
> - csr tselect
> - csr tdata1
> - csr tdata2
> - csr tdata3
> -
> - csr dcsr
> - csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> -
> - csr mcounteren
> - csr mtval
> -
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
> deleted file mode 100644
> index 823601c..0000000
> --- a/gas/testsuite/gas/riscv/satp.d
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -#as:
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> -[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
> deleted file mode 100644
> index f8aa766..0000000
> --- a/gas/testsuite/gas/riscv/satp.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - csrr t0, satp
> - csrr t0, sptbr
> diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
> index da1bf19..a9ea54d 100644
> --- a/gdb/features/riscv/32bit-csr.xml
> +++ b/gdb/features/riscv/32bit-csr.xml
> @@ -227,24 +227,32 @@
> <reg name="tdata3" bitsize="32"/>
> <reg name="dcsr" bitsize="32"/>
> <reg name="dpc" bitsize="32"/>
> - <reg name="dscratch" bitsize="32"/>
> <reg name="hstatus" bitsize="32"/>
> <reg name="hedeleg" bitsize="32"/>
> <reg name="hideleg" bitsize="32"/>
> - <reg name="hie" bitsize="32"/>
> - <reg name="htvec" bitsize="32"/>
> - <reg name="hscratch" bitsize="32"/>
> - <reg name="hepc" bitsize="32"/>
> - <reg name="hcause" bitsize="32"/>
> - <reg name="hbadaddr" bitsize="32"/>
> - <reg name="hip" bitsize="32"/>
> + <reg name="hcounteren" bitsize="32"/>
> + <reg name="hgatp" bitsize="32"/>
> + <reg name="htimedelta" bitsize="32"/>
> + <reg name="htimedeltah" bitsize="32"/>
> + <reg name="vsstatus" bitsize="32"/>
> + <reg name="vsie" bitsize="32"/>
> + <reg name="vstvec" bitsize="32"/>
> + <reg name="vsscratch" bitsize="32"/>
> + <reg name="vsepc" bitsize="32"/>
> + <reg name="vscause" bitsize="32"/>
> + <reg name="vstval" bitsize="32"/>
> + <reg name="vsip" bitsize="32"/>
> + <reg name="vsatp" bitsize="32"/>
> + <reg name="mstatush" bitsize="32"/>
> + <reg name="mcountinhibit" bitsize="32"/>
> + <reg name="dscratch0" bitsize="32"/>
> + <reg name="dscratch1" bitsize="32"/>
> <reg name="mbase" bitsize="32"/>
> <reg name="mbound" bitsize="32"/>
> <reg name="mibase" bitsize="32"/>
> <reg name="mibound" bitsize="32"/>
> <reg name="mdbase" bitsize="32"/>
> <reg name="mdbound" bitsize="32"/>
> - <reg name="mucounteren" bitsize="32"/>
> <reg name="mscounteren" bitsize="32"/>
> <reg name="mhcounteren" bitsize="32"/>
> </feature>
> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> index 6aa4bed..b32b413 100644
> --- a/gdb/features/riscv/64bit-csr.xml
> +++ b/gdb/features/riscv/64bit-csr.xml
> @@ -227,24 +227,32 @@
> <reg name="tdata3" bitsize="64"/>
> <reg name="dcsr" bitsize="64"/>
> <reg name="dpc" bitsize="64"/>
> - <reg name="dscratch" bitsize="64"/>
> <reg name="hstatus" bitsize="64"/>
> <reg name="hedeleg" bitsize="64"/>
> <reg name="hideleg" bitsize="64"/>
> - <reg name="hie" bitsize="64"/>
> - <reg name="htvec" bitsize="64"/>
> - <reg name="hscratch" bitsize="64"/>
> - <reg name="hepc" bitsize="64"/>
> - <reg name="hcause" bitsize="64"/>
> - <reg name="hbadaddr" bitsize="64"/>
> - <reg name="hip" bitsize="64"/>
> + <reg name="hcounteren" bitsize="64"/>
> + <reg name="hgatp" bitsize="64"/>
> + <reg name="htimedelta" bitsize="64"/>
> + <reg name="htimedeltah" bitsize="64"/>
> + <reg name="vsstatus" bitsize="64"/>
> + <reg name="vsie" bitsize="64"/>
> + <reg name="vstvec" bitsize="64"/>
> + <reg name="vsscratch" bitsize="64"/>
> + <reg name="vsepc" bitsize="64"/>
> + <reg name="vscause" bitsize="64"/>
> + <reg name="vstval" bitsize="64"/>
> + <reg name="vsip" bitsize="64"/>
> + <reg name="vsatp" bitsize="64"/>
> + <reg name="mstatush" bitsize="64"/>
> + <reg name="mcountinhibit" bitsize="64"/>
> + <reg name="dscratch0" bitsize="64"/>
> + <reg name="dscratch1" bitsize="64"/>
> <reg name="mbase" bitsize="64"/>
> <reg name="mbound" bitsize="64"/>
> <reg name="mibase" bitsize="64"/>
> <reg name="mibound" bitsize="64"/>
> <reg name="mdbase" bitsize="64"/>
> <reg name="mdbound" bitsize="64"/>
> - <reg name="mucounteren" bitsize="64"/>
> <reg name="mscounteren" bitsize="64"/>
> <reg name="mhcounteren" bitsize="64"/>
> </feature>
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index f09200c..ee3d976 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -795,18 +795,31 @@
> #define CSR_TDATA3 0x7a3
> #define CSR_DCSR 0x7b0
> #define CSR_DPC 0x7b1
> -#define CSR_DSCRATCH 0x7b2
> +/* These registers are present in priv spec 1.12. */
> +#define CSR_HSTATUS 0x600
> +#define CSR_HEDELEG 0x602
> +#define CSR_HIDELEG 0x603
> +#define CSR_HCOUNTEREN 0x606
> +#define CSR_HGATP 0x680
> +#define CSR_HTIMEDELTA 0x605
> +#define CSR_HTIMEDELTAH 0x615
> +#define CSR_VSSTATUS 0x200
> +#define CSR_VSIE 0x204
> +#define CSR_VSTVEC 0x205
> +#define CSR_VSSCRATCH 0x240
> +#define CSR_VSEPC 0x241
> +#define CSR_VSCAUSE 0x242
> +#define CSR_VSTVAL 0x243
> +#define CSR_VSIP 0x244
> +#define CSR_VSATP 0x280
> +#define CSR_MSTATUSH 0x310
> +#define CSR_MCOUNTINHIBIT 0x320
> +#define CSR_DSCRATCH0 0x7b2
> +#define CSR_DSCRATCH1 0x7b3
> /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> -#define CSR_HSTATUS 0x200
> -#define CSR_HEDELEG 0x202
> -#define CSR_HIDELEG 0x203
> -#define CSR_HIE 0x204
> -#define CSR_HTVEC 0x205
> -#define CSR_HSCRATCH 0x240
> -#define CSR_HEPC 0x241
> -#define CSR_HCAUSE 0x242
> -#define CSR_HBADADDR 0x243
> -#define CSR_HIP 0x244
> +/* CSR_HSTATUS is 0x200 in 1.9.1, dropped in 1.10, but 0x600 in 1.12. */
> +/* CSR_HEDELEG is 0x202 in 1.9.1, dropped in 1.10, but 0x602 in 1.12. */
> +/* CSR_HIDELEG is 0x203 in 1.9.1, dropped in 1.10, but 0x603 in 1.12. */
> /* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> @@ -814,7 +827,6 @@
> #define CSR_MIBOUND 0x383
> #define CSR_MDBASE 0x384
> #define CSR_MDBOUND 0x385
> -#define CSR_MUCOUNTEREN 0x320
> #define CSR_MSCOUNTEREN 0x321
> #define CSR_MHCOUNTEREN 0x322
> #define CAUSE_MISALIGNED_FETCH 0x0
> @@ -1336,25 +1348,34 @@ DECLARE_CSR(tdata2, CSR_TDATA2)
> DECLARE_CSR(tdata3, CSR_TDATA3)
> DECLARE_CSR(dcsr, CSR_DCSR)
> DECLARE_CSR(dpc, CSR_DPC)
> -DECLARE_CSR(dscratch, CSR_DSCRATCH)
> -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> +/* These registers are present in priv spec 1.12. */
> DECLARE_CSR(hstatus, CSR_HSTATUS)
> DECLARE_CSR(hedeleg, CSR_HEDELEG)
> DECLARE_CSR(hideleg, CSR_HIDELEG)
> -DECLARE_CSR(hie, CSR_HIE)
> -DECLARE_CSR(htvec, CSR_HTVEC)
> -DECLARE_CSR(hscratch, CSR_HSCRATCH)
> -DECLARE_CSR(hepc, CSR_HEPC)
> -DECLARE_CSR(hcause, CSR_HCAUSE)
> -DECLARE_CSR(hbadaddr, CSR_HBADADDR)
> -DECLARE_CSR(hip, CSR_HIP)
> +DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
> +DECLARE_CSR(hgatp, CSR_HGATP)
> +DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
> +DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
> +DECLARE_CSR(vsstatus, CSR_VSSTATUS)
> +DECLARE_CSR(vsie, CSR_VSIE)
> +DECLARE_CSR(vstvec, CSR_VSTVEC)
> +DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
> +DECLARE_CSR(vsepc, CSR_VSEPC)
> +DECLARE_CSR(vscause, CSR_VSCAUSE)
> +DECLARE_CSR(vstval, CSR_VSTVAL)
> +DECLARE_CSR(vsip, CSR_VSIP)
> +DECLARE_CSR(vsatp, CSR_VSATP)
> +DECLARE_CSR(mstatush, CSR_MSTATUSH)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
> +/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> DECLARE_CSR(mbase, CSR_MBASE)
> DECLARE_CSR(mbound, CSR_MBOUND)
> DECLARE_CSR(mibase, CSR_MIBASE)
> DECLARE_CSR(mibound, CSR_MIBOUND)
> DECLARE_CSR(mdbase, CSR_MDBASE)
> DECLARE_CSR(mdbound, CSR_MDBOUND)
> -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
> DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
> DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
> #endif
> @@ -1367,6 +1388,24 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL)
> DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
> /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
> +/* Hie is 0x204 in 1.9.1, but 0x204 is vsie in 1.12. */
> +DECLARE_CSR_ALIAS(hie, CSR_VSIE)
> +/* Htvec is 0x205 in 1.9.1, but 0x205 is vstvec in 1.12. */
> +DECLARE_CSR_ALIAS(htvec, CSR_VSTVEC)
> +/* Hscratch is 0x240 in 1.9.1, but 0x240 is vsscratch in 1.12. */
> +DECLARE_CSR_ALIAS(hscratch, CSR_VSSCRATCH)
> +/* Hepc is 0x241 in 1.9.1, but 0x241 is vsepc in 1.12. */
> +DECLARE_CSR_ALIAS(hepc, CSR_VSEPC)
> +/* Hcause is 0x242 in 1.9.1, but 0x242 is vscause in 1.12. */
> +DECLARE_CSR_ALIAS(hcause, CSR_VSCAUSE)
> +/* Hbadaddr is 0x243 in 1.9.1, but 0x243 is vstval in 1.12. */
> +DECLARE_CSR_ALIAS(hbadaddr, CSR_VSTVAL)
> +/* Hip is 0x244 in 1.9.1, but 0x244 is vsip in 1.12. */
> +DECLARE_CSR_ALIAS(hip, CSR_VSIP)
> +/* Mucounteren is 0x320 in 1.9.1, but 0x320 is mcountinhibit in 1.12. */
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT)
> +/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.12. */
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PING] [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
2019-12-16 5:21 ` [PATCH v3 4/4] RISC-V: Disable the CSR checking by default Nelson Chu
@ 2020-01-03 1:32 ` Nelson Chu
2020-02-01 3:08 ` Jim Wilson
1 sibling, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-01-03 1:32 UTC (permalink / raw)
To: Binutils; +Cc: Palmer Dabbelt, Jim Wilson, Andrew Waterman, Kito Cheng
PING :)
On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> Add new .option `csrcheck/nocsrcheck` and GAS option `-mcsrcheck/-mno-csrcheck`
> to enbale/disable the CSR checking. Disable the CSR checking by default.
>
> gas/
> * config/tc-riscv.c: Add new .option and GAS options to enbale/disable
> the CSR checking. We disable the CSR checking by default.
> (riscv_ip, reg_lookup_internal): Check the `riscv_opts.csrcheck`
> before we doing the CSR checking.
> * doc/c-riscv.texi: Add description for the new .option and assembler
> options.
> * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsrcheck` to enable
> the CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
> ---
> gas/config/tc-riscv.c | 23 +++++++++++++++++++++-
> gas/doc/c-riscv.texi | 13 ++++++++++++
> gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-01.d | 2 +-
> .../gas/riscv/priv-reg-fail-read-only-02.d | 2 +-
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 2 +-
> 6 files changed, 39 insertions(+), 5 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 592864b..9c6cde0 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -83,6 +83,7 @@ struct riscv_set_options
> int rve; /* Generate RVE code. */
> int relax; /* Emit relocs the linker is allowed to relax. */
> int arch_attr; /* Emit arch attribute. */
> + int csrcheck; /* Enable the CSR checking. */
> };
>
> static struct riscv_set_options riscv_opts =
> @@ -92,6 +93,7 @@ static struct riscv_set_options riscv_opts =
> 0, /* rve */
> 1, /* relax */
> DEFAULT_RISCV_ATTR, /* arch_attr */
> + 0. /* csrcheck */
> };
>
> static void
> @@ -566,7 +568,9 @@ reg_lookup_internal (const char *s, enum reg_class class)
> if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15)
> return -1;
>
> - if (class == RCLASS_CSR && !reg_csr_lookup_internal (s))
> + if (class == RCLASS_CSR
> + && riscv_opts.csrcheck
> + && !reg_csr_lookup_internal (s))
> return -1;
>
> return DECODE_REG_NUM (r);
> @@ -1590,6 +1594,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> /* Check if we write a read-only CSR by the CSR
> instruction. */
> if (insn_with_csr
> + && riscv_opts.csrcheck
> && !riscv_csr_read_only_check (ip->insn_opcode))
> {
> /* Don't parse the next insn in the riscv_opcode.
> @@ -2328,6 +2333,8 @@ enum options
> OPTION_NO_RELAX,
> OPTION_ARCH_ATTR,
> OPTION_NO_ARCH_ATTR,
> + OPTION_CSR_CHECK,
> + OPTION_NO_CSR_CHECK,
> OPTION_END_OF_ENUM
> };
>
> @@ -2342,6 +2349,8 @@ struct option md_longopts[] =
> {"mno-relax", no_argument, NULL, OPTION_NO_RELAX},
> {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR},
> {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR},
> + {"mcsrcheck", no_argument, NULL, OPTION_CSR_CHECK},
> + {"mno-csrcheck", no_argument, NULL, OPTION_NO_CSR_CHECK},
>
> {NULL, no_argument, NULL, 0}
> };
> @@ -2420,6 +2429,14 @@ md_parse_option (int c, const char *arg)
> riscv_opts.arch_attr = FALSE;
> break;
>
> + case OPTION_CSR_CHECK:
> + riscv_opts.csrcheck = TRUE;
> + break;
> +
> + case OPTION_NO_CSR_CHECK:
> + riscv_opts.csrcheck = FALSE;
> + break;
> +
> default:
> return 0;
> }
> @@ -2812,6 +2829,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
> riscv_opts.relax = TRUE;
> else if (strcmp (name, "norelax") == 0)
> riscv_opts.relax = FALSE;
> + else if (strcmp (name, "csrcheck") == 0)
> + riscv_opts.csrcheck = TRUE;
> + else if (strcmp (name, "nocsrcheck") == 0)
> + riscv_opts.csrcheck = FALSE;
> else if (strcmp (name, "push") == 0)
> {
> struct riscv_option_stack *s;
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 9bc8c82..644e332 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -59,6 +59,15 @@ required to materialize symbol addresses. (default)
> @item -mno-relax
> Don't do linker relaxations.
>
> +@cindex @samp{-mcsrcheck} option, RISC-V
> +@item -mcsrcheck
> +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
> +The ISA-dependent CSR are only valid when the specific ISA is set. The
> +read-only CSR can not be written by the CSR instructions.
> +
> +@cindex @samp{-mno-csrcheck} option, RISC-V
> +@item -mno-csrcheck
> +Don't do CSR cheching.
> @end table
> @c man end
>
> @@ -160,6 +169,10 @@ opportunistically relax some code sequences, but sometimes this behavior is not
> desirable.
> @end table
>
> +@item csrcheck
> +@itemx nocsrcheck
> +Enables or disables the CSR checking.
> +
> @cindex INSN directives
> @item .insn @var{value}
> @itemx .insn @var{value}
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> index 4c27f47..2b9faeb 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32i
> +#as: -march=rv32i -mcsrcheck
> #source: priv-reg-all.s
> #error_output: priv-reg-fail-fext.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> index 9c93d8a..72ff57b 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32if
> +#as: -march=rv32if -mcsrcheck
> #source: priv-reg-fail-read-only-01.s
> #error_output: priv-reg-fail-read-only-01.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> index ede45c5..22ad2da 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv32if
> +#as: -march=rv32if -mcsrcheck
> #source: priv-reg-fail-read-only-02.s
> #error_output: priv-reg-fail-read-only-02.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> index 88038bd..e45337f 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d
> @@ -1,3 +1,3 @@
> -#as: -march=rv64if
> +#as: -march=rv64if -mcsrcheck
> #source: priv-reg-all.s
> #error_output: priv-reg-fail-rv32-only.l
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
` (4 preceding siblings ...)
2020-01-03 1:29 ` [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
@ 2020-01-22 21:35 ` Palmer Dabbelt via binutils
2020-01-27 23:26 ` Jim Wilson
2020-01-30 18:39 ` Palmer Dabbelt via binutils
5 siblings, 2 replies; 25+ messages in thread
From: Palmer Dabbelt via binutils @ 2020-01-22 21:35 UTC (permalink / raw)
To: nelson.chu; +Cc: binutils, Jim Wilson, Andrew Waterman, kito.cheng
On Thu, 02 Jan 2020 17:29:33 PST (-0800), nelson.chu@sifive.com wrote:
> Kind reminder :)
> Any comments or suggestions?
>
> Thanks
> Best Regards
> Nelson
>
> On Mon, Dec 16, 2019 at 1:21 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>>
>> Dear Palmer,
>>
>> I'm on the master branch, but failed to notice that my internal build environment
>> add the --disable-gdb configure option to disable the GDB build. I'm really sorry
>> for this. After attaching the v3 patches, I can build riscv-gdb now. However,
>> the csr checking only work for the assembler so far. I extend the DECLARE_CSR
>> to record more informaton (`class`), but these information are unused in GDB.
>> Therefore, I just fix the GDB build failed by allowing more arguments for
>> DECLARE_CSR.
>>
>> Thanks and best regards
>> Nelson
>>
>>
>> Fix the build failed for GDB.
>>
>> * [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
>> Same as the previous one.
>>
>> * [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
>> Upadte the gdb/riscv-tdep.h and gdb/riscv-tdep.c since the DECLARE_CSR is changed.
>>
>> * [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
>> Same as the previous one.
>>
>> * [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
>> Same as the previous one.
>>
Sorry, I dropped these over the holidays. I'll push them once I get
binutils-gdb SSH access working on my new computer...
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
2020-01-22 21:35 ` Palmer Dabbelt via binutils
@ 2020-01-27 23:26 ` Jim Wilson
2020-01-30 18:39 ` Palmer Dabbelt via binutils
1 sibling, 0 replies; 25+ messages in thread
From: Jim Wilson @ 2020-01-27 23:26 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Nelson Chu, Binutils, Andrew Waterman, Kito Cheng
On Wed, Jan 22, 2020 at 1:35 PM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
> Sorry, I dropped these over the holidays. I'll push them once I get
> binutils-gdb SSH access working on my new computer...
Palmer, if you don't have time to do this, I can take care of it.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12.
2020-01-22 21:35 ` Palmer Dabbelt via binutils
2020-01-27 23:26 ` Jim Wilson
@ 2020-01-30 18:39 ` Palmer Dabbelt via binutils
1 sibling, 0 replies; 25+ messages in thread
From: Palmer Dabbelt via binutils @ 2020-01-30 18:39 UTC (permalink / raw)
To: Jim Wilson; +Cc: nelson.chu, binutils, Andrew Waterman, kito.cheng
On Mon, 27 Jan 2020 23:26:27 GMT (+0000), Jim Wilson wrote:
> On Wed, Jan 22, 2020 at 1:35 PM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>> Sorry, I dropped these over the holidays. I'll push them once I get
>> binutils-gdb SSH access working on my new computer...
>
> Palmer, if you don't have time to do this, I can take care of it.
That'd be great, thanks. I still don't have SSH set up and I'm in Europe for
FOSDEM until next week so I can't use my old laptop to add my Google key.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2019-12-16 5:21 ` [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12 Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
@ 2020-02-01 0:19 ` Jim Wilson
2020-02-01 0:24 ` Andrew Waterman
1 sibling, 1 reply; 25+ messages in thread
From: Jim Wilson @ 2020-02-01 0:19 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
On Sun, Dec 15, 2019 at 9:22 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> gas/
> * testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s Update
> the CSR to privilege spec 1.12.
> * testsuite/gas/riscv/priv-reg.d: Likewise.
> * testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
> * testsuite/gas/riscv/bad-csr.d: Likewise.
> * testsuite/gas/riscv/bad-csr.l: Likewise.
> * testsuite/gas/riscv/satp.s: Deleted. Duplicate of priv-reg-all.s
> * testsuite/gas/riscv/satp.d: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.s: Updated.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
>
> include/
> * opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.
>
> gdb/
> * features/riscv/32bit-csr.xml: Regenerated.
> * features/riscv/64bit-csr.xml: Regenerated.
Privilege spec 1.11 is ratified, and spec 1.12 is in draft form. Do
we want to implement a draft?
I see some hypervisor registers missing, e.g. hgeie and hgeip which
were added to the 1.12 draft on November 20. Hie was added Oct 29,
and is listed as dropped in your patch. It isn't clear to me which
version of the 1.12 draft you are using, but it seems to be an old
one. If we are implementing
1.12 draft we should probably implement the current one.
Overall it looks reasonable, but we need to be clear which spec we are
implementing, so we can verify that the patch matches the spec.
I see that the csr-dw-regnums.s test doesn't have any of the csr
aliases, but that seems OK. priv-reg-all.s is the important one and
does have all of them.
You are modifying gdb xml files. These need to be sent to gdb-patches
for approval instead of the binutils list, and I don't have gdb patch
approval permission. These are shared with qemu, and ideally should
be kept in sync. As a practical matter though, gdb doesn't use the
csr xml files as yet. And updating qemu means adding priv spec 1.12
draft support to qemu which is probably non-trivial, unless we can
ignore the as yet unsupported registers in the gdb stub which should
work. I believe WDC is working on the qemu hypervisor support, so it
might actually be tracking the 1.12 draft already. It is probably OK
to submit the gdb xml changes, and then file a bug somewhere asking
for gdb and qemu xml support to be synchronized.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2020-02-01 0:19 ` Jim Wilson
@ 2020-02-01 0:24 ` Andrew Waterman
2020-02-04 7:06 ` Nelson Chu
2020-02-10 18:12 ` Palmer Dabbelt via binutils
0 siblings, 2 replies; 25+ messages in thread
From: Andrew Waterman @ 2020-02-01 0:24 UTC (permalink / raw)
To: Jim Wilson; +Cc: Nelson Chu, Binutils
On Fri, Jan 31, 2020 at 4:19 PM Jim Wilson <jimw@sifive.com> wrote:
>
> On Sun, Dec 15, 2019 at 9:22 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> > gas/
> > * testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s Update
> > the CSR to privilege spec 1.12.
> > * testsuite/gas/riscv/priv-reg.d: Likewise.
> > * testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
> > * testsuite/gas/riscv/bad-csr.d: Likewise.
> > * testsuite/gas/riscv/bad-csr.l: Likewise.
> > * testsuite/gas/riscv/satp.s: Deleted. Duplicate of priv-reg-all.s
> > * testsuite/gas/riscv/satp.d: Likewise.
> > * testsuite/gas/riscv/csr-dw-regnums.s: Updated.
> > * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> >
> > include/
> > * opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.
> >
> > gdb/
> > * features/riscv/32bit-csr.xml: Regenerated.
> > * features/riscv/64bit-csr.xml: Regenerated.
>
> Privilege spec 1.11 is ratified, and spec 1.12 is in draft form. Do
> we want to implement a draft?
It seems inadvisable to incorporate draft standards into the FSF
binutils port. In particular, the hypervisor ISA is virtually certain
to change in backwards-incompatible ways prior to being frozen. It
seems to me that pushing this stuff upstream at this time will cause
more problems than it solves.
We could consider maintaining these patches on branches in the RISC-V
github repositories, and push them to the FSF tree at the appropriate
time. That way, we can support software development against these
draft standards while reducing the scope of backwards
incompatibilities.
>
>
> I see some hypervisor registers missing, e.g. hgeie and hgeip which
> were added to the 1.12 draft on November 20. Hie was added Oct 29,
> and is listed as dropped in your patch. It isn't clear to me which
> version of the 1.12 draft you are using, but it seems to be an old
> one. If we are implementing
> 1.12 draft we should probably implement the current one.
>
> Overall it looks reasonable, but we need to be clear which spec we are
> implementing, so we can verify that the patch matches the spec.
>
> I see that the csr-dw-regnums.s test doesn't have any of the csr
> aliases, but that seems OK. priv-reg-all.s is the important one and
> does have all of them.
>
> You are modifying gdb xml files. These need to be sent to gdb-patches
> for approval instead of the binutils list, and I don't have gdb patch
> approval permission. These are shared with qemu, and ideally should
> be kept in sync. As a practical matter though, gdb doesn't use the
> csr xml files as yet. And updating qemu means adding priv spec 1.12
> draft support to qemu which is probably non-trivial, unless we can
> ignore the as yet unsupported registers in the gdb stub which should
> work. I believe WDC is working on the qemu hypervisor support, so it
> might actually be tracking the 1.12 draft already. It is probably OK
> to submit the gdb xml changes, and then file a bug somewhere asking
> for gdb and qemu xml support to be synchronized.
>
> Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
2019-12-16 5:21 ` [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
@ 2020-02-01 1:27 ` Jim Wilson
2020-02-04 7:15 ` Nelson Chu
1 sibling, 1 reply; 25+ messages in thread
From: Jim Wilson @ 2020-02-01 1:27 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
On Sun, Dec 15, 2019 at 9:23 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> gas/
> * config/tc-riscv.c (enum riscv_csr_class): New enum. Used to decide
> whether or not this CSR is legal in the current ISA string.
> (riscv_csr_extra): New structure to hold all extra information of CSR.
> (riscv_init_csr_hash): New function. According to the DECLARE_CSR and
> DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash.
> Call hash_reg_name to insert CSR address into reg_names_hash.
> (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR.
> (reg_csr_lookup_internal, riscv_csr_class_check): New functions.
> Decide whether the CSR is valid according to the `csr_extra_hash`.
> * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source
> file is `priv-reg-all.s`, and the ISA is rv32i without f-ext, so the
> f-ext CSR are not allowed.
> * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The
> source file is `priv-reg-all.s`, and the ISA is rv64if, so the
> rv32-only CSR are not allowed.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
>
> include/
> * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to
> record riscv_csr_class.
>
> opcodes/
> * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is changed.
>
> gdb/
> * riscv-tdep.c: Updated since the DECLARE_CSR is changed.
> * riscv-tdep.h: Likewise.
> * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without
> rv32-only CSR.
> * features/riscv/64bit-csr.xml: Regernated.
>
> binutils/
> * dwarf.c: Updated since the DECLARE_CSR is changed.
Overall, this one looks OK to me.
But there are gdb changes that require gdb review and approval. It is
OK to send an email to both binutils and gdb-patches at the same time
when it needs approval from both. And unfortunately I'm not a gdb
reviewer but I can give a thumbs up on the gdb patches.
This conflicts with the first patch which isn't approved yet because
of questions about which version we are implementing, and whether we
are implementing a draft.
And there are more xml file changes, which ideally should be updated
in qemu too, but we can probably handle that as a separate issue.
I see some functions missing comments. This is a minor problem, but I
think the style guidelines still require an explanatory comment before
each function.
When I ran the testsuite for a riscv64-elf target, the csr-dw-regnums
test fails.
/home/jimw/FOSS/BINUTILS/binutils-gdb/gas/testsuite/gas/riscv/csr-dw-regnums.s:53:
Error: unknown register `cycleh'
followed by a lot of similar errors. This will need to use
-march=rv32if as is already done with priv-reg-all.d.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
@ 2020-02-01 2:38 ` Jim Wilson
2020-02-04 7:31 ` Nelson Chu
1 sibling, 1 reply; 25+ messages in thread
From: Jim Wilson @ 2020-02-01 2:38 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
On Sun, Dec 15, 2019 at 9:22 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> gas/
> * config/tc-riscv.c (insn_with_csr): New boolean to indicate we are
> assembling instruction with CSR.
> (enum csr_insn_type): New enum is used to classify the CSR instruction.
> (riscv_csr_insn_type, riscv_csr_read_only_check): New functions. These
> are used to check if we write a read-only CSR by the CSR instruction.
> (riscv_ip): Call riscv_csr_read_only_check after parsing all arguments.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: New testcase. Test
> all CSR for the read-only CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.s: New testcase. Test
> all CSR instructions for the read-only CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.l: Likewise.
This makes insn_with_csr a global variable. It looks like it should
be local to riscv_ip.
The testcases are using 1.12 draft csrs, which makes it dependent on
the first patch in the series.
> + error = _("Read-only CSR is used");
The error looks a little odd to me. Using implies that you are
reading it, which is OK for a read-only CSR. I would suggest "written
to" instead of "used". That makes the error more obvious.
Also, maybe this should be a warning instead of an error. This is a
valid instruction after all, it is just one that will always give a
run-time trap. But it is possible that people might be writing code
this way for a reason, for instance, maybe a hardware verification
testsuite to test whether the instruction does give a trap exactly as
it is supposed to.
There is a function without an explanatory comment before it which is
a minor issue.
Otherwise this looks OK.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
2019-12-16 5:21 ` [PATCH v3 4/4] RISC-V: Disable the CSR checking by default Nelson Chu
2020-01-03 1:32 ` [PING] " Nelson Chu
@ 2020-02-01 3:08 ` Jim Wilson
2020-02-04 7:48 ` Nelson Chu
1 sibling, 1 reply; 25+ messages in thread
From: Jim Wilson @ 2020-02-01 3:08 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
On Sun, Dec 15, 2019 at 9:22 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> gas/
> * config/tc-riscv.c: Add new .option and GAS options to enbale/disable
> the CSR checking. We disable the CSR checking by default.
> (riscv_ip, reg_lookup_internal): Check the `riscv_opts.csrcheck`
> before we doing the CSR checking.
> * doc/c-riscv.texi: Add description for the new .option and assembler
> options.
> * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsrcheck` to enable
> the CSR checking.
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
This patch makes the error message in the previous patch OK. I should
have looked ahead a bit. Though now I'm wondering if maybe csrcheck
can choose between an error and a warning. So we have a choice here
between error/no error or error/warning. There is a gas option
--fatal-warnings that will turn warnings into errors for people that
want that. And a --no-warn/-W option that turns warnings off, if
people don't want the warning.
I think -mcsrcheck is a little hard to parse, maybe -mcsr-check
instead? And similarly for the .option if we do that.
Otherwise this one looks OK, but depends on previous patches not approved yet.
Also, not directly related to this patch, but I noticed that we are
missing doc entries for the -march-attr/-mno-arch-attr command line
options added a year ago. That would be at least partly my fault for
not asking for that during the review. Maybe something you can add to
your to do list.
This fixes the csr-dw-regnums rv64 testsuite failure from the second
patch by accident, because you didn't turn on csrchecking for that
test. But it should still be fixed anyways, in case someone turns
this on by default in their copy of binutils.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2020-02-01 0:24 ` Andrew Waterman
@ 2020-02-04 7:06 ` Nelson Chu
2020-02-10 18:12 ` Palmer Dabbelt via binutils
1 sibling, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-02-04 7:06 UTC (permalink / raw)
To: Andrew Waterman; +Cc: Jim Wilson, Binutils
Hi Andrew and Jim,
Thanks for the feedback. Yes the serial patches are according to the
Oct 14 draft, so it is the old one. I agree with that keep the draft
standard into the RISC-V github repo is more appropriate. Therefore,
I will remove this patch in this term.
Thanks
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking.
2020-02-01 1:27 ` Jim Wilson
@ 2020-02-04 7:15 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-02-04 7:15 UTC (permalink / raw)
To: Jim Wilson; +Cc: Binutils
Hi Jim,
On Sat, Feb 1, 2020 at 9:26 AM Jim Wilson <jimw@sifive.com> wrote:
>
> Overall, this one looks OK to me.
Thank you very much :)
> But there are gdb changes that require gdb review and approval. It is
> OK to send an email to both binutils and gdb-patches at the same time
> when it needs approval from both. And unfortunately I'm not a gdb
> reviewer but I can give a thumbs up on the gdb patches.
OK, I will remove the first patch and then send the new series of
patches to both binutils and gdb.
> I see some functions missing comments. This is a minor problem, but I
> think the style guidelines still require an explanatory comment before
> each function.
No problem, I will fix this.
> When I ran the testsuite for a riscv64-elf target, the csr-dw-regnums
> test fails.
> /home/jimw/FOSS/BINUTILS/binutils-gdb/gas/testsuite/gas/riscv/csr-dw-regnums.s:53:
> Error: unknown register `cycleh'
> followed by a lot of similar errors. This will need to use
> -march=rv32if as is already done with priv-reg-all.d.
Oh I test the regressions after attaching the whole series of patches.
Thanks for your remind, I will fix this in the next version.
Thanks
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 3/4] RISC-V: Support the read-only CSR checking.
2020-02-01 2:38 ` Jim Wilson
@ 2020-02-04 7:31 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-02-04 7:31 UTC (permalink / raw)
To: Jim Wilson; +Cc: Binutils
On Sat, Feb 1, 2020 at 10:38 AM Jim Wilson <jimw@sifive.com> wrote:
>
> This makes insn_with_csr a global variable. It looks like it should
> be local to riscv_ip.
Yes it should be local with static to riscv_ip. I will fix it.
> The testcases are using 1.12 draft csrs, which makes it dependent on
> the first patch in the series.
>
> > + error = _("Read-only CSR is used");
>
> The error looks a little odd to me. Using implies that you are
> reading it, which is OK for a read-only CSR. I would suggest "written
> to" instead of "used". That makes the error more obvious.
OK, _("Read-only CSR is written") is better.
Thanks
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
2020-02-01 3:08 ` Jim Wilson
@ 2020-02-04 7:48 ` Nelson Chu
2020-02-04 20:22 ` Jim Wilson
0 siblings, 1 reply; 25+ messages in thread
From: Nelson Chu @ 2020-02-04 7:48 UTC (permalink / raw)
To: Jim Wilson; +Cc: Binutils
Hi Jim,
On Sat, Feb 1, 2020 at 11:08 AM Jim Wilson <jimw@sifive.com> wrote:
>
> Though now I'm wondering if maybe csrcheck
> can choose between an error and a warning. So we have a choice here
> between error/no error or error/warning. There is a gas option
> --fatal-warnings that will turn warnings into errors for people that
> want that. And a --no-warn/-W option that turns warnings off, if
> people don't want the warning.
If the csr check is a warning, then do we still need to support the
-mcsr-check options?
We also generate the warning for the csr check, and user can use
--fatal-warnings and --no-warn/-W options to decide whether the
warning is needed. It seems like we no longer need the csr check
options, is it right?
> I think -mcsrcheck is a little hard to parse, maybe -mcsr-check
> instead? And similarly for the .option if we do that.
OK, this naming is better to parse.
> Also, not directly related to this patch, but I noticed that we are
> missing doc entries for the -march-attr/-mno-arch-attr command line
> options added a year ago. That would be at least partly my fault for
> not asking for that during the review. Maybe something you can add to
> your to do list.
OK, noted :)
> This fixes the csr-dw-regnums rv64 testsuite failure from the second
> patch by accident, because you didn't turn on csrchecking for that
> test. But it should still be fixed anyways, in case someone turns
> this on by default in their copy of binutils.
Maybe we can add the -W option to the csr-dw-regnums rv64 testsuite?
or we can add the -march=rv32if option which is mentioned in the
previous mail. I think both are workable.
Thanks
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] RISC-V: Disable the CSR checking by default.
2020-02-04 7:48 ` Nelson Chu
@ 2020-02-04 20:22 ` Jim Wilson
0 siblings, 0 replies; 25+ messages in thread
From: Jim Wilson @ 2020-02-04 20:22 UTC (permalink / raw)
To: Nelson Chu; +Cc: Binutils
On Mon, Feb 3, 2020 at 11:48 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> If the csr check is a warning, then do we still need to support the
> -mcsr-check options?
I think the option is still useful. Gives people a way to turn this
particular warning off if they don't want it.
> Maybe we can add the -W option to the csr-dw-regnums rv64 testsuite?
> or we can add the -march=rv32if option which is mentioned in the
> previous mail. I think both are workable.
I'd suggest adding the -march=rv32if option.
Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2020-02-01 0:24 ` Andrew Waterman
2020-02-04 7:06 ` Nelson Chu
@ 2020-02-10 18:12 ` Palmer Dabbelt via binutils
2020-02-11 3:23 ` Nelson Chu
1 sibling, 1 reply; 25+ messages in thread
From: Palmer Dabbelt via binutils @ 2020-02-10 18:12 UTC (permalink / raw)
To: Andrew Waterman; +Cc: Jim Wilson, nelson.chu, binutils
On Fri, 31 Jan 2020 16:24:29 PST (-0800), Andrew Waterman wrote:
> On Fri, Jan 31, 2020 at 4:19 PM Jim Wilson <jimw@sifive.com> wrote:
>>
>> On Sun, Dec 15, 2019 at 9:22 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>> > gas/
>> > * testsuite/gas/riscv/priv-reg.s: Rename to priv-reg-all.s Update
>> > the CSR to privilege spec 1.12.
>> > * testsuite/gas/riscv/priv-reg.d: Likewise.
>> > * testsuite/gas/riscv/bad-csr.s: Rename to priv-reg-fail-nonexistent.
>> > * testsuite/gas/riscv/bad-csr.d: Likewise.
>> > * testsuite/gas/riscv/bad-csr.l: Likewise.
>> > * testsuite/gas/riscv/satp.s: Deleted. Duplicate of priv-reg-all.s
>> > * testsuite/gas/riscv/satp.d: Likewise.
>> > * testsuite/gas/riscv/csr-dw-regnums.s: Updated.
>> > * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
>> >
>> > include/
>> > * opcode/riscv-opc.h: Update the CSR to privilege spec 1.12.
>> >
>> > gdb/
>> > * features/riscv/32bit-csr.xml: Regenerated.
>> > * features/riscv/64bit-csr.xml: Regenerated.
>>
>> Privilege spec 1.11 is ratified, and spec 1.12 is in draft form. Do
>> we want to implement a draft?
>
> It seems inadvisable to incorporate draft standards into the FSF
> binutils port. In particular, the hypervisor ISA is virtually certain
> to change in backwards-incompatible ways prior to being frozen. It
> seems to me that pushing this stuff upstream at this time will cause
> more problems than it solves.
>
> We could consider maintaining these patches on branches in the RISC-V
> github repositories, and push them to the FSF tree at the appropriate
> time. That way, we can support software development against these
> draft standards while reducing the scope of backwards
> incompatibilities.
That's the approach we're taking everywhere else, and I think it's the right
way to go here. Sorry, I must have been off by one when I was looking.
>
>>
>>
>> I see some hypervisor registers missing, e.g. hgeie and hgeip which
>> were added to the 1.12 draft on November 20. Hie was added Oct 29,
>> and is listed as dropped in your patch. It isn't clear to me which
>> version of the 1.12 draft you are using, but it seems to be an old
>> one. If we are implementing
>> 1.12 draft we should probably implement the current one.
>>
>> Overall it looks reasonable, but we need to be clear which spec we are
>> implementing, so we can verify that the patch matches the spec.
>>
>> I see that the csr-dw-regnums.s test doesn't have any of the csr
>> aliases, but that seems OK. priv-reg-all.s is the important one and
>> does have all of them.
>>
>> You are modifying gdb xml files. These need to be sent to gdb-patches
>> for approval instead of the binutils list, and I don't have gdb patch
>> approval permission. These are shared with qemu, and ideally should
>> be kept in sync. As a practical matter though, gdb doesn't use the
>> csr xml files as yet. And updating qemu means adding priv spec 1.12
>> draft support to qemu which is probably non-trivial, unless we can
>> ignore the as yet unsupported registers in the gdb stub which should
>> work. I believe WDC is working on the qemu hypervisor support, so it
>> might actually be tracking the 1.12 draft already. It is probably OK
>> to submit the gdb xml changes, and then file a bug somewhere asking
>> for gdb and qemu xml support to be synchronized.
>>
>> Jim
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12.
2020-02-10 18:12 ` Palmer Dabbelt via binutils
@ 2020-02-11 3:23 ` Nelson Chu
0 siblings, 0 replies; 25+ messages in thread
From: Nelson Chu @ 2020-02-11 3:23 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Andrew Waterman, Jim Wilson, Binutils
Thanks Palmer :)
Your feedback convinced me that implement the draft is inadvisable. I
have fixed the series of patches according to Jim, Andrew and your
suggestions, and now is waiting for the approval of gdb since there
are some gdb modifications. And I'm not sure that the modifications
is good enough in gdb side.
Thanks again
Nelson
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2020-02-11 3:23 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-16 5:21 [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
2019-12-16 5:21 ` [PATCH v3 3/4] RISC-V: Support the read-only CSR checking Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 2:38 ` Jim Wilson
2020-02-04 7:31 ` Nelson Chu
2019-12-16 5:21 ` [PATCH v3 4/4] RISC-V: Disable the CSR checking by default Nelson Chu
2020-01-03 1:32 ` [PING] " Nelson Chu
2020-02-01 3:08 ` Jim Wilson
2020-02-04 7:48 ` Nelson Chu
2020-02-04 20:22 ` Jim Wilson
2019-12-16 5:21 ` [PATCH v3 1/4] RISC-V: Update the CSR to privilege spec 1.12 Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 0:19 ` Jim Wilson
2020-02-01 0:24 ` Andrew Waterman
2020-02-04 7:06 ` Nelson Chu
2020-02-10 18:12 ` Palmer Dabbelt via binutils
2020-02-11 3:23 ` Nelson Chu
2019-12-16 5:21 ` [PATCH v3 2/4] RISC-V: Support the ISA-dependent CSR checking Nelson Chu
2020-01-03 1:31 ` [PING] " Nelson Chu
2020-02-01 1:27 ` Jim Wilson
2020-02-04 7:15 ` Nelson Chu
2020-01-03 1:29 ` [PING] [PATCH v3 0/4] RISC-V: Support more rigorous check for CSR, and update them to spec 1.12 Nelson Chu
2020-01-22 21:35 ` Palmer Dabbelt via binutils
2020-01-27 23:26 ` Jim Wilson
2020-01-30 18:39 ` Palmer Dabbelt via binutils
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