From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 818 invoked by alias); 3 Mar 2020 22:16:23 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Received: (qmail 457 invoked by uid 89); 3 Mar 2020 22:16:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-vs1-f68.google.com Received: from mail-vs1-f68.google.com (HELO mail-vs1-f68.google.com) (209.85.217.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Mar 2020 22:16:21 +0000 Received: by mail-vs1-f68.google.com with SMTP id w142so3505517vsw.9 for ; Tue, 03 Mar 2020 14:16:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sdvmv6prYzZe+yAlDPqhzhbEfjugatotenEs5D8AZoA=; b=FyzULGtT1xPdjXAu/wOXt836nsqxad0c7johF+aqJsPyCEc4Pj4Vfv1wqnEmu+RCh0 t73HepdbRKEOypGVYdkioZz4D3IijuReuaCHIyN21DkfAMI36d0otktFGVdyczAFjlpZ Tsp3tW96q2GoQCnttHJ9E0c8ngVXnZ7B9EEXvP/XeBQq9AKDIIogd3TI2ZFRQL20oe8F pqdK9wolU6tk3Tmmj5UI7v/zdSargr3y4z5NH3QQKgb1NT4NDaKMZQkWhhXnTj626LMr kTygONIqZpmd4mG6mIl7y/zO7S5Y9E6WIdpg2mPyHTY5jNOUPuna6FpZuNf+aB6W0M/n Ko3Q== MIME-Version: 1.0 References: <1583230959-11401-1-git-send-email-nelson.chu@sifive.com> <1583230959-11401-3-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1583230959-11401-3-git-send-email-nelson.chu@sifive.com> From: Jim Wilson Date: Tue, 03 Mar 2020 22:16:00 -0000 Message-ID: Subject: Re: [PATCH 2/2] RISC-V: Support assembler modifier %got_pcrel_hi. To: Nelson Chu Cc: Binutils , James Clarke , Kito Cheng , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-03/txt/msg00055.txt On Tue, Mar 3, 2020 at 2:22 AM Nelson Chu wrote: > > gas/ > * config/tc-riscv.c: Support the modifier %got_pcrel_hi. > * doc/c-riscv.texi: Add documentation. > * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new > modifier %got_pcrel_hi. > * testsuite/gas/riscv/no-relax-reloc.s: Likewise. > * testsuite/gas/riscv/relax-reloc.d: Likewise. > * testsuite/gas/riscv/relax-reloc.s: Likewise. This looks good. I'd just suggest some minor doc fixes to be consistent with suggestions for the first patch. > +@item %got_pcrel_hi(@var{symbol} > +The high 20-bit of relative address between pc and the GOT entry of > +@var{symbol}. This is usually used with the %pcrel_lo to access the GOT entry. 20-bit -> 20 bits "the %pcrel_lo" -> "%pcrel_lo" or "the %pcrel_lo modifier" > +@smallexample > +@var{label}: > + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 > + addi/load/store a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I/S > +@end smallexample > + > +Also, the pseudo la instruction with PIC has the similar behavior. "the similar" -> "similar" or "the same" Jim