From: Mel Chen <mel.chen@sifive.com>
To: binutils@sourceware.org, kito.cheng@gmail.com, jimw@sifive.com
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH][1/2] RISC-V: Set floating-point CSR-access instructions to alias instructions
Date: Tue, 30 Jul 2019 11:57:00 -0000 [thread overview]
Message-ID: <CAH6HdcOMD72V69gYf3uMNZ8yTV_Vud5DZG10j9iQYPyuR8RyPw@mail.gmail.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 572 bytes --]
This patch sets floating-point CSR-access pseudoinstructions to aliases.
opcodes/
* riscv-opc.c (riscv_opcodes): Set floating-point CSR-access
instructions to alias instructions.
Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags,
fsflags, fsflagsi to alias instructions.
gas/
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
alias instructions.
* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s
with -Mno-aliases.
[-- Attachment #2: 0001-RISC-V-Set-floating-point-CSR-access-instructions-to.patch --]
[-- Type: application/octet-stream, Size: 7164 bytes --]
From 6c8cf381f4438b36b7e5acec166445b8c87f8f5d Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen@sifive.com>
Date: Mon, 29 Jul 2019 23:28:52 -0700
Subject: [PATCH 1/2] RISC-V: Set floating-point CSR-access instructions to
alias instructions.
opcodes/
* riscv-opc.c (riscv_opcodes): Set floating-point CSR-access
instructions to alias instructions.
Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags,
fsflags, fsflagsi to alias instructions.
gas/
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
alias instructions.
* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s
with -Mno-aliases.
---
gas/ChangeLog | 7 +++++++
gas/testsuite/gas/riscv/alias-csr.s | 14 ++++++++++++++
gas/testsuite/gas/riscv/no-aliases-csr.d | 23 +++++++++++++++++++++++
opcodes/ChangeLog | 8 ++++++++
opcodes/riscv-opc.c | 32 ++++++++++++++++----------------
5 files changed, 68 insertions(+), 16 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/alias-csr.s
create mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 34581e0..bf2e5a6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
+ alias instructions.
+ * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
+ -Mno-aliases.
+
2019-07-24 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
new file mode 100644
index 0000000..8577de1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/alias-csr.s
@@ -0,0 +1,14 @@
+alias_csr:
+ frcsr t0
+ fscsr t0, t2
+ fscsr t2
+ frrm t0
+ fsrm t0, t1
+ fsrm t1
+ fsrmi t0, 31
+ fsrmi 31
+ frflags t0
+ fsflags t0, t1
+ fsflags t1
+ fsflagsi t0, 31
+ fsflagsi 31
diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
new file mode 100644
index 0000000..2275330
--- /dev/null
+++ b/gas/testsuite/gas/riscv/no-aliases-csr.d
@@ -0,0 +1,23 @@
+#source: alias-csr.s
+#as: -march=rv64if
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <alias_csr>:
+[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
+[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
+[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
+[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
+[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
+[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
+[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
+[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
+[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
+[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
+[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
+[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
+[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ba0be86..e86d387 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Set floating-point CSR-access
+ instructions to alias instructions.
+
+ Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags,
+ fsflagsi to alias instructions.
+
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 113d1a5..6fc5ac6 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -496,22 +496,22 @@ const struct riscv_opcode riscv_opcodes[] =
{"remuw", 64, {"M", 0}, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
/* Single-precision floating-point instruction subset */
-{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 },
-{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
+{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS },
+{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS },
{"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
--
2.7.4
next reply other threads:[~2019-07-30 11:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 11:57 Mel Chen [this message]
2019-07-30 21:48 ` Jim Wilson
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