From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by sourceware.org (Postfix) with ESMTPS id 07DD93858001 for ; Tue, 15 Mar 2022 16:24:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 07DD93858001 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-lj1-x235.google.com with SMTP id c15so10642298ljr.9 for ; Tue, 15 Mar 2022 09:24:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=jkXqn3wrOOrWrZO4To++fQ/UnsLAxObq2gvPgxG/UTc=; b=XIwEtEHbdFnRhr2tV1Rg/wKnl6cQneVdail1Z5YoD4wJ15oRI0wumAN3gACdAGLqAd QF7EAvOmJTrwj4Z9qgd+esj/+0R3H66GrmyiVU62S13bARYCF2Vh/izTz9rBT21Q3RvA trHkM1Rv5w92x4F3JiTsPa2rZ2A5m177KowjivxoJjdHNOSn+4wDB4xvhNSFytIELpjy YJvfsK5M1EIijLT3Mtw/9aUsHbQ515m87kjtoKZztw1eZE24sMDkqpapj5ZKwQbfxnf4 l0Fdy/hhL0TpX4lYMOTtVJmemNE7GFoGpZEbXjCq7vZHnGtn5Uh+YsfXG53VB9A33Y3a J3CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=jkXqn3wrOOrWrZO4To++fQ/UnsLAxObq2gvPgxG/UTc=; b=bjrf8yD5hqnYGjdpBVpVUwxJwttVmfYUey3o/pygbrvMcuWsDffiUlIBefZspn4Z56 nJMqCmoYFGWDablgmb0FbkcMDowoj607EI56Pw9Ll+HW2ZlVIBxiCNJjjafZGRBcmYTT l3ShhzIR2AHzlSuJC8ZE/vCD9Pc8NOAzQI2PE44o+pjIeZZGBTHkO6fKVoChn2DYV/+G AhbGjulwm51ISy8ZuXB8iGwCXnpRo7Nf4dMAJSg7AKp7YcUH13eyZBl5n+UEhOJWBWGM KfSIQAo+mu/NG5n6pwLj0LFQI9ykwAZimVAy4JG7YmGyOPsH3GoYOB4qJqf9VJLjp4Ho sbZA== X-Gm-Message-State: AOAM531/zBhnRMQeTyUDxl1l4Mkl87UwtTROatcBUOmrvNjhc/eq7Tlk mgFvN+8u2OVcyiEEJ0K6h4ff3Uh/eaH1MY7eRfeaKg== X-Google-Smtp-Source: ABdhPJw9EHL9hMlfgn5UnMkpnDSSBHR/mvSFZ6QG07QUqVJ5++lLqt6PPdtKkJXlgcsOG9UhsBmNhleRCAsYhEaoeiU= X-Received: by 2002:a2e:9f02:0:b0:244:8e4b:5aaa with SMTP id u2-20020a2e9f02000000b002448e4b5aaamr17734309ljk.249.1647361479425; Tue, 15 Mar 2022 09:24:39 -0700 (PDT) MIME-Version: 1.0 References: <20220315024318.297-1-shihua@iscas.ac.cn> In-Reply-To: <20220315024318.297-1-shihua@iscas.ac.cn> From: Christoph Muellner Date: Tue, 15 Mar 2022 17:24:28 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Support ZTSO extension To: Shihua Liao Cc: binutils@sourceware.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , jiawei , nelson.chu@sifive.com X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Mar 2022 16:24:43 -0000 On Tue, Mar 15, 2022 at 3:44 AM wrote: > From: LiaoShihua > > ZTSO is the extension of tatol store order model. > typo: tatol -> total > This extension adds no new instructions to the ISA, and you can use it > with arch "ztso". > If you use it, TSO flag will be generate in the ELF header. > > bfd\ChangeLog: > > * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data):Add > support for ztso extension. > * elfxx-riscv.c (riscv_multi_subset_supports):Ditto. > > binutils\ChangeLog: > > * readelf.c (get_machine_flags):Ditto. > > gas\ChangeLog: > > * config/tc-riscv.c (struct riscv_set_options):Ditto. > (riscv_set_tso):Ditto. > (riscv_set_arch):Ditto. > > include\ChangeLog: > > * elf/riscv.h (EF_RISCV_TSO):Ditto. > * opcode/riscv.h (enum riscv_insn_class):Ditto. > > --- > bfd/elfnn-riscv.c | 3 +++ > bfd/elfxx-riscv.c | 3 +++ > binutils/readelf.c | 3 +++ > gas/config/tc-riscv.c | 17 +++++++++++++++++ > include/elf/riscv.h | 3 +++ > include/opcode/riscv.h | 1 + > 6 files changed, 30 insertions(+) > > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c > index 8f9f0d8a86a..25e8082b957 100644 > --- a/bfd/elfnn-riscv.c > +++ b/bfd/elfnn-riscv.c > @@ -3886,6 +3886,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, > struct bfd_link_info *info) > /* Allow linking RVC and non-RVC, and keep the RVC flag. */ > elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC; > > + /* Allow linking ZTSO and non-ZTSO, and keep the TSO flag. */ > + elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO; > Is this flag evaluated anywhere? I.e. how do we protect users from executing TSO binaries on RVWMO systems? In the case of e.g. compressed instructions, they will run into a SIG_ILL, but here they will observe unpredictable behavior if we don't do anything. > + > return true; > > fail: > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 2915b74dd0f..a041c89a623 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1215,6 +1215,7 @@ static struct riscv_supported_ext > riscv_supported_std_z_ext[] = > {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"ztso", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, > {NULL, 0, 0, 0, 0} > }; > > @@ -2393,6 +2394,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t > *rps, > || riscv_subset_supports (rps, "zve32f")); > case INSN_CLASS_SVINVAL: > return riscv_subset_supports (rps, "svinval"); > + case INSN_CLASS_ZTSO: > + return riscv_subset_supports (rps, "ztso"); > default: > rps->error_handler > (_("internal: unreachable INSN_CLASS_*")); > diff --git a/binutils/readelf.c b/binutils/readelf.c > index 16efe1dfd2d..ba4d6f9db4f 100644 > --- a/binutils/readelf.c > +++ b/binutils/readelf.c > @@ -3975,6 +3975,9 @@ get_machine_flags (Filedata * filedata, unsigned > e_flags, unsigned e_machine) > > if (e_flags & EF_RISCV_RVE) > strcat (buf, ", RVE"); > + > + if (e_flags & EF_RISCV_TSO) > + strcat (buf, ", TSO"); > > switch (e_flags & EF_RISCV_FLOAT_ABI) > { > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 9cc0abfda88..ed33cfa919a 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -222,6 +222,7 @@ struct riscv_set_options > int relax; /* Emit relocs the linker is allowed to relax. */ > int arch_attr; /* Emit architecture and privileged elf attributes. */ > int csr_check; /* Enable the CSR checking. */ > + int tso; /* Use TSO model. */ > }; > > static struct riscv_set_options riscv_opts = > @@ -231,6 +232,7 @@ static struct riscv_set_options riscv_opts = > 1, /* relax */ > DEFAULT_RISCV_ATTR, /* arch_attr */ > 0, /* csr_check */ > + 0, /* tso */ > }; > > /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag > @@ -245,6 +247,18 @@ riscv_set_rvc (bool rvc_value) > riscv_opts.rvc = rvc_value; > } > > +/* Enable or disable the tso flags for riscv_opts. Turn on the tso flag > + for elf_flags once we have enabled ztso extension. */ > + > +static void > +riscv_set_tso (bool tso_value) > +{ > + if (tso_value) > + elf_flags |= EF_RISCV_TSO; > + > + riscv_opts.tso = tso_value; > +} > + > /* This linked list records all enabled extensions, which are parsed from > the architecture string. The architecture string can be set by the > -march option, the elf architecture attributes, and the --with-arch > @@ -295,6 +309,9 @@ riscv_set_arch (const char *s) > riscv_set_rvc (false); > if (riscv_subset_supports (&riscv_rps_as, "c")) > riscv_set_rvc (true); > + > + if (riscv_subset_supports (&riscv_rps_as, "ztso")) > + riscv_set_tso (true); > } > > /* Indicate -mabi option is explictly set. */ > diff --git a/include/elf/riscv.h b/include/elf/riscv.h > index d0acf6886d8..eed3ec5f82e 100644 > --- a/include/elf/riscv.h > +++ b/include/elf/riscv.h > @@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max) > /* File uses the 32E base integer instruction. */ > #define EF_RISCV_RVE 0x0008 > > +/* File uses the TSO model. */ > +#define EF_RISCV_TSO 0x0010 > + > /* The name of the global pointer symbol. */ > #define RISCV_GP_SYMBOL "__global_pointer$" > > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 048ab0a5d68..ed81df271c1 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -388,6 +388,7 @@ enum riscv_insn_class > INSN_CLASS_V, > INSN_CLASS_ZVEF, > INSN_CLASS_SVINVAL, > + INSN_CLASS_ZTSO, > }; > > /* This structure holds information for a particular instruction. */ > -- > 2.31.1.windows.1 > >