Re: [PATCH] RISC-V: Support ZTSO extension

[Christoph Muellner <cmuellner@ventanamicro.com>]

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Hi Vineet,

Ztso is currently in public review.
I would expect the kernel patch to be part of the ratification plan.
I'll follow up with Jeff to see where we are.

Thanks,
Christoph


On Thu, Sep 15, 2022 at 9:49 PM Vineet Gupta <vineetg@rivosinc.com> wrote:

> On 3/14/22 19:43, shihua@iscas.ac.cn wrote:
> > From: LiaoShihua <shihua@iscas.ac.cn>
> >
> >     ZTSO is the extension of tatol store order model.
> >     This extension adds no new instructions to the ISA, and you can use
> it with arch "ztso".
> >     If you use it, TSO flag will be generate in the ELF header.
> >
> > bfd\ChangeLog:
> >
> >          * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data):Add
> support for ztso extension.
> >          * elfxx-riscv.c (riscv_multi_subset_supports):Ditto.
> >
> > binutils\ChangeLog:
> >
> >          * readelf.c (get_machine_flags):Ditto.
> >
> > gas\ChangeLog:
> >
> >          * config/tc-riscv.c (struct riscv_set_options):Ditto.
> >          (riscv_set_tso):Ditto.
> >          (riscv_set_arch):Ditto.
> >
> > include\ChangeLog:
> >
> >          * elf/riscv.h (EF_RISCV_TSO):Ditto.
> >          * opcode/riscv.h (enum riscv_insn_class):Ditto.
>
> Ping ! This got lost because kernel bits were missing.
> But this was a pre-req for gcc patch not being merged and I'm sure that
> circularly gates a kernel change :-)
>
> Can we please break the dependency chain and merge this first.
>
> Thx,
> -Vineet
>
> >
> > ---
> >   bfd/elfnn-riscv.c      |  3 +++
> >   bfd/elfxx-riscv.c      |  3 +++
> >   binutils/readelf.c     |  3 +++
> >   gas/config/tc-riscv.c  | 17 +++++++++++++++++
> >   include/elf/riscv.h    |  3 +++
> >   include/opcode/riscv.h |  1 +
> >   6 files changed, 30 insertions(+)
> >
> > diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> > index 8f9f0d8a86a..25e8082b957 100644
> > --- a/bfd/elfnn-riscv.c
> > +++ b/bfd/elfnn-riscv.c
> > @@ -3886,6 +3886,9 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd,
> struct bfd_link_info *info)
> >     /* Allow linking RVC and non-RVC, and keep the RVC flag.  */
> >     elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_RVC;
> >
> > +  /* Allow linking ZTSO and non-ZTSO, and keep the TSO flag.  */
> > +  elf_elfheader (obfd)->e_flags |= new_flags & EF_RISCV_TSO;
> > +
> >     return true;
> >
> >    fail:
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index 2915b74dd0f..a041c89a623 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1215,6 +1215,7 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> >     {"zvl16384b",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> >     {"zvl32768b",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> >     {"zvl65536b",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> > +  {"ztso",           ISA_SPEC_CLASS_DRAFT,           0, 1,  0 },
> >     {NULL, 0, 0, 0, 0}
> >   };
> >
> > @@ -2393,6 +2394,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> >             || riscv_subset_supports (rps, "zve32f"));
> >       case INSN_CLASS_SVINVAL:
> >         return riscv_subset_supports (rps, "svinval");
> > +    case INSN_CLASS_ZTSO:
> > +      return riscv_subset_supports (rps, "ztso");
> >       default:
> >         rps->error_handler
> >           (_("internal: unreachable INSN_CLASS_*"));
> > diff --git a/binutils/readelf.c b/binutils/readelf.c
> > index 16efe1dfd2d..ba4d6f9db4f 100644
> > --- a/binutils/readelf.c
> > +++ b/binutils/readelf.c
> > @@ -3975,6 +3975,9 @@ get_machine_flags (Filedata * filedata, unsigned
> e_flags, unsigned e_machine)
> >
> >         if (e_flags & EF_RISCV_RVE)
> >           strcat (buf, ", RVE");
> > +
> > +       if (e_flags & EF_RISCV_TSO)
> > +         strcat (buf, ", TSO");
> >
> >         switch (e_flags & EF_RISCV_FLOAT_ABI)
> >           {
> > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> > index 9cc0abfda88..ed33cfa919a 100644
> > --- a/gas/config/tc-riscv.c
> > +++ b/gas/config/tc-riscv.c
> > @@ -222,6 +222,7 @@ struct riscv_set_options
> >     int relax; /* Emit relocs the linker is allowed to relax.  */
> >     int arch_attr; /* Emit architecture and privileged elf attributes.
> */
> >     int csr_check; /* Enable the CSR checking.  */
> > +  int tso; /* Use TSO model.  */
> >   };
> >
> >   static struct riscv_set_options riscv_opts =
> > @@ -231,6 +232,7 @@ static struct riscv_set_options riscv_opts =
> >     1, /* relax */
> >     DEFAULT_RISCV_ATTR, /* arch_attr */
> >     0, /* csr_check */
> > +  0, /* tso */
> >   };
> >
> >   /* Enable or disable the rvc flags for riscv_opts.  Turn on the rvc
> flag
> > @@ -245,6 +247,18 @@ riscv_set_rvc (bool rvc_value)
> >     riscv_opts.rvc = rvc_value;
> >   }
> >
> > +/* Enable or disable the tso flags for riscv_opts.  Turn on the tso flag
> > +   for elf_flags once we have enabled ztso extension.  */
> > +
> > +static void
> > +riscv_set_tso (bool tso_value)
> > +{
> > +  if (tso_value)
> > +    elf_flags |= EF_RISCV_TSO;
> > +
> > +  riscv_opts.tso = tso_value;
> > +}
> > +
> >   /* This linked list records all enabled extensions, which are parsed
> from
> >      the architecture string.  The architecture string can be set by the
> >      -march option, the elf architecture attributes, and the --with-arch
> > @@ -295,6 +309,9 @@ riscv_set_arch (const char *s)
> >     riscv_set_rvc (false);
> >     if (riscv_subset_supports (&riscv_rps_as, "c"))
> >       riscv_set_rvc (true);
> > +
> > +  if (riscv_subset_supports (&riscv_rps_as, "ztso"))
> > +    riscv_set_tso (true);
> >   }
> >
> >   /* Indicate -mabi option is explictly set.  */
> > diff --git a/include/elf/riscv.h b/include/elf/riscv.h
> > index d0acf6886d8..eed3ec5f82e 100644
> > --- a/include/elf/riscv.h
> > +++ b/include/elf/riscv.h
> > @@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
> >   /* File uses the 32E base integer instruction.  */
> >   #define EF_RISCV_RVE 0x0008
> >
> > +/* File uses the TSO model. */
> > +#define EF_RISCV_TSO 0x0010
> > +
> >   /* The name of the global pointer symbol.  */
> >   #define RISCV_GP_SYMBOL "__global_pointer$"
> >
> > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> > index 048ab0a5d68..ed81df271c1 100644
> > --- a/include/opcode/riscv.h
> > +++ b/include/opcode/riscv.h
> > @@ -388,6 +388,7 @@ enum riscv_insn_class
> >     INSN_CLASS_V,
> >     INSN_CLASS_ZVEF,
> >     INSN_CLASS_SVINVAL,
> > +  INSN_CLASS_ZTSO,
> >   };
> >
> >   /* This structure holds information for a particular instruction.  */
>
>