From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe36.google.com (mail-vs1-xe36.google.com [IPv6:2607:f8b0:4864:20::e36]) by sourceware.org (Postfix) with ESMTPS id 010B63856DCA for ; Fri, 20 May 2022 14:24:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 010B63856DCA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-vs1-xe36.google.com with SMTP id z6so8383751vsp.0 for ; Fri, 20 May 2022 07:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hu8pRf5wNrc+v9PTYI+iANZLN+uDDg/cH9A0tjHRReM=; b=Xul64/AmD9TFaZDlGOfuFskkb7TTsNQyts69AL5V6cz1mHahM45sPaQwrex5sZ6jB0 mATGXNb2MnkX6Va7YmfKJbu+1WdjUq1AY/DPM6z6t3/+NcTtnzzJdYT5x/Y95IkTEkxs vPdgXjGncHb6w+Szf08AyXFsMNeheNauCFqGTIgeNU6eYjXB3UqIktIixpQMrkExGk45 AQts6Uqsn1T2CeAZFy7s/1y10t2szjoNyxvlOU1IMIRERv4acqwnA5cT9wimab9zFgAF ceRTz7dCuTb9mrUIz6W/dOCKZXl3n9n7jjFc/ZAKumhHHkdl4qpi4RxoiXtwzzQdnprT 4seQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hu8pRf5wNrc+v9PTYI+iANZLN+uDDg/cH9A0tjHRReM=; b=YxzWwTbujajfwe/KuxwAiLdPpQAp0CavNheJnunZaQvNHgGpsuBtfP2r6Mvu0aBsd5 VFL0V5gfUrFaAnVaCJktzXrvO927PrCTtpZeSPtjQg0o4S4X4/4MetHPBAu7ZB3tFoDO UoqslzY3PqofmM16gMdMvCNJ0Is09D8AtHyc9eoPqQu3/ErXivnm6bFoBbKwzOhW2O1r exT72uh/5QWyw9XJ3WCoAC2XUoPm+xiGpPbwNlWsUYJ2yAXTkLLIwSd004vUjduYs+t2 i6ouin2kTp+Z17aewZqbgitbM1YqW9V8fsv0SebDcEum0SVRe2Tywhk5QDex7AKjTA+b 7PUw== X-Gm-Message-State: AOAM532S4Z9PlxuqTJAJpRKCPvQu9lIj3t474gs8ANSsnBYSmcZ8m71I wDi2TjvvLE47Du5CwVsLm5EOLu+bgYuABxo6KE4hDk8l+/7Kvw== X-Google-Smtp-Source: ABdhPJwpH9cHwS1dviqRk+eVAZY++TTVpuOH0sCx2+rsYwYkrEQlgbjf+0yRacTkZwNf17rx+WUKvDv6qgUZIM/XFug= X-Received: by 2002:a67:f8ce:0:b0:335:d520:ab7f with SMTP id c14-20020a67f8ce000000b00335d520ab7fmr4502337vsp.51.1653056664307; Fri, 20 May 2022 07:24:24 -0700 (PDT) MIME-Version: 1.0 References: <20220520100934.1046277-1-jiawei@iscas.ac.cn> <1d8db6d3-1fe8-50b4-1900-c779a85ffcbf@irq.a4lg.com> In-Reply-To: <1d8db6d3-1fe8-50b4-1900-c779a85ffcbf@irq.a4lg.com> From: Nelson Chu Date: Fri, 20 May 2022 22:24:14 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Update zfinx implement with zicsr. To: Tsukasa OI Cc: Binutils , jiawei Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 May 2022 14:24:27 -0000 OK, committed. Thanks Nelson On Fri, May 20, 2022 at 8:06 PM Tsukasa OI via Binutils wrote: > > LGTM. I actually had exactly the same change in my Zfinx-related fixes > (PATCH v2) except I didn't make CSR-related {,pseudo}instruction testcases. > > I'll work on my other Zfinx-related fixes on your patch. > > Thanks, > Tsukasa > > On 2022/05/20 19:09, jiawei wrote: > > From: Jia-Wei Chen > > > > Update zfinx implement with zicsr, fix missing fcsr use by zfinx. > > add zicsr imply by zfinx. > > > > bfd/ChangeLog: > > > > * elfxx-riscv.c: New imply. > > > > gas/ChangeLog: > > > > * testsuite/gas/riscv/csr-insns-pseudo-zfinx.d: New test. > > > > opcodes/ChangeLog: > > > > * riscv-opc.c: Update insn class. > > > > --- > > bfd/elfxx-riscv.c | 1 + > > .../gas/riscv/csr-insns-pseudo-zfinx.d | 36 +++++++++++++++++++ > > opcodes/riscv-opc.c | 28 +++++++-------- > > 3 files changed, 51 insertions(+), 14 deletions(-) > > create mode 100644 gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d > > > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > > index 069832fece7..b2806185fa8 100644 > > --- a/bfd/elfxx-riscv.c > > +++ b/bfd/elfxx-riscv.c > > @@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > > {"zfh", "zicsr", check_implicit_always}, > > {"zqinx", "zdinx", check_implicit_always}, > > {"zdinx", "zfinx", check_implicit_always}, > > + {"zfinx", "zicsr", check_implicit_always}, > > {"zk", "zkn", check_implicit_always}, > > {"zk", "zkr", check_implicit_always}, > > {"zk", "zkt", check_implicit_always}, > > diff --git a/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d > > new file mode 100644 > > index 00000000000..6e86398cf7b > > --- /dev/null > > +++ b/gas/testsuite/gas/riscv/csr-insns-pseudo-zfinx.d > > @@ -0,0 +1,36 @@ > > +#source: csr-insns-pseudo.s > > +#as: -march=rv32i_zfinx > > +#objdump: -dr > > + > > +.*:[ ]+file format .* > > + > > + > > +Disassembly of section .text: > > + > > +0+000 : > > +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus > > +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0 > > +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0 > > +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0 > > +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31 > > +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31 > > +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31 > > +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2 > > +[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2 > > +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1 > > +[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1 > > +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31 > > +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31 > > +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0 > > +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1 > > +[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1 > > +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31 > > +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31 > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 7524be7feae..2a41db0a440 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -638,22 +638,22 @@ const struct riscv_opcode riscv_opcodes[] = > > {"fcvt.h.lu", 64, INSN_CLASS_ZFH, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, > > > > /* Single-precision floating-point instruction subset. */ > > -{"frcsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, > > -{"frsr", 0, INSN_CLASS_F, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, > > -{"fscsr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, > > -{"fscsr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, > > -{"fssr", 0, INSN_CLASS_F, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, > > -{"fssr", 0, INSN_CLASS_F, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, > > -{"frrm", 0, INSN_CLASS_F, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, > > -{"fsrm", 0, INSN_CLASS_F, "s", MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS }, > > -{"fsrm", 0, INSN_CLASS_F, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, > > -{"fsrmi", 0, INSN_CLASS_F, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, > > -{"fsrmi", 0, INSN_CLASS_F, "Z", MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS }, > > +{"frcsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, > > +{"frsr", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, > > +{"fscsr", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, > > +{"fscsr", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, > > +{"fssr", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSCSR, MASK_FSCSR|MASK_RD, match_opcode, INSN_ALIAS }, > > +{"fssr", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, > > +{"frrm", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, > > +{"fsrm", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSRM, MASK_FSRM|MASK_RD, match_opcode, INSN_ALIAS }, > > +{"fsrm", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, > > +{"fsrmi", 0, INSN_CLASS_F_OR_ZFINX, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, > > +{"fsrmi", 0, INSN_CLASS_F_OR_ZFINX, "Z", MATCH_FSRMI, MASK_FSRMI|MASK_RD, match_opcode, INSN_ALIAS }, > > {"frflags", 0, INSN_CLASS_F_OR_ZFINX, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS }, > > {"fsflags", 0, INSN_CLASS_F_OR_ZFINX, "s", MATCH_FSFLAGS, MASK_FSFLAGS|MASK_RD, match_opcode, INSN_ALIAS }, > > -{"fsflags", 0, INSN_CLASS_F, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, > > -{"fsflagsi", 0, INSN_CLASS_F, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, > > -{"fsflagsi", 0, INSN_CLASS_F, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, > > +{"fsflags", 0, INSN_CLASS_F_OR_ZFINX, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, > > +{"fsflagsi", 0, INSN_CLASS_F_OR_ZFINX, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, > > +{"fsflagsi", 0, INSN_CLASS_F_OR_ZFINX, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI|MASK_RD, match_opcode, INSN_ALIAS }, > > {"flw", 32, INSN_CLASS_F_AND_C, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, > > {"flw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, > > {"flw", 0, INSN_CLASS_F, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },