* [PATCH 0/3] RISC-V: Zfinx extension support
@ 2021-10-28 16:47 jiawei
2021-10-28 16:47 ` [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: jiawei @ 2021-10-28 16:47 UTC (permalink / raw)
To: binutils
Cc: tariq.kurd, kito.cheng, jimw, jeremy.bennett, cmuellner, palmer,
andrew, lazyparser, jiawei
This patch is support zfinx extension on binutils, zfinx is not compatible with any float extension and use gpr replace fpr, we adjust the opreand set when zfinx used. For disassemble part, we add a flag ZFINX(0x10) as ELF-header to distinguish whether use gpr or fpr name for float instructions.
jiawei (3):
RISC-V: Add mininal support for z[fdq]inx
RISC-V: Add instructions and operand set for z[fdq]inx
RISC-V: Add testcases and disassemble support for z[fdq]inx
bfd/elfxx-riscv.c | 32 +++++++
binutils/readelf.c | 3 +
gas/config/tc-riscv.c | 33 +++++++-
gas/testsuite/gas/riscv/zdinx.d | 41 +++++++++
gas/testsuite/gas/riscv/zdinx.s | 33 ++++++++
gas/testsuite/gas/riscv/zfinx.d | 39 +++++++++
gas/testsuite/gas/riscv/zfinx.s | 31 +++++++
gas/testsuite/gas/riscv/zqinx.d | 43 ++++++++++
gas/testsuite/gas/riscv/zqinx.s | 35 ++++++++
include/elf/riscv.h | 3 +
include/opcode/riscv.h | 3 +
opcodes/riscv-dis.c | 4 +
opcodes/riscv-opc.c | 146 ++++++++++++++++++++++++++++++++
13 files changed, 443 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx.d
create mode 100644 gas/testsuite/gas/riscv/zdinx.s
create mode 100644 gas/testsuite/gas/riscv/zfinx.d
create mode 100644 gas/testsuite/gas/riscv/zfinx.s
create mode 100644 gas/testsuite/gas/riscv/zqinx.d
create mode 100644 gas/testsuite/gas/riscv/zqinx.s
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx
2021-10-28 16:47 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
@ 2021-10-28 16:47 ` jiawei
2021-11-09 6:32 ` Nelson Chu
2021-10-28 16:47 ` [PATCH 2/3] RISC-V: Add instructions and operand set " jiawei
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2021-10-28 16:47 UTC (permalink / raw)
To: binutils
Cc: tariq.kurd, kito.cheng, jimw, jeremy.bennett, cmuellner, palmer,
andrew, lazyparser, jiawei
---
bfd/elfxx-riscv.c | 32 ++++++++++++++++++++++++++++++++
gas/config/tc-riscv.c | 7 +++++++
include/opcode/riscv.h | 3 +++
3 files changed, 42 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cdb4fa0996a..e62c63abbb4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1075,6 +1075,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"q", "d", check_implicit_always},
{"d", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
+ {"zqinx", "zdinx", check_implicit_always},
+ {"zdinx", "zfinx", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1146,6 +1148,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -1824,6 +1829,33 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
(_("rv32e does not support the `f' extension"));
no_conflict = false;
}
+ if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
+ && (riscv_lookup_subset (rps->subset_list, "f", &subset)
+ || riscv_lookup_subset (rps->subset_list, "d", &subset)
+ || riscv_lookup_subset (rps->subset_list, "q", &subset)))
+ {
+ rps->error_handler
+ (_("`zfinx' is conflict with the `f/d/q' extension"));
+ no_conflict = false;
+ }
+ if (riscv_lookup_subset (rps->subset_list, "zdinx", &subset)
+ && (riscv_lookup_subset (rps->subset_list, "f", &subset)
+ || riscv_lookup_subset (rps->subset_list, "d", &subset)
+ || riscv_lookup_subset (rps->subset_list, "q", &subset)))
+ {
+ rps->error_handler
+ (_("`zdinx' is conflict with the `f/d/q' extension"));
+ no_conflict = false;
+ }
+ if (riscv_lookup_subset (rps->subset_list, "zqinx", &subset)
+ && (riscv_lookup_subset (rps->subset_list, "f", &subset)
+ || riscv_lookup_subset (rps->subset_list, "d", &subset)
+ || riscv_lookup_subset (rps->subset_list, "q", &subset)))
+ {
+ rps->error_handler
+ (_("`zqinx' is conflict with the `f/d/q' extension"));
+ no_conflict = false;
+ }
return no_conflict;
}
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index f7e0c929aa0..2c4df208664 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -286,6 +286,13 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZBS:
return riscv_subset_supports ("zbs");
+ case INSN_CLASS_ZFINX:
+ return riscv_subset_supports ("zfinx");
+ case INSN_CLASS_ZDINX:
+ return riscv_subset_supports ("zdinx");
+ case INSN_CLASS_ZQINX:
+ return riscv_subset_supports ("zqinx");
+
default:
as_fatal ("internal: unreachable");
return false;
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index afcd41ff1dd..a23cd010e4a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -320,6 +320,9 @@ enum riscv_insn_class
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
INSN_CLASS_ZBS,
+ INSN_CLASS_ZFINX,
+ INSN_CLASS_ZDINX,
+ INSN_CLASS_ZQINX,
};
/* This structure holds information for a particular instruction. */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/3] RISC-V: Add instructions and operand set for z[fdq]inx
2021-10-28 16:47 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
2021-10-28 16:47 ` [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
@ 2021-10-28 16:47 ` jiawei
2021-11-09 9:51 ` Nelson Chu
2021-10-28 16:47 ` [PATCH 3/3] RISC-V: Add testcases and disassemble support " jiawei
2021-11-09 10:06 ` [PATCH 0/3] RISC-V: Zfinx extension support Nelson Chu
3 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2021-10-28 16:47 UTC (permalink / raw)
To: binutils
Cc: tariq.kurd, kito.cheng, jimw, jeremy.bennett, cmuellner, palmer,
andrew, lazyparser, jiawei
---
gas/config/tc-riscv.c | 11 +++-
opcodes/riscv-opc.c | 146 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 154 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2c4df208664..b879bf1ea8b 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1158,6 +1158,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
USE_BITS (OP_MASK_RS1, OP_SH_RS1);
/* Fall through. */
case 'T': /* RS2, floating point. */
+ case 'x': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* Fall through. */
case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
case 'R': /* RS3, floating point. */
case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
@@ -2508,6 +2509,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'd': /* Destination register. */
case 's': /* Source register. */
case 't': /* Target register. */
+ case 'x': /* rs1 and rs2. */
case 'r': /* RS3 */
if (reg_lookup (&s, RCLASS_GPR, ®no))
{
@@ -2519,12 +2521,15 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
string to figure out where it goes in the instruction. */
switch (c)
{
+ case 'd':
+ INSERT_OPERAND (RD, *ip, regno);
+ break;
case 's':
INSERT_OPERAND (RS1, *ip, regno);
break;
- case 'd':
- INSERT_OPERAND (RD, *ip, regno);
- break;
+ case 'x':
+ INSERT_OPERAND (RS1, *ip, regno);
+ /* fallthru */
case 't':
INSERT_OPERAND (RS2, *ip, regno);
break;
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b756bae64ab..435fb434161 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -534,52 +534,99 @@ const struct riscv_opcode riscv_opcodes[] =
{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.s", 0, INSN_CLASS_ZFINX, "d,x", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.s", 0, INSN_CLASS_ZFINX, "d,x", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
+{"fsgnj.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
{"fsgnjn.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
+{"fsgnjn.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
{"fsgnjx.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
+{"fsgnjx.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
{"fadd.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
{"fadd.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
+{"fadd.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
+{"fadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
{"fsub.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
{"fsub.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
+{"fsub.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
+{"fsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
{"fmul.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
{"fmul.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
+{"fmul.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
+{"fmul.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
{"fdiv.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
{"fdiv.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
+{"fdiv.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
+{"fdiv.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
{"fsqrt.s", 0, INSN_CLASS_F, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
{"fsqrt.s", 0, INSN_CLASS_F, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
+{"fsqrt.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
+{"fsqrt.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
{"fmin.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
+{"fmin.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
{"fmax.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
+{"fmax.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
{"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
{"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
+{"fmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
+{"fmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
{"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
{"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
+{"fnmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
+{"fnmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
{"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
{"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
+{"fmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
+{"fmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
{"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
{"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
+{"fnmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
+{"fnmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
{"fcvt.w.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
{"fcvt.w.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
+{"fcvt.w.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
+{"fcvt.w.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
{"fcvt.wu.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
{"fcvt.wu.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
+{"fcvt.wu.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
{"fcvt.s.w", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
{"fcvt.s.w", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
+{"fcvt.s.w", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.w", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
{"fcvt.s.wu", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
{"fcvt.s.wu", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
+{"fcvt.s.wu", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
+{"fcvt.s.wu", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
{"fclass.s", 0, INSN_CLASS_F, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
+{"fclass.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
{"feq.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
+{"feq.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
{"flt.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"flt.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
{"fle.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fle.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
{"fgt.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
+{"fgt.s", 0, INSN_CLASS_ZFINX, "d,t,s", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
{"fge.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
+{"fge.s", 0, INSN_CLASS_ZFINX, "d,t,s", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
{"fcvt.l.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
{"fcvt.l.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
+{"fcvt.l.s", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
+{"fcvt.l.s", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
{"fcvt.lu.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
{"fcvt.lu.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
{"fcvt.s.l", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
{"fcvt.s.l", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
+{"fcvt.s.l", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
+{"fcvt.s.l", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
{"fcvt.s.lu", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
{"fcvt.s.lu", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
/* Double-precision floating-point instruction subset. */
{"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
@@ -592,55 +639,103 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.d", 0, INSN_CLASS_ZDINX, "d,x", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.d", 0, INSN_CLASS_ZDINX, "d,x", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
+{"fsgnj.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
{"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
+{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
{"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
+{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
{"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
{"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
+{"fadd.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
+{"fadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
{"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
{"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
+{"fsub.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
+{"fsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
{"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
{"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
+{"fmul.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
+{"fmul.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
{"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
{"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
+{"fdiv.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
+{"fdiv.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
{"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
{"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
+{"fsqrt.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
+{"fsqrt.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
{"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
+{"fmin.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
{"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
+{"fmax.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
{"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
+{"fmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
+{"fmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
{"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
+{"fnmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
+{"fnmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
{"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
+{"fmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
+{"fmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
{"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
+{"fnmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
+{"fnmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
{"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
{"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
+{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
+{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
{"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
+{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
+{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
{"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
+{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
{"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
{"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
+{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
{"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
{"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
+{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
+{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
{"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
+{"fclass.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
{"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
+{"feq.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
{"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"flt.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
{"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fle.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
{"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
+{"fgt.d", 0, INSN_CLASS_ZDINX, "d,t,s", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
{"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
+{"fge.d", 0, INSN_CLASS_ZDINX, "d,t,s", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
{"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
{"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
{"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
{"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
+{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
+{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
{"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
+{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
+{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
{"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
{"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
+{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
+{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
{"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
/* Quad-precision floating-point instruction subset. */
{"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
@@ -649,58 +744,109 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.q", 0, INSN_CLASS_ZQINX, "d,x", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.q", 0, INSN_CLASS_ZQINX, "d,x", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
+{"fsgnj.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
{"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
+{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
{"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
+{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
{"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
{"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
+{"fadd.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
+{"fadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
{"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
{"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
+{"fsub.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
+{"fsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
{"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
{"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
+{"fmul.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
+{"fmul.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
{"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
+{"fdiv.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
+{"fdiv.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
{"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
{"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
+{"fsqrt.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
+{"fsqrt.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
{"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
+{"fmin.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
{"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
+{"fmax.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
{"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
+{"fmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
+{"fmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
{"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
+{"fnmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
+{"fnmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
{"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
+{"fmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
+{"fmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
{"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
+{"fnmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
+{"fnmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
{"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
+{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
{"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
+{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
{"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
+{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
{"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
{"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
+{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
{"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
+{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
{"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
+{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
{"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
+{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
{"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
+{"fclass.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
{"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
+{"feq.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
{"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"flt.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
{"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fle.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
{"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
+{"fgt.q", 0, INSN_CLASS_ZQINX, "d,t,s", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
{"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
+{"fge.q", 0, INSN_CLASS_ZQINX, "d,t,s", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
{"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
{"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
{"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
+{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
{"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
+{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
{"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
+{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
+{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
{"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
+{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
+{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
/* Compressed instructions. */
{"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 },
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] RISC-V: Add testcases and disassemble support for z[fdq]inx
2021-10-28 16:47 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
2021-10-28 16:47 ` [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
2021-10-28 16:47 ` [PATCH 2/3] RISC-V: Add instructions and operand set " jiawei
@ 2021-10-28 16:47 ` jiawei
2021-11-09 10:03 ` Nelson Chu
2021-11-09 10:06 ` [PATCH 0/3] RISC-V: Zfinx extension support Nelson Chu
3 siblings, 1 reply; 8+ messages in thread
From: jiawei @ 2021-10-28 16:47 UTC (permalink / raw)
To: binutils
Cc: tariq.kurd, kito.cheng, jimw, jeremy.bennett, cmuellner, palmer,
andrew, lazyparser, jiawei
---
binutils/readelf.c | 3 +++
gas/config/tc-riscv.c | 15 ++++++++++++
gas/testsuite/gas/riscv/zdinx.d | 41 +++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zdinx.s | 33 +++++++++++++++++++++++++
gas/testsuite/gas/riscv/zfinx.d | 39 ++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zfinx.s | 31 ++++++++++++++++++++++++
gas/testsuite/gas/riscv/zqinx.d | 43 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/zqinx.s | 35 +++++++++++++++++++++++++++
include/elf/riscv.h | 3 +++
opcodes/riscv-dis.c | 4 +++
10 files changed, 247 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zdinx.d
create mode 100644 gas/testsuite/gas/riscv/zdinx.s
create mode 100644 gas/testsuite/gas/riscv/zfinx.d
create mode 100644 gas/testsuite/gas/riscv/zfinx.s
create mode 100644 gas/testsuite/gas/riscv/zqinx.d
create mode 100644 gas/testsuite/gas/riscv/zqinx.s
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 682eacdef14..fc889c6c3ff 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3717,6 +3717,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
if (e_flags & EF_RISCV_RVE)
strcat (buf, ", RVE");
+ if (e_flags & EF_RISCV_ZFINX)
+ strcat (buf, ", ZFINX");
+
switch (e_flags & EF_RISCV_FLOAT_ABI)
{
case EF_RISCV_FLOAT_ABI_SOFT:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index b879bf1ea8b..ff279263ffb 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -204,6 +204,7 @@ struct riscv_set_options
int pic; /* Generate position-independent code. */
int rvc; /* Generate RVC code. */
int rve; /* Generate RVE code. */
+ int zfinx; /* Generate ZFINX code. */
int relax; /* Emit relocs the linker is allowed to relax. */
int arch_attr; /* Emit architecture and privileged elf attributes. */
int csr_check; /* Enable the CSR checking. */
@@ -214,6 +215,7 @@ static struct riscv_set_options riscv_opts =
0, /* pic */
0, /* rvc */
0, /* rve */
+ 0, /* ZFINX */
1, /* relax */
DEFAULT_RISCV_ATTR, /* arch_attr */
0, /* csr_check */
@@ -234,6 +236,15 @@ riscv_set_rve (bool rve_value)
riscv_opts.rve = rve_value;
}
+static void
+riscv_set_zfinx (bool finx_value)
+{
+ if (finx_value)
+ elf_flags |= EF_RISCV_ZFINX;
+
+ riscv_opts.finx = finx_value;
+}
+
static riscv_subset_list_t riscv_subsets;
static bool
@@ -328,6 +339,10 @@ riscv_set_arch (const char *s)
riscv_set_rve (false);
if (riscv_subset_supports ("e"))
riscv_set_rve (true);
+ if (riscv_subset_supports ("zfinx")
+ || riscv_subset_supports ("zdinx")
+ || riscv_subset_supports ("zqinx"))
+ riscv_set_finx (true);
}
/* Indicate -mabi option is explictly set. */
diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
new file mode 100644
index 00000000000..3e4c1a73388
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx.d
@@ -0,0 +1,41 @@
+#as: -march=rv64ima_zdinx
+#source: zdinx.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
new file mode 100644
index 00000000000..c427d982aaf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx.s
@@ -0,0 +1,33 @@
+target:
+ fadd.d a0, a1, a2
+ fsub.d a0, a1, a2
+ fmul.d a0, a1, a2
+ fdiv.d a0, a1, a2
+ fsqrt.d a0, a0
+ fmin.d a0, a1, a2
+ fmax.d a0, a1, a2
+ fmadd.d a0, a1, a2, a3
+ fnmadd.d a0, a1, a2, a3
+ fmsub.d a0, a1, a2, a3
+ fnmsub.d a0, a1, a2, a3
+ fcvt.w.d a0, a1
+ fcvt.wu.d a0, a1
+ fcvt.l.d a0, a1
+ fcvt.lu.d a0, a1
+ fcvt.s.d a0, a1
+ fcvt.d.s a0, a1
+ fcvt.d.w a0, a1
+ fcvt.d.wu a0, a1
+ fcvt.d.l a0, a1
+ fcvt.d.lu a0, a1
+ fsgnj.d a0, a1, a2
+ fsgnjn.d a0, a1, a2
+ fsgnjx.d a0, a1, a2
+ feq.d a0, a1, a2
+ flt.d a0, a1, a2
+ fle.d a0, a1, a2
+ fgt.d a0, a1, a2
+ fge.d a0, a1, a2
+ fneg.d a0, a0
+ fabs.d a0, a0
+ fclass.d a0, a1
diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
new file mode 100644
index 00000000000..d5499aa9131
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx.d
@@ -0,0 +1,39 @@
+#as: -march=rv64ima_zfinx
+#source: zfinx.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a0c59553[ ]+flt.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
new file mode 100644
index 00000000000..af50490fadf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx.s
@@ -0,0 +1,31 @@
+target:
+ fadd.s a0, a1, a2
+ fsub.s a0, a1, a2
+ fmul.s a0, a1, a2
+ fdiv.s a0, a1, a2
+ fsqrt.s a0, a0
+ fmin.s a0, a1, a2
+ fmax.s a0, a1, a2
+ fmadd.s a0, a1, a2, a3
+ fnmadd.s a0, a1, a2, a3
+ fmsub.s a0, a1, a2, a3
+ fnmsub.s a0, a1, a2, a3
+ fcvt.w.s a0, a1
+ fcvt.wu.s a0, a1
+ fcvt.l.s a0, a1
+ fcvt.lu.s a0, a1
+ fcvt.s.w a0, a1
+ fcvt.s.wu a0, a1
+ fcvt.s.l a0, a1
+ fcvt.s.lu a0, a1
+ fsgnj.s a0, a1, a2
+ fsgnjn.s a0, a1, a2
+ fsgnjx.s a0, a1, a2
+ feq.s a0, a1, a2
+ flt.s a0, a1, a2
+ fle.s a0, a1, a2
+ fgt.s a0, a1, a2
+ fge.s a0, a1, a2
+ fneg.s a0, a0
+ fabs.s a0, a0
+ fclass.s a0, a1
diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
new file mode 100644
index 00000000000..a1c9eab4e1d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx.d
@@ -0,0 +1,43 @@
+#as: -march=rv64ima_zqinx
+#source: zqinx.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.q[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3
+[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.d.q[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.q.d[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.q.w[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.q.wu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.q.l[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.q.lu[ ]+a0,a1
+[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.q[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.q[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.q[ ]+a0,a2,a1
+[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.q[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.q[ ]+a0,a0
+[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.q[ ]+a0,a1
diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
new file mode 100644
index 00000000000..8372ba57c71
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx.s
@@ -0,0 +1,35 @@
+target:
+ fadd.q a0, a1, a2
+ fsub.q a0, a1, a2
+ fmul.q a0, a1, a2
+ fdiv.q a0, a1, a2
+ fsqrt.q a0, a0
+ fmin.q a0, a1, a2
+ fmax.q a0, a1, a2
+ fmadd.q a0, a1, a2, a3
+ fnmadd.q a0, a1, a2, a3
+ fmsub.q a0, a1, a2, a3
+ fnmsub.q a0, a1, a2, a3
+ fcvt.w.q a0, a1
+ fcvt.wu.q a0, a1
+ fcvt.l.q a0, a1
+ fcvt.lu.q a0, a1
+ fcvt.s.q a0, a1
+ fcvt.d.q a0, a1
+ fcvt.q.s a0, a1
+ fcvt.q.d a0, a1
+ fcvt.q.w a0, a1
+ fcvt.q.wu a0, a1
+ fcvt.q.l a0, a1
+ fcvt.q.lu a0, a1
+ fsgnj.q a0, a1, a2
+ fsgnjn.q a0, a1, a2
+ fsgnjx.q a0, a1, a2
+ feq.q a0, a1, a2
+ flt.q a0, a1, a2
+ fle.q a0, a1, a2
+ fgt.q a0, a1, a2
+ fge.q a0, a1, a2
+ fneg.q a0, a0
+ fabs.q a0, a0
+ fclass.q a0, a1
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
index 80822835cd9..a73623d315d 100644
--- a/include/elf/riscv.h
+++ b/include/elf/riscv.h
@@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
/* File uses the 32E base integer instruction. */
#define EF_RISCV_RVE 0x0008
+/* File uses the gpr base ZFINX instruction. */
+#define EF_RISCV_ZFINX 0x0010
+
/* The name of the global pointer symbol. */
#define RISCV_GP_SYMBOL "__global_pointer$"
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2e28ba77e60..4bf640e6f53 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -513,6 +513,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
}
+ /* If ELF has ZFINX flags, use gpr for disassemble. */
+ if ((ehdr->e_flags & EF_RISCV_ZFINX_ABI) == EF_RISCV_ZFINX_ABI)
+ riscv_fpr_names = riscv_gpr_names_abi;
+
for (; op->name; op++)
{
/* Does the opcode match? */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx
2021-10-28 16:47 ` [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
@ 2021-11-09 6:32 ` Nelson Chu
0 siblings, 0 replies; 8+ messages in thread
From: Nelson Chu @ 2021-11-09 6:32 UTC (permalink / raw)
To: jiawei; +Cc: Binutils, tariq.kurd, cmuellner, Kito Cheng
On Fri, Oct 29, 2021 at 12:49 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> bfd/elfxx-riscv.c | 32 ++++++++++++++++++++++++++++++++
> gas/config/tc-riscv.c | 7 +++++++
> include/opcode/riscv.h | 3 +++
> 3 files changed, 42 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index cdb4fa0996a..e62c63abbb4 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1075,6 +1075,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
> {"q", "d", check_implicit_always},
> {"d", "f", check_implicit_always},
> {"f", "zicsr", check_implicit_always},
> + {"zqinx", "zdinx", check_implicit_always},
> + {"zdinx", "zfinx", check_implicit_always},
> {NULL, NULL, NULL}
> };
>
> @@ -1146,6 +1148,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
> @@ -1824,6 +1829,33 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
> (_("rv32e does not support the `f' extension"));
> no_conflict = false;
> }
> + if (riscv_lookup_subset (rps->subset_list, "zfinx", &subset)
> + && (riscv_lookup_subset (rps->subset_list, "f", &subset)
> + || riscv_lookup_subset (rps->subset_list, "d", &subset)
> + || riscv_lookup_subset (rps->subset_list, "q", &subset)))
> + {
> + rps->error_handler
> + (_("`zfinx' is conflict with the `f/d/q' extension"));
> + no_conflict = false;
> + }
> + if (riscv_lookup_subset (rps->subset_list, "zdinx", &subset)
> + && (riscv_lookup_subset (rps->subset_list, "f", &subset)
> + || riscv_lookup_subset (rps->subset_list, "d", &subset)
> + || riscv_lookup_subset (rps->subset_list, "q", &subset)))
> + {
> + rps->error_handler
> + (_("`zdinx' is conflict with the `f/d/q' extension"));
> + no_conflict = false;
> + }
> + if (riscv_lookup_subset (rps->subset_list, "zqinx", &subset)
> + && (riscv_lookup_subset (rps->subset_list, "f", &subset)
> + || riscv_lookup_subset (rps->subset_list, "d", &subset)
> + || riscv_lookup_subset (rps->subset_list, "q", &subset)))
> + {
> + rps->error_handler
> + (_("`zqinx' is conflict with the `f/d/q' extension"));
> + no_conflict = false;
> + }
> return no_conflict;
> }
For two reasons,
1. zqinx imply zdinx, and zdinx imply zfinx.
2. q imply d, and d imply f.
I would suggest that we only check the conflict between zfinx and f
should be enough.
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index f7e0c929aa0..2c4df208664 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -286,6 +286,13 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
> case INSN_CLASS_ZBS:
> return riscv_subset_supports ("zbs");
>
> + case INSN_CLASS_ZFINX:
> + return riscv_subset_supports ("zfinx");
> + case INSN_CLASS_ZDINX:
> + return riscv_subset_supports ("zdinx");
> + case INSN_CLASS_ZQINX:
> + return riscv_subset_supports ("zqinx");
> +
> default:
> as_fatal ("internal: unreachable");
> return false;
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index afcd41ff1dd..a23cd010e4a 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -320,6 +320,9 @@ enum riscv_insn_class
> INSN_CLASS_ZBB,
> INSN_CLASS_ZBC,
> INSN_CLASS_ZBS,
> + INSN_CLASS_ZFINX,
> + INSN_CLASS_ZDINX,
> + INSN_CLASS_ZQINX,
> };
This patch seems to support the zfinx, zdinx and zqinx extensions for
the architecture parser, so it is better to move these INSN_CLASS_*
changes to the remaining patches, since they won't be used here.
> /* This structure holds information for a particular instruction. */
> --
> 2.25.1
>
Thanks
Nelson
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] RISC-V: Add instructions and operand set for z[fdq]inx
2021-10-28 16:47 ` [PATCH 2/3] RISC-V: Add instructions and operand set " jiawei
@ 2021-11-09 9:51 ` Nelson Chu
0 siblings, 0 replies; 8+ messages in thread
From: Nelson Chu @ 2021-11-09 9:51 UTC (permalink / raw)
To: jiawei; +Cc: Binutils, tariq.kurd, cmuellner, Kito Cheng
This patch should work for zfinx. But we need to add a new operand
'x', and add multiple extra entries of riscv_opcodes. Jim has
suggested before, and after discussing with Kito, I think the better
solution should be as follows:
* Just change the zfinx instructions from INSN_CLASS_F to
INSN_CLASS_ZFINX class (or probably INSN_CLASS_F_OR_ZFINX), but keep
the original operands. And then update the
riscv_multi_subset_supports,
@@ -287,6 +287,8 @@ riscv_multi_subset_supports (enum riscv_insn_class
insn_class)
return riscv_subset_supports ("zbc");
case INSN_CLASS_ZBS:
return riscv_subset_supports ("zbs");
+ case INSN_CLASS_F_OR_ZFINX:
+ return (riscv_subset_supports ("f") || riscv_subset_supports ("zfinx"));
default:
as_fatal ("internal: unreachable");
return false;
* In gas/config/tc-riscv.c:riscv_ip,
@@ -2530,7 +2532,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
expressionS *imm_expr,
case 'T': /* Floating point RS2. */
case 'U': /* Floating point RS1 and RS2. */
case 'R': /* Floating point RS3. */
- if (reg_lookup (&asarg, RCLASS_FPR, ®no))
+ if (reg_lookup (&asarg, (riscv_subset_supports ("zfinx")
+ ? RCLASS_GPR : RCLASS_FPR), ®no))
{
char c = *oparg;
if (*asarg == ' ')
Therefore, I can get the expected results as follows,
nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
fadd.s fa0, fa1, fa2
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: illegal operands `fadd.s fa0,fa1,fa2'
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?
nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
fadd.s a0, a1, a2
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: illegal operands `fadd.s a0,a1,a2'
nelson@LAPTOP-QFSGI1F2:~/test$ cat tmp.s
foo:
flw fa0, foo, a1
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32i_zfinx tmp.s -o tmp.o
tmp.s: Assembler messages:
tmp.s:2: Error: unrecognized opcode `flw fa0,foo,a1'
nelson@LAPTOP-QFSGI1F2:~/test$
~/binutils-dev/build-elf64-upstream/build-install/bin/riscv64-unknown-elf-as
-march=rv32if tmp.s -o tmp.o
nelson@LAPTOP-QFSGI1F2:~/test$ echo $?
Note that the error of flw is "unrecognized opcode", since we are
using INSN_CLASS_F for these non-zfinx instructions, and f cannot be
used with zfinx at the same time. And fortunately, we only need to
hack this check for U, S, T, ... floating operand in the riscv_ip, we
don't need to handle them in the macro_build.
Thanks
Nelson
On Fri, Oct 29, 2021 at 12:50 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> gas/config/tc-riscv.c | 11 +++-
> opcodes/riscv-opc.c | 146 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 154 insertions(+), 3 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 2c4df208664..b879bf1ea8b 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1158,6 +1158,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
> USE_BITS (OP_MASK_RS1, OP_SH_RS1);
> /* Fall through. */
> case 'T': /* RS2, floating point. */
> + case 'x': USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* Fall through. */
> case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
> case 'R': /* RS3, floating point. */
> case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
> @@ -2508,6 +2509,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> case 'd': /* Destination register. */
> case 's': /* Source register. */
> case 't': /* Target register. */
> + case 'x': /* rs1 and rs2. */
> case 'r': /* RS3 */
> if (reg_lookup (&s, RCLASS_GPR, ®no))
> {
> @@ -2519,12 +2521,15 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
> string to figure out where it goes in the instruction. */
> switch (c)
> {
> + case 'd':
> + INSERT_OPERAND (RD, *ip, regno);
> + break;
> case 's':
> INSERT_OPERAND (RS1, *ip, regno);
> break;
> - case 'd':
> - INSERT_OPERAND (RD, *ip, regno);
> - break;
> + case 'x':
> + INSERT_OPERAND (RS1, *ip, regno);
> + /* fallthru */
> case 't':
> INSERT_OPERAND (RS2, *ip, regno);
> break;
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index b756bae64ab..435fb434161 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -534,52 +534,99 @@ const struct riscv_opcode riscv_opcodes[] =
> {"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
> {"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
> {"fneg.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.s", 0, INSN_CLASS_ZFINX, "d,x", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
> {"fabs.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.s", 0, INSN_CLASS_ZFINX, "d,x", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
> {"fsgnj.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
> +{"fsgnj.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
> {"fsgnjn.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
> +{"fsgnjn.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
> {"fsgnjx.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
> +{"fsgnjx.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
> {"fadd.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
> {"fadd.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
> +{"fadd.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
> +{"fadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
> {"fsub.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
> {"fsub.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
> +{"fsub.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
> +{"fsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
> {"fmul.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
> {"fmul.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
> +{"fmul.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
> +{"fmul.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
> {"fdiv.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
> {"fdiv.s", 0, INSN_CLASS_F, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
> +{"fdiv.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
> +{"fdiv.s", 0, INSN_CLASS_ZFINX, "d,s,t,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
> {"fsqrt.s", 0, INSN_CLASS_F, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
> {"fsqrt.s", 0, INSN_CLASS_F, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
> +{"fsqrt.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
> +{"fsqrt.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
> {"fmin.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
> +{"fmin.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
> {"fmax.s", 0, INSN_CLASS_F, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
> +{"fmax.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
> {"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
> {"fmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
> +{"fmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
> +{"fmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
> {"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
> {"fnmadd.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
> +{"fnmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
> +{"fnmadd.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
> {"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
> {"fmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
> +{"fmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
> {"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
> {"fnmsub.s", 0, INSN_CLASS_F, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
> +{"fnmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
> +{"fnmsub.s", 0, INSN_CLASS_ZFINX, "d,s,t,r,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
> {"fcvt.w.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
> {"fcvt.w.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
> +{"fcvt.w.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
> {"fcvt.wu.s", 0, INSN_CLASS_F, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
> {"fcvt.wu.s", 0, INSN_CLASS_F, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
> +{"fcvt.wu.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.s", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
> {"fcvt.s.w", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> {"fcvt.s.w", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
> +{"fcvt.s.w", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.w", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
> {"fcvt.s.wu", 0, INSN_CLASS_F, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> {"fcvt.s.wu", 0, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
> +{"fcvt.s.wu", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.wu", 0, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
> {"fclass.s", 0, INSN_CLASS_F, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
> +{"fclass.s", 0, INSN_CLASS_ZFINX, "d,s", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
> {"feq.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
> +{"feq.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
> {"flt.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"flt.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> {"fle.s", 0, INSN_CLASS_F, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fle.s", 0, INSN_CLASS_ZFINX, "d,s,t", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> {"fgt.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> +{"fgt.s", 0, INSN_CLASS_ZFINX, "d,t,s", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
> {"fge.s", 0, INSN_CLASS_F, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> +{"fge.s", 0, INSN_CLASS_ZFINX, "d,t,s", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
> {"fcvt.l.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
> {"fcvt.l.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
> +{"fcvt.l.s", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 },
> +{"fcvt.l.s", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
> {"fcvt.lu.s", 64, INSN_CLASS_F, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
> {"fcvt.lu.s", 64, INSN_CLASS_F, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.s", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
> {"fcvt.s.l", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> {"fcvt.s.l", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
> +{"fcvt.s.l", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.l", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
> {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
> {"fcvt.s.lu", 64, INSN_CLASS_F, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.lu", 64, INSN_CLASS_ZFINX, "d,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
>
> /* Double-precision floating-point instruction subset. */
> {"fld", 0, INSN_CLASS_D_AND_C, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
> @@ -592,55 +639,103 @@ const struct riscv_opcode riscv_opcodes[] =
> {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
> {"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
> {"fneg.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.d", 0, INSN_CLASS_ZDINX, "d,x", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
> {"fabs.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.d", 0, INSN_CLASS_ZDINX, "d,x", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
> {"fsgnj.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
> +{"fsgnj.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
> {"fsgnjn.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
> +{"fsgnjn.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
> {"fsgnjx.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
> +{"fsgnjx.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
> {"fadd.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
> {"fadd.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
> +{"fadd.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 },
> +{"fadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
> {"fsub.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
> {"fsub.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
> +{"fsub.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 },
> +{"fsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
> {"fmul.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
> {"fmul.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
> +{"fmul.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 },
> +{"fmul.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
> {"fdiv.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
> {"fdiv.d", 0, INSN_CLASS_D, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
> +{"fdiv.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 },
> +{"fdiv.d", 0, INSN_CLASS_ZDINX, "d,s,t,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
> {"fsqrt.d", 0, INSN_CLASS_D, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
> {"fsqrt.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
> +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 },
> +{"fsqrt.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
> {"fmin.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
> +{"fmin.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
> {"fmax.d", 0, INSN_CLASS_D, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
> +{"fmax.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
> {"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
> {"fmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
> +{"fmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 },
> +{"fmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
> {"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
> {"fnmadd.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
> +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 },
> +{"fnmadd.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
> {"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
> {"fmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
> +{"fmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 },
> +{"fmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
> {"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
> {"fnmsub.d", 0, INSN_CLASS_D, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
> +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 },
> +{"fnmsub.d", 0, INSN_CLASS_ZDINX, "d,s,t,r,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
> {"fcvt.w.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
> {"fcvt.w.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
> +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.w.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
> {"fcvt.wu.d", 0, INSN_CLASS_D, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
> {"fcvt.wu.d", 0, INSN_CLASS_D, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
> +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
> {"fcvt.d.w", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.w", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 },
> {"fcvt.d.wu", 0, INSN_CLASS_D, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.wu", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 },
> {"fcvt.d.s", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.s", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 },
> {"fcvt.s.d", 0, INSN_CLASS_D, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
> {"fcvt.s.d", 0, INSN_CLASS_D, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
> +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.s.d", 0, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
> {"fclass.d", 0, INSN_CLASS_D, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
> +{"fclass.d", 0, INSN_CLASS_ZDINX, "d,s", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
> {"feq.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
> +{"feq.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
> {"flt.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"flt.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> {"fle.d", 0, INSN_CLASS_D, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fle.d", 0, INSN_CLASS_ZDINX, "d,s,t", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> {"fgt.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> +{"fgt.d", 0, INSN_CLASS_ZDINX, "d,t,s", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
> {"fge.d", 0, INSN_CLASS_D, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> +{"fge.d", 0, INSN_CLASS_ZDINX, "d,t,s", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
> {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
> {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
> {"fcvt.l.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
> {"fcvt.l.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
> +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.l.d", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
> {"fcvt.lu.d", 64, INSN_CLASS_D, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
> {"fcvt.lu.d", 64, INSN_CLASS_D, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.d", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
> {"fcvt.d.l", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> {"fcvt.d.l", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
> +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.d.l", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
> {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
> {"fcvt.d.lu", 64, INSN_CLASS_D, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 },
> +{"fcvt.d.lu", 64, INSN_CLASS_ZDINX, "d,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
>
> /* Quad-precision floating-point instruction subset. */
> {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
> @@ -649,58 +744,109 @@ const struct riscv_opcode riscv_opcodes[] =
> {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
> {"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
> {"fneg.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fneg.q", 0, INSN_CLASS_ZQINX, "d,x", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> {"fabs.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> +{"fabs.q", 0, INSN_CLASS_ZQINX, "d,x", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> {"fsgnj.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> +{"fsgnj.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> {"fsgnjn.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> +{"fsgnjn.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> {"fsgnjx.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> +{"fsgnjx.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> {"fadd.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
> {"fadd.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> +{"fadd.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
> +{"fadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> {"fsub.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
> {"fsub.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> +{"fsub.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> {"fmul.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
> {"fmul.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> +{"fmul.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
> +{"fmul.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
> {"fdiv.q", 0, INSN_CLASS_Q, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> +{"fdiv.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
> +{"fdiv.q", 0, INSN_CLASS_ZQINX, "d,s,t,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> {"fsqrt.q", 0, INSN_CLASS_Q, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
> {"fsqrt.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
> +{"fsqrt.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> {"fmin.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> +{"fmin.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> {"fmax.q", 0, INSN_CLASS_Q, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> +{"fmax.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> {"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
> {"fmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> +{"fmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> {"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
> {"fnmadd.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
> +{"fnmadd.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> {"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
> {"fmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> +{"fmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> {"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
> {"fnmsub.q", 0, INSN_CLASS_Q, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
> +{"fnmsub.q", 0, INSN_CLASS_ZQINX, "d,s,t,r,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> {"fcvt.w.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.w.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.w.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> {"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.wu.q", 0, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.wu.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> {"fcvt.q.w", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.w", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> {"fcvt.q.wu", 0, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.wu", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> {"fcvt.q.s", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.s", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> {"fcvt.q.d", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.d", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> {"fcvt.s.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.s.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.s.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> {"fcvt.d.q", 0, INSN_CLASS_Q, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.d.q", 0, INSN_CLASS_Q, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.d.q", 0, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> {"fclass.q", 0, INSN_CLASS_Q, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> +{"fclass.q", 0, INSN_CLASS_ZQINX, "d,s", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> {"feq.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> +{"feq.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> {"flt.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"flt.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> {"fle.q", 0, INSN_CLASS_Q, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fle.q", 0, INSN_CLASS_ZQINX, "d,s,t", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> {"fgt.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> +{"fgt.q", 0, INSN_CLASS_ZQINX, "d,t,s", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> {"fge.q", 0, INSN_CLASS_Q, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> +{"fge.q", 0, INSN_CLASS_ZQINX, "d,t,s", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> {"fmv.x.q", 64, INSN_CLASS_Q, "d,S", MATCH_FMV_X_Q, MASK_FMV_X_Q, match_opcode, 0 },
> {"fmv.q.x", 64, INSN_CLASS_Q, "D,s", MATCH_FMV_Q_X, MASK_FMV_Q_X, match_opcode, 0 },
> {"fcvt.l.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.l.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.l.q", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> {"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> {"fcvt.lu.q", 64, INSN_CLASS_Q, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
> +{"fcvt.lu.q", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> {"fcvt.q.l", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> {"fcvt.q.l", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
> +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.l", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
> {"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> {"fcvt.q.lu", 64, INSN_CLASS_Q, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "d,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.lu", 64, INSN_CLASS_ZQINX, "d,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
>
> /* Compressed instructions. */
> {"c.unimp", 0, INSN_CLASS_C, "", 0, 0xffffU, match_opcode, 0 },
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] RISC-V: Add testcases and disassemble support for z[fdq]inx
2021-10-28 16:47 ` [PATCH 3/3] RISC-V: Add testcases and disassemble support " jiawei
@ 2021-11-09 10:03 ` Nelson Chu
0 siblings, 0 replies; 8+ messages in thread
From: Nelson Chu @ 2021-11-09 10:03 UTC (permalink / raw)
To: jiawei; +Cc: Binutils, tariq.kurd, cmuellner, Kito Cheng
Umm, adding a new flag in the elf header needs to change the riscv
psabi, but in fact we could try to get the information from the elf
architecture attribute. I have sent a patch to let dis-assembler can
access the elf attributes, and then parse the architecture string:
https://sourceware.org/pipermail/binutils/2021-November/118444.html
So that you can call "riscv_subset_supports (&riscv_rps_dis, "zfinx")"
to check if the zfinx extension is enable or not, and without adding
and checking the new elf header flag.
I will commit my patch in a few days, so please feel free to contact
me if you have any questions.
Thanks
Nelson
On Fri, Oct 29, 2021 at 12:50 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> binutils/readelf.c | 3 +++
> gas/config/tc-riscv.c | 15 ++++++++++++
> gas/testsuite/gas/riscv/zdinx.d | 41 +++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zdinx.s | 33 +++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zfinx.d | 39 ++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zfinx.s | 31 ++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zqinx.d | 43 +++++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zqinx.s | 35 +++++++++++++++++++++++++++
> include/elf/riscv.h | 3 +++
> opcodes/riscv-dis.c | 4 +++
> 10 files changed, 247 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zdinx.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx.s
> create mode 100644 gas/testsuite/gas/riscv/zfinx.d
> create mode 100644 gas/testsuite/gas/riscv/zfinx.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx.s
>
> diff --git a/binutils/readelf.c b/binutils/readelf.c
> index 682eacdef14..fc889c6c3ff 100644
> --- a/binutils/readelf.c
> +++ b/binutils/readelf.c
> @@ -3717,6 +3717,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
> if (e_flags & EF_RISCV_RVE)
> strcat (buf, ", RVE");
>
> + if (e_flags & EF_RISCV_ZFINX)
> + strcat (buf, ", ZFINX");
> +
> switch (e_flags & EF_RISCV_FLOAT_ABI)
> {
> case EF_RISCV_FLOAT_ABI_SOFT:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index b879bf1ea8b..ff279263ffb 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -204,6 +204,7 @@ struct riscv_set_options
> int pic; /* Generate position-independent code. */
> int rvc; /* Generate RVC code. */
> int rve; /* Generate RVE code. */
> + int zfinx; /* Generate ZFINX code. */
> int relax; /* Emit relocs the linker is allowed to relax. */
> int arch_attr; /* Emit architecture and privileged elf attributes. */
> int csr_check; /* Enable the CSR checking. */
> @@ -214,6 +215,7 @@ static struct riscv_set_options riscv_opts =
> 0, /* pic */
> 0, /* rvc */
> 0, /* rve */
> + 0, /* ZFINX */
> 1, /* relax */
> DEFAULT_RISCV_ATTR, /* arch_attr */
> 0, /* csr_check */
> @@ -234,6 +236,15 @@ riscv_set_rve (bool rve_value)
> riscv_opts.rve = rve_value;
> }
>
> +static void
> +riscv_set_zfinx (bool finx_value)
> +{
> + if (finx_value)
> + elf_flags |= EF_RISCV_ZFINX;
> +
> + riscv_opts.finx = finx_value;
> +}
> +
> static riscv_subset_list_t riscv_subsets;
>
> static bool
> @@ -328,6 +339,10 @@ riscv_set_arch (const char *s)
> riscv_set_rve (false);
> if (riscv_subset_supports ("e"))
> riscv_set_rve (true);
> + if (riscv_subset_supports ("zfinx")
> + || riscv_subset_supports ("zdinx")
> + || riscv_subset_supports ("zqinx"))
> + riscv_set_finx (true);
> }
>
> /* Indicate -mabi option is explictly set. */
> diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
> new file mode 100644
> index 00000000000..3e4c1a73388
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.d
> @@ -0,0 +1,41 @@
> +#as: -march=rv64ima_zdinx
> +#source: zdinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
> new file mode 100644
> index 00000000000..c427d982aaf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.s
> @@ -0,0 +1,33 @@
> +target:
> + fadd.d a0, a1, a2
> + fsub.d a0, a1, a2
> + fmul.d a0, a1, a2
> + fdiv.d a0, a1, a2
> + fsqrt.d a0, a0
> + fmin.d a0, a1, a2
> + fmax.d a0, a1, a2
> + fmadd.d a0, a1, a2, a3
> + fnmadd.d a0, a1, a2, a3
> + fmsub.d a0, a1, a2, a3
> + fnmsub.d a0, a1, a2, a3
> + fcvt.w.d a0, a1
> + fcvt.wu.d a0, a1
> + fcvt.l.d a0, a1
> + fcvt.lu.d a0, a1
> + fcvt.s.d a0, a1
> + fcvt.d.s a0, a1
> + fcvt.d.w a0, a1
> + fcvt.d.wu a0, a1
> + fcvt.d.l a0, a1
> + fcvt.d.lu a0, a1
> + fsgnj.d a0, a1, a2
> + fsgnjn.d a0, a1, a2
> + fsgnjx.d a0, a1, a2
> + feq.d a0, a1, a2
> + flt.d a0, a1, a2
> + fle.d a0, a1, a2
> + fgt.d a0, a1, a2
> + fge.d a0, a1, a2
> + fneg.d a0, a0
> + fabs.d a0, a0
> + fclass.d a0, a1
> diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
> new file mode 100644
> index 00000000000..d5499aa9131
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv64ima_zfinx
> +#source: zfinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c59553[ ]+flt.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
> new file mode 100644
> index 00000000000..af50490fadf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.s
> @@ -0,0 +1,31 @@
> +target:
> + fadd.s a0, a1, a2
> + fsub.s a0, a1, a2
> + fmul.s a0, a1, a2
> + fdiv.s a0, a1, a2
> + fsqrt.s a0, a0
> + fmin.s a0, a1, a2
> + fmax.s a0, a1, a2
> + fmadd.s a0, a1, a2, a3
> + fnmadd.s a0, a1, a2, a3
> + fmsub.s a0, a1, a2, a3
> + fnmsub.s a0, a1, a2, a3
> + fcvt.w.s a0, a1
> + fcvt.wu.s a0, a1
> + fcvt.l.s a0, a1
> + fcvt.lu.s a0, a1
> + fcvt.s.w a0, a1
> + fcvt.s.wu a0, a1
> + fcvt.s.l a0, a1
> + fcvt.s.lu a0, a1
> + fsgnj.s a0, a1, a2
> + fsgnjn.s a0, a1, a2
> + fsgnjx.s a0, a1, a2
> + feq.s a0, a1, a2
> + flt.s a0, a1, a2
> + fle.s a0, a1, a2
> + fgt.s a0, a1, a2
> + fge.s a0, a1, a2
> + fneg.s a0, a0
> + fabs.s a0, a0
> + fclass.s a0, a1
> diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
> new file mode 100644
> index 00000000000..a1c9eab4e1d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.d
> @@ -0,0 +1,43 @@
> +#as: -march=rv64ima_zqinx
> +#source: zqinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.d.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.q.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.q.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.q.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.q.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.q.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.q[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.q[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.q[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
> new file mode 100644
> index 00000000000..8372ba57c71
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.s
> @@ -0,0 +1,35 @@
> +target:
> + fadd.q a0, a1, a2
> + fsub.q a0, a1, a2
> + fmul.q a0, a1, a2
> + fdiv.q a0, a1, a2
> + fsqrt.q a0, a0
> + fmin.q a0, a1, a2
> + fmax.q a0, a1, a2
> + fmadd.q a0, a1, a2, a3
> + fnmadd.q a0, a1, a2, a3
> + fmsub.q a0, a1, a2, a3
> + fnmsub.q a0, a1, a2, a3
> + fcvt.w.q a0, a1
> + fcvt.wu.q a0, a1
> + fcvt.l.q a0, a1
> + fcvt.lu.q a0, a1
> + fcvt.s.q a0, a1
> + fcvt.d.q a0, a1
> + fcvt.q.s a0, a1
> + fcvt.q.d a0, a1
> + fcvt.q.w a0, a1
> + fcvt.q.wu a0, a1
> + fcvt.q.l a0, a1
> + fcvt.q.lu a0, a1
> + fsgnj.q a0, a1, a2
> + fsgnjn.q a0, a1, a2
> + fsgnjx.q a0, a1, a2
> + feq.q a0, a1, a2
> + flt.q a0, a1, a2
> + fle.q a0, a1, a2
> + fgt.q a0, a1, a2
> + fge.q a0, a1, a2
> + fneg.q a0, a0
> + fabs.q a0, a0
> + fclass.q a0, a1
> diff --git a/include/elf/riscv.h b/include/elf/riscv.h
> index 80822835cd9..a73623d315d 100644
> --- a/include/elf/riscv.h
> +++ b/include/elf/riscv.h
> @@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
> /* File uses the 32E base integer instruction. */
> #define EF_RISCV_RVE 0x0008
>
> +/* File uses the gpr base ZFINX instruction. */
> +#define EF_RISCV_ZFINX 0x0010
> +
> /* The name of the global pointer symbol. */
> #define RISCV_GP_SYMBOL "__global_pointer$"
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 2e28ba77e60..4bf640e6f53 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -513,6 +513,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
> xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
> }
>
> + /* If ELF has ZFINX flags, use gpr for disassemble. */
> + if ((ehdr->e_flags & EF_RISCV_ZFINX_ABI) == EF_RISCV_ZFINX_ABI)
> + riscv_fpr_names = riscv_gpr_names_abi;
> +
> for (; op->name; op++)
> {
> /* Does the opcode match? */
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/3] RISC-V: Zfinx extension support
2021-10-28 16:47 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
` (2 preceding siblings ...)
2021-10-28 16:47 ` [PATCH 3/3] RISC-V: Add testcases and disassemble support " jiawei
@ 2021-11-09 10:06 ` Nelson Chu
3 siblings, 0 replies; 8+ messages in thread
From: Nelson Chu @ 2021-11-09 10:06 UTC (permalink / raw)
To: jiawei; +Cc: Binutils, tariq.kurd, cmuellner, Kito Cheng
Hi Jiawei,
Thanks for implementing the zfinx support both in gcc and binutils :)
I have given some comments, so please see the details in the related
mails.
Thanks
Nelson
On Fri, Oct 29, 2021 at 12:48 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> This patch is support zfinx extension on binutils, zfinx is not compatible with any float extension and use gpr replace fpr, we adjust the opreand set when zfinx used. For disassemble part, we add a flag ZFINX(0x10) as ELF-header to distinguish whether use gpr or fpr name for float instructions.
>
> jiawei (3):
> RISC-V: Add mininal support for z[fdq]inx
> RISC-V: Add instructions and operand set for z[fdq]inx
> RISC-V: Add testcases and disassemble support for z[fdq]inx
>
> bfd/elfxx-riscv.c | 32 +++++++
> binutils/readelf.c | 3 +
> gas/config/tc-riscv.c | 33 +++++++-
> gas/testsuite/gas/riscv/zdinx.d | 41 +++++++++
> gas/testsuite/gas/riscv/zdinx.s | 33 ++++++++
> gas/testsuite/gas/riscv/zfinx.d | 39 +++++++++
> gas/testsuite/gas/riscv/zfinx.s | 31 +++++++
> gas/testsuite/gas/riscv/zqinx.d | 43 ++++++++++
> gas/testsuite/gas/riscv/zqinx.s | 35 ++++++++
> include/elf/riscv.h | 3 +
> include/opcode/riscv.h | 3 +
> opcodes/riscv-dis.c | 4 +
> opcodes/riscv-opc.c | 146 ++++++++++++++++++++++++++++++++
> 13 files changed, 443 insertions(+), 3 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/zdinx.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx.s
> create mode 100644 gas/testsuite/gas/riscv/zfinx.d
> create mode 100644 gas/testsuite/gas/riscv/zfinx.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx.s
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-11-09 10:06 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-28 16:47 [PATCH 0/3] RISC-V: Zfinx extension support jiawei
2021-10-28 16:47 ` [PATCH 1/3] RISC-V: Add mininal support for z[fdq]inx jiawei
2021-11-09 6:32 ` Nelson Chu
2021-10-28 16:47 ` [PATCH 2/3] RISC-V: Add instructions and operand set " jiawei
2021-11-09 9:51 ` Nelson Chu
2021-10-28 16:47 ` [PATCH 3/3] RISC-V: Add testcases and disassemble support " jiawei
2021-11-09 10:03 ` Nelson Chu
2021-11-09 10:06 ` [PATCH 0/3] RISC-V: Zfinx extension support Nelson Chu
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