From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vk1-xa32.google.com (mail-vk1-xa32.google.com [IPv6:2607:f8b0:4864:20::a32]) by sourceware.org (Postfix) with ESMTPS id 729DF3858414 for ; Fri, 25 Feb 2022 09:08:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 729DF3858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-vk1-xa32.google.com with SMTP id l42so1226804vkd.7 for ; Fri, 25 Feb 2022 01:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LjWoK36eTfc9sos9ig+bCrPQIuCMqCkF1MktqvlYDVQ=; b=aPzIzq2VC8+qjqAHeKeC0Qjry3DXayxyhbbRVBapvW7sqUauNR6u4M/GAczntkSxdr YKlIA1F3YUtnTq9hf0IkoGYn4kul7Yl/fK8GhRNh4NENtpgnEaE0tixDxhcEl4+ECLAX AH+bQHdjF4qVQj1ugICt8FU0hMTq7f+mXFIQtWp/kE9aOwSpV38O09SLUe3ffFMnvuh/ aKUzuqJn8FsYRnDHJ7gCV1bDclIPs6/SJVEPSixkBd/rtVjq88BtVPu85DuatyWjcmtS /CdMhphFQS5OgaBTiOgeCDIPWOGSik1dcFZ6Ro1yjFW4uksJ+e7kTl7QBkt30aDXrOJO RK+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LjWoK36eTfc9sos9ig+bCrPQIuCMqCkF1MktqvlYDVQ=; b=32fJkB0aVODEi+XJDg0qqSIA5x0h9YKWHjUYgd1Z0CT4Y9+g6UUIAyfjYk9x1L6qGm vjqOX5Qp93ZmSNwlZXHIuyKoHbzMI93yizOGnvMdCFVT7W3RF9V3S8DWN/nY2j2VPho3 dNTv45/XGYxRewN8bG+5tcXIpNzRXA9crUxEJWGp7jRE+XoDD1FQ7c7Z+Hv5bfOmSUuH RKs+4tNex62Us2qaCOunYvET6yMuJQJEqgj/tfA+HPsQeuS1vjfxLOXAE1gnZ9v1cYo8 XdjsdCJBdqjiuhcstNVdV9O9SeDikbm8JbpTNChAAO7HdjPUmpR2PZY3gPNyCCb17g7R iBYA== X-Gm-Message-State: AOAM531U/mtCgDSi4JvixK4OFcvwdeSmZclnk4d1PG6enaER2v+1LRi6 ZtCOmSl5nfyYsTCVBzo4GFEzrux/1B+PQ+BWN7cbTL5Vy94= X-Google-Smtp-Source: ABdhPJzsGuIxjAXqEBbibsyXxnaVO44clWtUAtJj8D7AmYk8x9IU63mlgni6BcU4c+KfdlDhOnwUPdm0S5ovYe/0iZg= X-Received: by 2002:a05:6122:9a9:b0:331:6ff8:c190 with SMTP id g41-20020a05612209a900b003316ff8c190mr3091562vkd.23.1645780137978; Fri, 25 Feb 2022 01:08:57 -0800 (PST) MIME-Version: 1.0 References: <3ab20eb4c065dc1e5a976dccc593a2c9a6ab853f.1641802855.git.research_trasio@irq.a4lg.com> In-Reply-To: From: Nelson Chu Date: Fri, 25 Feb 2022 17:08:47 +0800 Message-ID: Subject: Re: [PATCH 1/1] RISC-V: Fix mask for some fcvt instructions To: Andrew Waterman Cc: Tsukasa OI , Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Feb 2022 09:09:00 -0000 Committed, thanks. Nelson On Tue, Jan 11, 2022 at 7:56 AM Andrew Waterman wrote: > > LGTM. Thanks. > > On Mon, Jan 10, 2022 at 12:23 AM Tsukasa OI via Binutils > wrote: > > > > This commit fixes incorrect uses of mask values in 'fcvt' instruction > > family. > > > > opcodes/ChangeLog: > > > > * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values > > in 'fcvt' instruction family. > > --- > > opcodes/riscv-opc.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index 2da0f7cf0a4..00ee21d783f 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -630,7 +630,7 @@ const struct riscv_opcode riscv_opcodes[] = > > {"fcvt.wu.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, > > {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, > > {"fcvt.s.w", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, > > -{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, > > +{"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, > > {"fcvt.s.wu", 0, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, > > {"fclass.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, > > {"feq.s", 0, INSN_CLASS_F_OR_ZFINX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, > > @@ -644,7 +644,7 @@ const struct riscv_opcode riscv_opcodes[] = > > {"fcvt.lu.s", 64, INSN_CLASS_F_OR_ZFINX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, > > {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, > > {"fcvt.s.l", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, > > -{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, > > +{"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.s.lu", 64, INSN_CLASS_F_OR_ZFINX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, > > > > /* Double-precision floating-point instruction subset. */ > > @@ -705,7 +705,7 @@ const struct riscv_opcode riscv_opcodes[] = > > {"fcvt.lu.d", 64, INSN_CLASS_D_OR_ZDINX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, > > {"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, > > {"fcvt.d.l", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, > > -{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, > > +{"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.d.lu", 64, INSN_CLASS_D_OR_ZDINX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, > > > > /* Quad-precision floating-point instruction subset. */ > > @@ -765,7 +765,7 @@ const struct riscv_opcode riscv_opcodes[] = > > {"fcvt.lu.q", 64, INSN_CLASS_Q_OR_ZQINX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, > > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_L|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > > {"fcvt.q.l", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, > > -{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, > > +{"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s", MATCH_FCVT_Q_LU|MASK_RM, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, > > {"fcvt.q.lu", 64, INSN_CLASS_Q_OR_ZQINX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, > > > > /* Compressed instructions. */ > > -- > > 2.32.0 > >