From: Nelson Chu <nelson.chu@sifive.com>
To: Andrew Waterman <andrew@sifive.com>
Cc: Binutils <binutils@sourceware.org>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Craig topper <craig.topper@sifive.com>
Subject: Re: [PATCH] RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.
Date: Tue, 30 Nov 2021 15:15:17 +0800 [thread overview]
Message-ID: <CAJYME4EoqQyGNrhWw-8DPc8PxNWK4Y5ZkMPKdZcJ6eJHh6t0Mg@mail.gmail.com> (raw)
In-Reply-To: <CA++6G0BB=xmU0GO_ysWV4VfTG60Z4WGCiNm2CSJKTVUJ1JPW3g@mail.gmail.com>
Thanks, committed.
Nelson
On Tue, Nov 30, 2021 at 3:12 PM Andrew Waterman <andrew@sifive.com> wrote:
>
> LGTM. Thanks, Nelson.
>
> Andrew
>
>
> On Mon, Nov 29, 2021 at 9:43 PM Nelson Chu <nelson.chu@sifive.com> wrote:
> >
> > Consider the following case,
> >
> > vsetvli a0, a1, 0x4 # unrecognized vlmul
> > vsetvli a0, a1, 0x20 # unrecognized vsew
> > vsetivli a0, 0xb, 0x4 # unrecognized vlmul
> > vsetivli a0, 0xb, 0x20 # unrecognized vsew
> >
> > For the current dis-assembler, we get the result,
> >
> > 0000000000000000 <.text>:
> > 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu
> > 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu
> > 8: c045f557 vsetivli a0,11,e8,(null),tu,mu
> > c: c205f557 vsetivli a0,11,e128,m1,tu,mu
> >
> > The vsew e128 and vlmul (null) are preserved according to the spec,
> > so dump these fields looks wrong. Consider that we are used to dump
> > the unrecognized csr as csr numbers directly, we should also dump
> > the whole vset[i]vli immediates as numbers, once the vsew or vlmul
> > is reserved. Therefore, following is what I expected,
> >
> > 0000000000000000 <.text>:
> > 0: 0045f557 vsetvli a0,a1,4
> > 4: 0205f557 vsetvli a0,a1,32
> > 8: c045f557 vsetivli a0,11,4
> > c: c205f557 vsetivli a0,11,32
> >
> > gas/
> > * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli
> > testcases since we should dump the immediate as numbers once
> > the vsew or vlmul is reserved.
> > * testsuite/gas/riscv/vector-insns.s: Likewise.
> > opcodes/
> > * riscv-dis.c (print_insn_args): The reserved vsew and vlmul
> > are NULL string in the riscv_vsew and riscv_vlmul, so dump the
> > whole imm as numbers once one of them is NULL.
> > * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL.
> > (riscv_vlmul): Set the reserved vlmul to NULL.
> > ---
> > gas/testsuite/gas/riscv/vector-insns.d | 46 +++++++++----------------------
> > gas/testsuite/gas/riscv/vector-insns.s | 50 ++++++++++------------------------
> > opcodes/riscv-dis.c | 4 ++-
> > opcodes/riscv-opc.c | 4 +--
> > 4 files changed, 33 insertions(+), 71 deletions(-)
> >
> > diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d
> > index 711f927..6325c74 100644
> > --- a/gas/testsuite/gas/riscv/vector-insns.d
> > +++ b/gas/testsuite/gas/riscv/vector-insns.d
> > @@ -10,40 +10,20 @@ Disassembly of section .text:
> > [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2
> > [ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu
> > [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047
> > -[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
> > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
> > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma
> > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma
> > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu
> > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4
> > +[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32
> > +[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu
> > +[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma
> > [ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma
> > -[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
> > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
> > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
> > -[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma
> > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma
> > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu
> > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023
> > +[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4
> > +[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32
> > +[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu
> > +[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu
> > +[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma
> > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
> > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
> > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\)
> > diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s
> > index 37b6ba4..8370264 100644
> > --- a/gas/testsuite/gas/riscv/vector-insns.s
> > +++ b/gas/testsuite/gas/riscv/vector-insns.s
> > @@ -1,40 +1,20 @@
> > - vsetvl a0, a1, a2
> > - vsetvli a0, a1, 0
> > - vsetvli a0, a1, 0x7ff
> > - vsetvli a0, a1, e16, m2
> > - vsetvli a0, a1, e256, m8
> > - vsetvli a0, a1, e512, m8
> > - vsetvli a0, a1, e1024, m8
> > - vsetvli a0, a1, e1024, m1
> > - vsetvli a0, a1, e1024, mf2
> > - vsetvli a0, a1, e512, mf4
> > - vsetvli a0, a1, e256, mf8
> > - vsetvli a0, a1, e256, m2, ta
> > - vsetvli a0, a1, e256, m2, ma
> > - vsetvli a0, a1, e256, m2, tu
> > - vsetvli a0, a1, e256, m2, mu
> > - vsetvli a0, a1, e256, m2, ta, ma
> > - vsetvli a0, a1, e256, m2, tu, ma
> > - vsetvli a0, a1, e256, m2, ta, mu
> > - vsetvli a0, a1, e256, m2, tu, mu
> > + vsetvl a0, a1, a2
> > + vsetvli a0, a1, 0
> > + vsetvli a0, a1, 0x7ff
> > + vsetvli a0, a1, 0x4 # unrecognized vlmul
> > + vsetvli a0, a1, 0x20 # unrecognized vsew
> > + vsetvli a0, a1, e8, m2
> > + vsetvli a0, a1, e16, m4, ta
> > + vsetvli a0, a1, e32, mf4, mu
> > + vsetvli a0, a1, e64, mf8, tu, ma
> > vsetivli a0, 0xb, 0
> > vsetivli a0, 0xb, 0x3ff
> > - vsetivli a0, 0xb, e16, m2
> > - vsetivli a0, 0xb, e256, m8
> > - vsetivli a0, 0xb, e512, m8
> > - vsetivli a0, 0xb, e1024, m8
> > - vsetivli a0, 0xb, e1024, m1
> > - vsetivli a0, 0xb, e1024, mf2
> > - vsetivli a0, 0xb, e512, mf4
> > - vsetivli a0, 0xb, e256, mf8
> > - vsetivli a0, 0xb, e256, m2, ta
> > - vsetivli a0, 0xb, e256, m2, ma
> > - vsetivli a0, 0xb, e256, m2, tu
> > - vsetivli a0, 0xb, e256, m2, mu
> > - vsetivli a0, 0xb, e256, m2, ta, ma
> > - vsetivli a0, 0xb, e256, m2, tu, ma
> > - vsetivli a0, 0xb, e256, m2, ta, mu
> > - vsetivli a0, 0xb, e256, m2, tu, mu
> > + vsetivli a0, 0xb, 0x4 # unrecognized vlmul
> > + vsetivli a0, 0xb, 0x20 # unrecognized vsew
> > + vsetivli a0, 0xb, e8, m2
> > + vsetivli a0, 0xb, e16, m4, ta
> > + vsetivli a0, 0xb, e32, mf4, mu
> > + vsetivli a0, 0xb, e64, mf8, tu, ma
> >
> > vlm.v v4, (a0)
> > vlm.v v4, 0(a0)
> > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> > index 18e498a..a3c8506 100644
> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -334,7 +334,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> > && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
> > && imm_vta < ARRAY_SIZE (riscv_vta)
> > && imm_vma < ARRAY_SIZE (riscv_vma)
> > - && !imm_vtype_res)
> > + && !imm_vtype_res
> > + && riscv_vsew[imm_vsew] != NULL
> > + && riscv_vlmul[imm_vlmul] != NULL)
> > print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew],
> > riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
> > riscv_vma[imm_vma]);
> > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> > index bad77fb..40037db 100644
> > --- a/opcodes/riscv-opc.c
> > +++ b/opcodes/riscv-opc.c
> > @@ -76,13 +76,13 @@ const char * const riscv_vecm_names_numeric[NVECM] =
> > /* The vsetvli vsew constants. */
> > const char * const riscv_vsew[8] =
> > {
> > - "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024"
> > + "e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL
> > };
> >
> > /* The vsetvli vlmul constants. */
> > const char * const riscv_vlmul[8] =
> > {
> > - "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2"
> > + "m1", "m2", "m4", "m8", NULL, "mf8", "mf4", "mf2"
> > };
> >
> > /* The vsetvli vta constants. */
> > --
> > 2.7.4
> >
prev parent reply other threads:[~2021-11-30 7:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 5:43 Nelson Chu
2021-11-30 7:12 ` Andrew Waterman
2021-11-30 7:15 ` Nelson Chu [this message]
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