From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x92f.google.com (mail-ua1-x92f.google.com [IPv6:2607:f8b0:4864:20::92f]) by sourceware.org (Postfix) with ESMTPS id 7C5B13858409 for ; Tue, 30 Nov 2021 07:15:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7C5B13858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-ua1-x92f.google.com with SMTP id p37so39412564uae.8 for ; Mon, 29 Nov 2021 23:15:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BfPnKqM74YtkdTsjwBW2e3oRfUXK4oj5sKujsSqXKzs=; b=asqpEkVCmfrFQ1m+0qQceOf2XVoT8orpj3sqbGz470W5yagQ4Or9OYunMZUdpvxZe2 Aa9mi+tgEP83PZIfzI3nYLJ99GoL3wYT7mZrcXhOnm4PTwft+BvkruICGHM/jSHCVO3W zfbVTiOdtrpqd2oCXx+KuJpMaF4ystujKqtVgH+PctFNAhEGujOYtc56Yd4m1QC2JiHx b6HUdcBpqC0KJmaSVTx5TFmBiEgdkPazS0246YqZhWH2bwf1ooT3JH1FoBl8NMab9phK FkO+9CEMf45hfcNH2vYL2wWMtQFzIzrGsXWZLmKQCChT0DESh5XoK0IrxyKQSykyFeW3 j3hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BfPnKqM74YtkdTsjwBW2e3oRfUXK4oj5sKujsSqXKzs=; b=NmwTc0g9H1YUVQ6YBeyDJx6T/Xp8vaUM8P1h5QbK67JS9YbxzmJcyjajrhf+sFt7Fw GJNlTfdIU4m0nCFQNSePk9meBRr35HXFr6da8KeLEs5ZAy8519hOCeBGl4+SeV/srMV7 TVcf8taS6n9TgFWA24jdQLn96VV45JaqUfITDvFAXcTNJXNXpZShU66lssXoyAVx/e3T xcL/y1f55p0LqoEAnMnAMssWT3qNy4ZUp4uYLt2wjYMzE/cu3VErigJFhPdJa8addjpT 3E5Q+QzNwwmwja/Tl35TB9u8+77xfFwXMX7B9wR3q7gdb8ZBCvsg1/6qtT5mrz+9Ey2a Xm8w== X-Gm-Message-State: AOAM530m8ve7T06jQQY9ZAuN5r9lba95pV5te+3A+beUOAyUGB3vTG/p Aiejv0dFXScX0rAIz1J0BUCupC/z+OC01ypLzLUuzA== X-Google-Smtp-Source: ABdhPJx9S3JMthfEYV9Y5QkfOkdAi0ATuv4uncy+liiMtRbLJGQuhIIHUEcdZWuOKetDEhmh+TnrXFZb5SGlmIdd+GM= X-Received: by 2002:a67:e054:: with SMTP id n20mr39073862vsl.83.1638256527989; Mon, 29 Nov 2021 23:15:27 -0800 (PST) MIME-Version: 1.0 References: <1638250994-21268-1-git-send-email-nelson.chu@sifive.com> In-Reply-To: From: Nelson Chu Date: Tue, 30 Nov 2021 15:15:17 +0800 Message-ID: Subject: Re: [PATCH] RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved. To: Andrew Waterman Cc: Binutils , Jim Wilson , Craig topper Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 30 Nov 2021 07:15:30 -0000 Thanks, committed. Nelson On Tue, Nov 30, 2021 at 3:12 PM Andrew Waterman wrote: > > LGTM. Thanks, Nelson. > > Andrew > > > On Mon, Nov 29, 2021 at 9:43 PM Nelson Chu wrote: > > > > Consider the following case, > > > > vsetvli a0, a1, 0x4 # unrecognized vlmul > > vsetvli a0, a1, 0x20 # unrecognized vsew > > vsetivli a0, 0xb, 0x4 # unrecognized vlmul > > vsetivli a0, 0xb, 0x20 # unrecognized vsew > > > > For the current dis-assembler, we get the result, > > > > 0000000000000000 <.text>: > > 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu > > 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu > > 8: c045f557 vsetivli a0,11,e8,(null),tu,mu > > c: c205f557 vsetivli a0,11,e128,m1,tu,mu > > > > The vsew e128 and vlmul (null) are preserved according to the spec, > > so dump these fields looks wrong. Consider that we are used to dump > > the unrecognized csr as csr numbers directly, we should also dump > > the whole vset[i]vli immediates as numbers, once the vsew or vlmul > > is reserved. Therefore, following is what I expected, > > > > 0000000000000000 <.text>: > > 0: 0045f557 vsetvli a0,a1,4 > > 4: 0205f557 vsetvli a0,a1,32 > > 8: c045f557 vsetivli a0,11,4 > > c: c205f557 vsetivli a0,11,32 > > > > gas/ > > * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli > > testcases since we should dump the immediate as numbers once > > the vsew or vlmul is reserved. > > * testsuite/gas/riscv/vector-insns.s: Likewise. > > opcodes/ > > * riscv-dis.c (print_insn_args): The reserved vsew and vlmul > > are NULL string in the riscv_vsew and riscv_vlmul, so dump the > > whole imm as numbers once one of them is NULL. > > * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. > > (riscv_vlmul): Set the reserved vlmul to NULL. > > --- > > gas/testsuite/gas/riscv/vector-insns.d | 46 +++++++++---------------------- > > gas/testsuite/gas/riscv/vector-insns.s | 50 ++++++++++------------------------ > > opcodes/riscv-dis.c | 4 ++- > > opcodes/riscv-opc.c | 4 +-- > > 4 files changed, 33 insertions(+), 71 deletions(-) > > > > diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d > > index 711f927..6325c74 100644 > > --- a/gas/testsuite/gas/riscv/vector-insns.d > > +++ b/gas/testsuite/gas/riscv/vector-insns.d > > @@ -10,40 +10,20 @@ Disassembly of section .text: > > [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2 > > [ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu > > [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047 > > -[ ]+[0-9a-f]+:[ ]+0095f557[ ]+vsetvli[ ]+a0,a1,e16,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+02b5f557[ ]+vsetvli[ ]+a0,a1,e256,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0335f557[ ]+vsetvli[ ]+a0,a1,e512,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+03b5f557[ ]+vsetvli[ ]+a0,a1,e1024,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0385f557[ ]+vsetvli[ ]+a0,a1,e1024,m1,tu,mu > > -[ ]+[0-9a-f]+:[ ]+03f5f557[ ]+vsetvli[ ]+a0,a1,e1024,mf2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0365f557[ ]+vsetvli[ ]+a0,a1,e512,mf4,tu,mu > > -[ ]+[0-9a-f]+:[ ]+02d5f557[ ]+vsetvli[ ]+a0,a1,e256,mf8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu > > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma > > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+0e95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,ma > > -[ ]+[0-9a-f]+:[ ]+0a95f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,ma > > -[ ]+[0-9a-f]+:[ ]+0695f557[ ]+vsetvli[ ]+a0,a1,e256,m2,ta,mu > > -[ ]+[0-9a-f]+:[ ]+0295f557[ ]+vsetvli[ ]+a0,a1,e256,m2,tu,mu > > +[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4 > > +[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32 > > +[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu > > +[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu > > +[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu > > +[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma > > [ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu > > -[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,ta,ma > > -[ ]+[0-9a-f]+:[ ]+c095f557[ ]+vsetivli[ ]+a0,11,e16,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c2b5f557[ ]+vsetivli[ ]+a0,11,e256,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c335f557[ ]+vsetivli[ ]+a0,11,e512,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c3b5f557[ ]+vsetivli[ ]+a0,11,e1024,m8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c385f557[ ]+vsetivli[ ]+a0,11,e1024,m1,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c3f5f557[ ]+vsetivli[ ]+a0,11,e1024,mf2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c365f557[ ]+vsetivli[ ]+a0,11,e512,mf4,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c2d5f557[ ]+vsetivli[ ]+a0,11,e256,mf8,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu > > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma > > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > > -[ ]+[0-9a-f]+:[ ]+ce95f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,ma > > -[ ]+[0-9a-f]+:[ ]+ca95f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,ma > > -[ ]+[0-9a-f]+:[ ]+c695f557[ ]+vsetivli[ ]+a0,11,e256,m2,ta,mu > > -[ ]+[0-9a-f]+:[ ]+c295f557[ ]+vsetivli[ ]+a0,11,e256,m2,tu,mu > > +[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023 > > +[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4 > > +[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32 > > +[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu > > +[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu > > +[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu > > +[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma > > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > > [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) > > diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s > > index 37b6ba4..8370264 100644 > > --- a/gas/testsuite/gas/riscv/vector-insns.s > > +++ b/gas/testsuite/gas/riscv/vector-insns.s > > @@ -1,40 +1,20 @@ > > - vsetvl a0, a1, a2 > > - vsetvli a0, a1, 0 > > - vsetvli a0, a1, 0x7ff > > - vsetvli a0, a1, e16, m2 > > - vsetvli a0, a1, e256, m8 > > - vsetvli a0, a1, e512, m8 > > - vsetvli a0, a1, e1024, m8 > > - vsetvli a0, a1, e1024, m1 > > - vsetvli a0, a1, e1024, mf2 > > - vsetvli a0, a1, e512, mf4 > > - vsetvli a0, a1, e256, mf8 > > - vsetvli a0, a1, e256, m2, ta > > - vsetvli a0, a1, e256, m2, ma > > - vsetvli a0, a1, e256, m2, tu > > - vsetvli a0, a1, e256, m2, mu > > - vsetvli a0, a1, e256, m2, ta, ma > > - vsetvli a0, a1, e256, m2, tu, ma > > - vsetvli a0, a1, e256, m2, ta, mu > > - vsetvli a0, a1, e256, m2, tu, mu > > + vsetvl a0, a1, a2 > > + vsetvli a0, a1, 0 > > + vsetvli a0, a1, 0x7ff > > + vsetvli a0, a1, 0x4 # unrecognized vlmul > > + vsetvli a0, a1, 0x20 # unrecognized vsew > > + vsetvli a0, a1, e8, m2 > > + vsetvli a0, a1, e16, m4, ta > > + vsetvli a0, a1, e32, mf4, mu > > + vsetvli a0, a1, e64, mf8, tu, ma > > vsetivli a0, 0xb, 0 > > vsetivli a0, 0xb, 0x3ff > > - vsetivli a0, 0xb, e16, m2 > > - vsetivli a0, 0xb, e256, m8 > > - vsetivli a0, 0xb, e512, m8 > > - vsetivli a0, 0xb, e1024, m8 > > - vsetivli a0, 0xb, e1024, m1 > > - vsetivli a0, 0xb, e1024, mf2 > > - vsetivli a0, 0xb, e512, mf4 > > - vsetivli a0, 0xb, e256, mf8 > > - vsetivli a0, 0xb, e256, m2, ta > > - vsetivli a0, 0xb, e256, m2, ma > > - vsetivli a0, 0xb, e256, m2, tu > > - vsetivli a0, 0xb, e256, m2, mu > > - vsetivli a0, 0xb, e256, m2, ta, ma > > - vsetivli a0, 0xb, e256, m2, tu, ma > > - vsetivli a0, 0xb, e256, m2, ta, mu > > - vsetivli a0, 0xb, e256, m2, tu, mu > > + vsetivli a0, 0xb, 0x4 # unrecognized vlmul > > + vsetivli a0, 0xb, 0x20 # unrecognized vsew > > + vsetivli a0, 0xb, e8, m2 > > + vsetivli a0, 0xb, e16, m4, ta > > + vsetivli a0, 0xb, e32, mf4, mu > > + vsetivli a0, 0xb, e64, mf8, tu, ma > > > > vlm.v v4, (a0) > > vlm.v v4, 0(a0) > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > > index 18e498a..a3c8506 100644 > > --- a/opcodes/riscv-dis.c > > +++ b/opcodes/riscv-dis.c > > @@ -334,7 +334,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > > && imm_vlmul < ARRAY_SIZE (riscv_vlmul) > > && imm_vta < ARRAY_SIZE (riscv_vta) > > && imm_vma < ARRAY_SIZE (riscv_vma) > > - && !imm_vtype_res) > > + && !imm_vtype_res > > + && riscv_vsew[imm_vsew] != NULL > > + && riscv_vlmul[imm_vlmul] != NULL) > > print (info->stream, "%s,%s,%s,%s", riscv_vsew[imm_vsew], > > riscv_vlmul[imm_vlmul], riscv_vta[imm_vta], > > riscv_vma[imm_vma]); > > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > > index bad77fb..40037db 100644 > > --- a/opcodes/riscv-opc.c > > +++ b/opcodes/riscv-opc.c > > @@ -76,13 +76,13 @@ const char * const riscv_vecm_names_numeric[NVECM] = > > /* The vsetvli vsew constants. */ > > const char * const riscv_vsew[8] = > > { > > - "e8", "e16", "e32", "e64", "e128", "e256", "e512", "e1024" > > + "e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL > > }; > > > > /* The vsetvli vlmul constants. */ > > const char * const riscv_vlmul[8] = > > { > > - "m1", "m2", "m4", "m8", 0, "mf8", "mf4", "mf2" > > + "m1", "m2", "m4", "m8", NULL, "mf8", "mf4", "mf2" > > }; > > > > /* The vsetvli vta constants. */ > > -- > > 2.7.4 > >