From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ua1-x933.google.com (mail-ua1-x933.google.com [IPv6:2607:f8b0:4864:20::933]) by sourceware.org (Postfix) with ESMTPS id A6E3F3858D28 for ; Fri, 17 Dec 2021 15:15:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A6E3F3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-ua1-x933.google.com with SMTP id u40so4980096uad.1 for ; Fri, 17 Dec 2021 07:15:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZZnHKe+V9Y6vZUJ/nDTnlevkqwJL1b3GjpoNG9lvwDU=; b=LZUDzYgKDiCRqiR9g/L4CWnbBN0SkcnjtqJIByI5s28E0aP9VeF4qdEK2JHJpebD5k E9ruZ5gs+qQRcgyoHDaibFCaVGOXa4QUWj7dRP2DxeKzxQ1bJW+zoU6UIdAQqUqtJBEm n4k//cgyeHL+6wSfUONqw4Y4DXRrGbewL3mRNkGVPnOTERHS8Es3ghXY1+RCxyWuhIdJ q6THfg8bp+ZdxTNzcwxoXpOEOpAChfI4oorwrghz+/zn43i5aNWY0W3UJqaXKPkyBram eOaedJDG0eRD11kbCzpAWcxBAETeU3jIGVfq62HMFrn+078Z6B0L7Iu45VjZvQB5msiX R0QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZZnHKe+V9Y6vZUJ/nDTnlevkqwJL1b3GjpoNG9lvwDU=; b=eb2LoqYz+8sBBLsg43fvEYwdNOcVUN8QMBhPM91Pi1ydQCmywle31SBL1PGhUwBPzB W1taOmymF2YFuAWKFdgwthUYEx68Lo/LLZqmlITCGtBxrFq1wG92FMeJOFULmihVkr8H U0SaEVgRIU/ejjlD1smIrGkEKfQ7407KlKDERJ3uZfQ6VF1byQc+9DASOPPUDlaSyayC lU7XgTyawlK9Z4Ogwcwha57KLhLw9LgzZc2npj9GJPJeFsgm80oL8gnDmoq+La4OJVbS RJ1Qd1XUiqUTHSYogfBDbyXzTt3hdvqms74B0zB1ZpL+PSUKoT3TBx3m6TqbhHI3yqXC WEbQ== X-Gm-Message-State: AOAM533rJ+yAHsxjA57pa7e0+u5f3AVbuFJCIGZvnU2eOrnMvG1qa2ap ZSSImWH4qcK1NO1GN/4F1k61Xjysd2OXJM7n+uTYKbAPfjJ9PQ== X-Google-Smtp-Source: ABdhPJz9Nj7NZUyyzXbyF3/eu1MicKMpD3qryfBHrHcY4LCnkdHAHdqGZvSbEtIGLb0kdYA6qZJ5yVO5dursFWaeVQM= X-Received: by 2002:a05:6102:3f50:: with SMTP id l16mr1296067vsv.85.1639754132097; Fri, 17 Dec 2021 07:15:32 -0800 (PST) MIME-Version: 1.0 References: <70be855026cd8ee3d64298325b77737441c013ac.1639652695.git.research_trasio@irq.a4lg.com> In-Reply-To: <70be855026cd8ee3d64298325b77737441c013ac.1639652695.git.research_trasio@irq.a4lg.com> From: Nelson Chu Date: Fri, 17 Dec 2021 23:15:21 +0800 Message-ID: Subject: Re: [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set To: Tsukasa OI Cc: Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Dec 2021 15:15:34 -0000 Hi Tsukasa, On Thu, Dec 16, 2021 at 7:11 PM Tsukasa OI via Binutils wrote: > > This commit adds Zicbop hint instructions. > > bfd/ChangeLog: > > * elfxx-riscv.c (riscv_multi_subset_supports): Add probing for > new instruction class. > > gas/ChangeLog: > > * config/tc-riscv.c (riscv_ip): Add handling for new operand > type 'f' (32-byte aligned pseudo S-type immediate for prefetch > hints). > (validate_riscv_insn): Likewise. > > include/ChangeLog: > > * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, > MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, > MASK_PREFETCH_W): New macros. > * opcode/riscv.h (enum riscv_insn_class): Add new instruction > class INSN_CLASS_ZICBOP. > > opcodes/ChangeLog: > > * riscv-dis.c (print_insn_args): Add handling for new operand > type. > * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions. > --- > bfd/elfxx-riscv.c | 2 ++ > gas/config/tc-riscv.c | 17 +++++++++++++++++ > include/opcode/riscv-opc.h | 6 ++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-dis.c | 4 ++++ > opcodes/riscv-opc.c | 3 +++ > 6 files changed, 33 insertions(+) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index a0a043cb5a8..2efc621fa07 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -2334,6 +2334,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > return riscv_subset_supports (rps, "i"); > case INSN_CLASS_ZICBOM: > return riscv_subset_supports (rps, "zicbom"); > + case INSN_CLASS_ZICBOP: > + return riscv_subset_supports (rps, "zicbop"); > case INSN_CLASS_ZICBOZ: > return riscv_subset_supports (rps, "zicboz"); > case INSN_CLASS_ZICSR: > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index e8061217e7c..4bb5b767140 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -1160,6 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) > case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; > case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; > case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; > + case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break; > case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; > case 'z': break; /* Zero immediate. */ > case '[': break; /* Unused operand. */ > @@ -3163,6 +3164,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, > imm_expr->X_op = O_absent; > continue; > > + case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ > + if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) > + continue; > + my_getExpression (imm_expr, asarg); > + check_absolute_expr (ip, imm_expr, false); > + if (((unsigned) (imm_expr->X_add_number) & 0x1f) > + || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 > + || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) > + as_bad (_("improper prefetch offset (%ld)"), > + (long) imm_expr->X_add_number); > + ip->insn_opcode |= ENCODE_STYPE_IMM (imm_expr->X_add_number); > + ip->insn_opcode &= ~ ENCODE_STYPE_IMM (0x1fU); At first I felt we didn't need this line since we should already make sure the 0-4 bits are zero of the immediate, which means the immediate is a multiple of 32. But if I remove this line, then I will get multiple extra illegal operand errors, which seems redundant... So I spend some time, and notice that the redundant operand errors are generated because we will call insn->match_func later. Therefore, masking the low 0-4 bits will let the errors look more clean. So LGTM. > + imm_expr->X_op = O_absent; > + asarg = expr_end; > + continue; > + > default: > unknown_riscv_ip_operand: > as_fatal (_("internal: unknown argument type `%s'"), > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index c804c1afd95..ccd33ed4278 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2006,6 +2006,12 @@ > #define MASK_CBO_INVAL 0xfff07fff > #define MATCH_CBO_ZERO 0x40200f > #define MASK_CBO_ZERO 0xfff07fff > +#define MATCH_PREFETCH_I 0x6013 > +#define MASK_PREFETCH_I 0x1f07fff > +#define MATCH_PREFETCH_R 0x106013 > +#define MASK_PREFETCH_R 0x1f07fff > +#define MATCH_PREFETCH_W 0x306013 > +#define MASK_PREFETCH_W 0x1f07fff > /* Privileged CSR addresses. */ > #define CSR_USTATUS 0x0 > #define CSR_UIE 0x4 > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 37f60a8b61c..4ff24cc21b4 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -389,6 +389,7 @@ enum riscv_insn_class > INSN_CLASS_ZVEF, > INSN_CLASS_SVINVAL, > INSN_CLASS_ZICBOM, > + INSN_CLASS_ZICBOP, > INSN_CLASS_ZICBOZ, > }; > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index d646dd56e64..07644dbca7b 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -424,6 +424,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info > print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); > break; > > + case 'f': > + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); > + break; > + > case 'a': > info->target = EXTRACT_JTYPE_IMM (l) + pc; > (*info->print_address_func) (info->target, info); > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index fc2a1107784..c85f1042621 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -388,6 +388,9 @@ const struct riscv_opcode riscv_opcodes[] = > {"lw", 0, INSN_CLASS_I, "d,o(s)", MATCH_LW, MASK_LW, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"lw", 0, INSN_CLASS_I, "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, > {"not", 0, INSN_CLASS_I, "d,s", MATCH_XORI|MASK_IMM, MASK_XORI|MASK_IMM, match_opcode, INSN_ALIAS }, > +{"prefetch.i", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_I, MASK_PREFETCH_I, match_opcode, 0 }, > +{"prefetch.r", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_R, MASK_PREFETCH_R, match_opcode, 0 }, > +{"prefetch.w", 0, INSN_CLASS_ZICBOP, "f(s)", MATCH_PREFETCH_W, MASK_PREFETCH_W, match_opcode, 0 }, > {"ori", 0, INSN_CLASS_I, "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, > {"or", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > {"or", 0, INSN_CLASS_C, "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, > -- > 2.32.0 >