[PATCH v2 0/6] RISC-V: Implement support for big endian targets

[PATCH v2 0/6] RISC-V: Implement support for big endian targets

[Marcus Comstedt]

This is an updated patch series where I have squashed some patches,
and added ChangeLog entries.

  // Marcus

[PATCH v2 1/6] RISC-V: Support assembly and disassembly in big endian mode

[Marcus Comstedt]

bfd/
	* config.bfd: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
	* configure.ac: Likewise.
	* configure: Regenerate.
	* elfnn-riscv.c: (riscv_elf_object_p): Recognize elf32-bigriscv
	as 32-bit mach.
	(TARGET_BIG_SYM, TARGET_BIG_NAME): Add them.
	* targets.c: Add riscv_elf32_be_vec and riscv_elf64_be_vec.

gas/
	* config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv
	and elf32-bigriscv.
	(install_insn): Always write instructions as little endian.
	(md_number_to_chars): Write data in target endianness.
	(options): Add OPTION_BIG_ENDIAN and OPTION_LITTLE_ENDIAN.
	(md_longopts): Likewise.
	(md_parse_option): Likewise.
---
 bfd/config.bfd        |  4 ++--
 bfd/configure         |  2 ++
 bfd/configure.ac      |  2 ++
 bfd/elfnn-riscv.c     |  5 ++++-
 bfd/targets.c         |  4 ++++
 gas/config/tc-riscv.c | 24 +++++++++++++++++++++---
 6 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index fdc6dbe3dd..2ae8b1a4cc 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1160,12 +1160,12 @@ case "${targ}" in
 #ifdef BFD64
   riscv-*-* | riscv32*-*-*)
     targ_defvec=riscv_elf32_vec
-    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
   riscv64*-*-*)
     targ_defvec=riscv_elf64_vec
-    targ_selvecs="riscv_elf32_vec riscv_elf64_vec"
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
 #endif
diff --git a/bfd/configure b/bfd/configure
index 5d84aed069..1460bbdfba 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -14919,6 +14919,8 @@ do
     pru_elf32_vec)		 tb="$tb elf32-pru.lo elf32.lo $elf" ;;
     riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
     riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
+    riscv_elf32_be_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
+    riscv_elf64_be_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
diff --git a/bfd/configure.ac b/bfd/configure.ac
index 5ec4d4f0b4..4813e661aa 100644
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -625,6 +625,8 @@ do
     pru_elf32_vec)		 tb="$tb elf32-pru.lo elf32.lo $elf" ;;
     riscv_elf32_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
     riscv_elf64_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
+    riscv_elf32_be_vec)		 tb="$tb elf32-riscv.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf" ;;
+    riscv_elf64_be_vec)		 tb="$tb elf64-riscv.lo elf64.lo elfxx-riscv.lo elf-ifunc.lo elf32.lo $elf"; target_size=64 ;;
     rl78_elf32_vec)		 tb="$tb elf32-rl78.lo elf32.lo $elf" ;;
     rs6000_xcoff64_vec)		 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
     rs6000_xcoff64_aix_vec)	 tb="$tb coff64-rs6000.lo aix5ppc-core.lo $xcoff"; target_size=64 ;;
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 20944c8109..618fe9319f 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4943,7 +4943,8 @@ static bfd_boolean
 riscv_elf_object_p (bfd *abfd)
 {
   /* There are only two mach types in RISCV currently.  */
-  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0)
+  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0 ||
+      strcmp (abfd->xvec->name, "elf32-bigriscv") == 0)
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32);
   else
     bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64);
@@ -4962,6 +4963,8 @@ riscv_elf_obj_attrs_arg_type (int tag)
 
 #define TARGET_LITTLE_SYM		riscv_elfNN_vec
 #define TARGET_LITTLE_NAME		"elfNN-littleriscv"
+#define TARGET_BIG_SYM			riscv_elfNN_be_vec
+#define TARGET_BIG_NAME			"elfNN-bigriscv"
 
 #define elf_backend_reloc_type_class	     riscv_reloc_type_class
 
diff --git a/bfd/targets.c b/bfd/targets.c
index 8ae5c489fc..8fa8f693fb 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -843,6 +843,8 @@ extern const bfd_target powerpc_xcoff_vec;
 extern const bfd_target pru_elf32_vec;
 extern const bfd_target riscv_elf32_vec;
 extern const bfd_target riscv_elf64_vec;
+extern const bfd_target riscv_elf32_be_vec;
+extern const bfd_target riscv_elf64_be_vec;
 extern const bfd_target rl78_elf32_vec;
 extern const bfd_target rs6000_xcoff64_vec;
 extern const bfd_target rs6000_xcoff64_aix_vec;
@@ -1237,6 +1239,8 @@ static const bfd_target * const _bfd_target_vector[] =
 #ifdef BFD64
 	&riscv_elf32_vec,
 	&riscv_elf64_vec,
+	&riscv_elf32_be_vec,
+	&riscv_elf64_be_vec,
 #endif
 	&rl78_elf32_vec,
 
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ca7e52a169..622eb48448 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -445,7 +445,10 @@ static char *expr_end;
 const char *
 riscv_target_format (void)
 {
-  return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
+  if (target_big_endian)
+    return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
+  else
+    return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
 }
 
 /* Return the length of instruction INSN.  */
@@ -474,7 +477,7 @@ static void
 install_insn (const struct riscv_cl_insn *insn)
 {
   char *f = insn->frag->fr_literal + insn->where;
-  md_number_to_chars (f, insn->insn_opcode, insn_length (insn));
+  number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
 }
 
 /* Move INSN to offset WHERE in FRAG.  Adjust the fixups accordingly
@@ -2662,7 +2665,10 @@ md_atof (int type, char *litP, int *sizeP)
 void
 md_number_to_chars (char *buf, valueT val, int n)
 {
-  number_to_chars_littleendian (buf, val, n);
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
 }
 
 const char *md_shortopts = "O::g::G:";
@@ -2681,6 +2687,8 @@ enum options
   OPTION_NO_CSR_CHECK,
   OPTION_MISA_SPEC,
   OPTION_MPRIV_SPEC,
+  OPTION_BIG_ENDIAN,
+  OPTION_LITTLE_ENDIAN,
   OPTION_END_OF_ENUM
 };
 
@@ -2699,6 +2707,8 @@ struct option md_longopts[] =
   {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK},
   {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC},
   {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
+  {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
+  {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -2777,6 +2787,14 @@ md_parse_option (int c, const char *arg)
     case OPTION_MPRIV_SPEC:
       return riscv_set_default_priv_spec (arg);
 
+    case OPTION_BIG_ENDIAN:
+      target_big_endian = 1;
+      break;
+
+    case OPTION_LITTLE_ENDIAN:
+      target_big_endian = 0;
+      break;
+
     default:
       return 0;
     }
-- 
2.26.2

Re: [PATCH v2 1/6] RISC-V: Support assembly and disassembly in big endian mode

[Nelson Chu]

On Sun, Dec 20, 2020 at 7:30 PM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
> bfd/
>         * config.bfd: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
>         * configure.ac: Likewise.
>         * configure: Regenerate.
>         * elfnn-riscv.c: (riscv_elf_object_p): Recognize elf32-bigriscv
>         as 32-bit mach.
>         (TARGET_BIG_SYM, TARGET_BIG_NAME): Add them.
>         * targets.c: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
>
> gas/
>         * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv
>         and elf32-bigriscv.
>         (install_insn): Always write instructions as little endian.
>         (md_number_to_chars): Write data in target endianness.
>         (options): Add OPTION_BIG_ENDIAN and OPTION_LITTLE_ENDIAN.
>         (md_longopts): Likewise.
>         (md_parse_option): Likewise.

I can not build the default big-endian binutils by setting
--target=riscv32be-unknow-elf.  You can refer to what other targets
did in the gas/configure.tgt, to set the `endian` correctly;
Otherwise, lots of ld testcases are broken and failed.  And you also
need to update the gas/config/tc-riscv.h file, to only set the
TARGET_BYTES_BIG_ENDIAN if it is undefined.

Thanks
Nelson

Re: [PATCH v2 1/6] RISC-V: Support assembly and disassembly in big endian mode

[Marcus Comstedt]

Nelson Chu <nelson.chu@sifive.com> writes:

> I can not build the default big-endian binutils by setting
> --target=riscv32be-unknow-elf.  You can refer to what other targets
> did in the gas/configure.tgt, to set the `endian` correctly;
> Otherwise, lots of ld testcases are broken and failed.  And you also
> need to update the gas/config/tc-riscv.h file, to only set the
> TARGET_BYTES_BIG_ENDIAN if it is undefined.

Ah, yes you are right.  It seems that I overlooked this due to gcc
passing -mbig-endian for that triple.  Will fix.


  // Marcus

[PATCH v2 2/6] RISC-V: Fix relocations in big endian mode

[Marcus Comstedt]

bfd/
	* elfnn-riscv.c: (riscv_get_insn, riscv_put_insn): Add them.
	(riscv_is_insn_reloc): Add it.
	(perform_relocation): Use either target endian or fixed little
	endian memory access functions depending on whether the relocation
	is against data or an instruction.
	(riscv_zero_pcrel_hi_reloc, riscv_elf_relocate_section),
	(riscv_elf_finish_dynamic_symbol, riscv_elf_finish_dynamic_sections),
	(_bfd_riscv_relax_call, _bfd_riscv_relax_lui, _bfd_riscv_relax_align),
	(_bfd_riscv_relax_pc): Use fixed little endian memory access
	functions for accesing instructions.
---
 bfd/elfnn-riscv.c | 93 +++++++++++++++++++++++++++++++----------------
 1 file changed, 61 insertions(+), 32 deletions(-)

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 618fe9319f..d241ff2f09 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -126,6 +126,18 @@ struct riscv_elf_link_hash_table
 };
 
 
+/* Instruction access functions. */
+#define riscv_get_insn(bits, ptr)		\
+  ((bits) == 16 ? bfd_getl16 (ptr)		\
+   : (bits) == 32 ? bfd_getl32 (ptr)		\
+   : (bits) == 64 ? bfd_getl64 (ptr)		\
+   : (abort (), (bfd_vma) - 1))
+#define riscv_put_insn(bits, val, ptr)		\
+  ((bits) == 16 ? bfd_putl16 (val, ptr)		\
+   : (bits) == 32 ? bfd_putl32 (val, ptr)	\
+   : (bits) == 64 ? bfd_putl64 (val, ptr)	\
+   : (abort (), (void) 0))
+
 /* Get the RISC-V ELF linker hash table from a link_info structure.  */
 #define riscv_elf_hash_table(p) \
   ((is_elf_hash_table ((p)->hash)					\
@@ -152,6 +164,17 @@ riscv_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
   bed->s->swap_reloca_out (abfd, rel, loc);
 }
 
+/* Return true if a relocation is modifying an instruction. */
+
+static bfd_boolean
+riscv_is_insn_reloc (const reloc_howto_type *howto)
+{
+  /* Heuristic: A multibyte destination with a nontrivial mask
+     is an instruction */
+  return howto->bitsize > 8 && howto->dst_mask != 0 &&
+    ~(howto->dst_mask | (((bfd_vma)0 - 1) << howto->bitsize)) != 0;
+}
+
 /* PLT/GOT stuff.  */
 
 #define PLT_HEADER_INSNS 8
@@ -1636,10 +1659,10 @@ perform_relocation (const reloc_howto_type *howto,
 	  /* Linker relaxation can convert an address equal to or greater than
 	     0x800 to slightly below 0x800.  C.LUI does not accept zero as a
 	     valid immediate.  We can fix this by converting it to a C.LI.  */
-	  bfd_vma insn = bfd_get (howto->bitsize, input_bfd,
-				  contents + rel->r_offset);
+	  bfd_vma insn = riscv_get_insn (howto->bitsize,
+					 contents + rel->r_offset);
 	  insn = (insn & ~MATCH_C_LUI) | MATCH_C_LI;
-	  bfd_put (howto->bitsize, input_bfd, insn, contents + rel->r_offset);
+	  riscv_put_insn (howto->bitsize, insn, contents + rel->r_offset);
 	  value = ENCODE_RVC_IMM (0);
 	}
       else if (!VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (value)))
@@ -1675,9 +1698,16 @@ perform_relocation (const reloc_howto_type *howto,
       return bfd_reloc_notsupported;
     }
 
-  bfd_vma word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset);
+  bfd_vma word;
+  if (riscv_is_insn_reloc (howto))
+    word = riscv_get_insn (howto->bitsize, contents + rel->r_offset);
+  else
+    word = bfd_get (howto->bitsize, input_bfd, contents + rel->r_offset);
   word = (word & ~howto->dst_mask) | (value & howto->dst_mask);
-  bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset);
+  if (riscv_is_insn_reloc (howto))
+    riscv_put_insn (howto->bitsize, word, contents + rel->r_offset);
+  else
+    bfd_put (howto->bitsize, input_bfd, word, contents + rel->r_offset);
 
   return bfd_reloc_ok;
 }
@@ -1755,7 +1785,7 @@ riscv_zero_pcrel_hi_reloc (Elf_Internal_Rela *rel,
 			   bfd_vma addr,
 			   bfd_byte *contents,
 			   const reloc_howto_type *howto,
-			   bfd *input_bfd)
+			   bfd *input_bfd ATTRIBUTE_UNUSED)
 {
   /* We may need to reference low addreses in PC-relative modes even when the
    * PC is far away from these addresses.  For example, undefweak references
@@ -1781,9 +1811,9 @@ riscv_zero_pcrel_hi_reloc (Elf_Internal_Rela *rel,
 
   rel->r_info = ELFNN_R_INFO(addr, R_RISCV_HI20);
 
-  bfd_vma insn = bfd_get(howto->bitsize, input_bfd, contents + rel->r_offset);
+  bfd_vma insn = riscv_get_insn(howto->bitsize, contents + rel->r_offset);
   insn = (insn & ~MASK_AUIPC) | MATCH_LUI;
-  bfd_put(howto->bitsize, input_bfd, insn, contents + rel->r_offset);
+  riscv_put_insn(howto->bitsize, insn, contents + rel->r_offset);
   return TRUE;
 }
 
@@ -2371,10 +2401,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	      && (!bfd_link_pic (info) || h->plt.offset == MINUS_ONE))
 	    {
 	      /* We can use x0 as the base register.  */
-	      bfd_vma insn = bfd_get_32 (input_bfd,
-					 contents + rel->r_offset + 4);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset + 4);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (input_bfd, insn, contents + rel->r_offset + 4);
+	      bfd_putl32 (insn, contents + rel->r_offset + 4);
 	      /* Set the relocation value so that we get 0 after the pc
 		 relative adjustment.  */
 	      relocation = sec_addr (input_section) + rel->r_offset;
@@ -2407,10 +2436,10 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	  if (VALID_ITYPE_IMM (relocation + rel->r_addend))
 	    {
 	      /* We can use tp as the base register.  */
-	      bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
 	      insn |= X_TP << OP_SH_RS1;
-	      bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    r = bfd_reloc_overflow;
@@ -2424,14 +2453,14 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	    if (x0_base || VALID_ITYPE_IMM (relocation + rel->r_addend - gp))
 	      {
 		/* We can use x0 or gp as the base register.  */
-		bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
+		bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 		insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
 		if (!x0_base)
 		  {
 		    rel->r_addend -= gp;
 		    insn |= X_GP << OP_SH_RS1;
 		  }
-		bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
+		bfd_putl32 (insn, contents + rel->r_offset);
 	      }
 	    else
 	      r = bfd_reloc_overflow;
@@ -2855,7 +2884,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	return FALSE;
 
       for (i = 0; i < PLT_ENTRY_INSNS; i++)
-	bfd_put_32 (output_bfd, plt_entry[i], loc + 4*i);
+	bfd_putl32 (plt_entry[i], loc + 4*i);
 
       /* Fill in the initial value of the .got.plt entry.  */
       loc = gotplt->contents + (got_address - sec_addr (gotplt));
@@ -3152,7 +3181,7 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
 	    return ret;
 
 	  for (i = 0; i < PLT_HEADER_INSNS; i++)
-	    bfd_put_32 (output_bfd, plt_header[i], splt->contents + 4*i);
+	    bfd_putl32 (plt_header[i], splt->contents + 4*i);
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize
 	    = PLT_ENTRY_SIZE;
@@ -4142,8 +4171,8 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   /* Shorten the function call.  */
   BFD_ASSERT (rel->r_offset + 8 <= sec->size);
 
-  auipc = bfd_get_32 (abfd, contents + rel->r_offset);
-  jalr = bfd_get_32 (abfd, contents + rel->r_offset + 4);
+  auipc = bfd_getl32 (contents + rel->r_offset);
+  jalr = bfd_getl32 (contents + rel->r_offset + 4);
   rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
   rvc = rvc && VALID_RVC_J_IMM (foff);
 
@@ -4173,7 +4202,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   /* Replace the R_RISCV_CALL reloc.  */
   rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), r_type);
   /* Replace the AUIPC.  */
-  bfd_put (8 * len, abfd, auipc, contents + rel->r_offset);
+  riscv_put_insn (8 * len, auipc, contents + rel->r_offset);
 
   /* Delete unnecessary JALR.  */
   *again = TRUE;
@@ -4247,9 +4276,9 @@ _bfd_riscv_relax_lui (bfd *abfd,
 	  if (undefined_weak)
 	    {
 	      /* Change the RS1 to zero.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_I);
@@ -4259,9 +4288,9 @@ _bfd_riscv_relax_lui (bfd *abfd,
 	  if (undefined_weak)
 	    {
 	      /* Change the RS1 to zero.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	    }
 	  else
 	    rel->r_info = ELFNN_R_INFO (sym, R_RISCV_GPREL_S);
@@ -4292,13 +4321,13 @@ _bfd_riscv_relax_lui (bfd *abfd,
 			       : ELF_MAXPAGESIZE)))
     {
       /* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp).  */
-      bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
+      bfd_vma lui = bfd_getl32 (contents + rel->r_offset);
       unsigned rd = ((unsigned)lui >> OP_SH_RD) & OP_MASK_RD;
       if (rd == 0 || rd == X_SP)
 	return TRUE;
 
       lui = (lui & (OP_MASK_RD << OP_SH_RD)) | MATCH_C_LUI;
-      bfd_put_32 (abfd, lui, contents + rel->r_offset);
+      bfd_putl32 (lui, contents + rel->r_offset);
 
       /* Replace the R_RISCV_HI20 reloc.  */
       rel->r_info = ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_RVC_LUI);
@@ -4400,11 +4429,11 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
 
   /* Write as many RISC-V NOPs as we need.  */
   for (pos = 0; pos < (nop_bytes & -4); pos += 4)
-    bfd_put_32 (abfd, RISCV_NOP, contents + rel->r_offset + pos);
+    bfd_putl32 (RISCV_NOP, contents + rel->r_offset + pos);
 
   /* Write a final RVC NOP if need be.  */
   if (nop_bytes % 4 != 0)
-    bfd_put_16 (abfd, RVC_NOP, contents + rel->r_offset + pos);
+    bfd_putl16 (RVC_NOP, contents + rel->r_offset + pos);
 
   /* Delete the excess bytes.  */
   return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + nop_bytes,
@@ -4511,9 +4540,9 @@ _bfd_riscv_relax_pc  (bfd *abfd ATTRIBUTE_UNUSED,
 	    {
 	      /* Change the RS1 to zero, and then modify the relocation
 		 type to R_RISCV_LO12_I.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	      rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_I);
 	      rel->r_addend = hi_reloc.hi_addend;
 	    }
@@ -4529,9 +4558,9 @@ _bfd_riscv_relax_pc  (bfd *abfd ATTRIBUTE_UNUSED,
 	    {
 	      /* Change the RS1 to zero, and then modify the relocation
 		 type to R_RISCV_LO12_S.  */
-	      bfd_vma insn = bfd_get_32 (abfd, contents + rel->r_offset);
+	      bfd_vma insn = bfd_getl32 (contents + rel->r_offset);
 	      insn &= ~(OP_MASK_RS1 << OP_SH_RS1);
-	      bfd_put_32 (abfd, insn, contents + rel->r_offset);
+	      bfd_putl32 (insn, contents + rel->r_offset);
 	      rel->r_info = ELFNN_R_INFO (sym, R_RISCV_LO12_S);
 	      rel->r_addend = hi_reloc.hi_addend;
 	    }
-- 
2.26.2

[PATCH v2 3/6] RISC-V: Add big endian linker scripts

[Marcus Comstedt]

ld/
	* Makefile.am: (eelf32briscv.c, eelf32briscv_ilp32f.c),
	(eelf32briscv_ilp32.c): Add them.
	* Makefile.in: Regenerate.
	* emulparams/elf32briscv.sh: Add it.
	* emulparams/elf32briscv_ilp32.sh: Likewise.
	* emulparams/elf32briscv_ilp32f.sh: Likewise.
	* emulparams/elf64briscv.sh: Likewise.
	* emulparams/elf64briscv_lp64.sh: Likewise.
	* emulparams/elf64briscv_lp64f.sh: Likewise.
---
 ld/Makefile.am                      | 12 ++++++++++++
 ld/Makefile.in                      | 19 +++++++++++++++++++
 ld/emulparams/elf32briscv.sh        |  2 ++
 ld/emulparams/elf32briscv_ilp32.sh  |  2 ++
 ld/emulparams/elf32briscv_ilp32f.sh |  2 ++
 ld/emulparams/elf64briscv.sh        |  2 ++
 ld/emulparams/elf64briscv_lp64.sh   |  2 ++
 ld/emulparams/elf64briscv_lp64f.sh  |  2 ++
 8 files changed, 43 insertions(+)
 create mode 100644 ld/emulparams/elf32briscv.sh
 create mode 100644 ld/emulparams/elf32briscv_ilp32.sh
 create mode 100644 ld/emulparams/elf32briscv_ilp32f.sh
 create mode 100644 ld/emulparams/elf64briscv.sh
 create mode 100644 ld/emulparams/elf64briscv_lp64.sh
 create mode 100644 ld/emulparams/elf64briscv_lp64f.sh

diff --git a/ld/Makefile.am b/ld/Makefile.am
index 73144e730a..b5245f5b76 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -266,6 +266,9 @@ ALL_EMULATION_SOURCES = \
 	eelf32lriscv.c \
 	eelf32lriscv_ilp32f.c \
 	eelf32lriscv_ilp32.c \
+	eelf32briscv.c \
+	eelf32briscv_ilp32f.c \
+	eelf32briscv_ilp32.c \
 	eelf32rl78.c \
 	eelf32rx.c \
 	eelf32rx_linux.c \
@@ -435,6 +438,9 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64f.c \
 	eelf64lriscv_lp64.c \
+	eelf64briscv.c \
+	eelf64briscv_lp64f.c \
+	eelf64briscv_lp64.c \
 	eelf64ltsmip.c \
 	eelf64ltsmip_fbsd.c \
 	eelf64mmix.c \
@@ -751,6 +757,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx_linux.Pc@am__quote@
@@ -916,6 +925,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Pc@am__quote@
diff --git a/ld/Makefile.in b/ld/Makefile.in
index 178ae49009..8d8cfb33a7 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -521,6 +521,7 @@ pdfdir = @pdfdir@
 prefix = @prefix@
 program_transform_name = @program_transform_name@
 psdir = @psdir@
+runstatedir = @runstatedir@
 sbindir = @sbindir@
 sharedstatedir = @sharedstatedir@
 srcdir = @srcdir@
@@ -755,6 +756,9 @@ ALL_EMULATION_SOURCES = \
 	eelf32lriscv.c \
 	eelf32lriscv_ilp32f.c \
 	eelf32lriscv_ilp32.c \
+	eelf32briscv.c \
+	eelf32briscv_ilp32f.c \
+	eelf32briscv_ilp32.c \
 	eelf32rl78.c \
 	eelf32rx.c \
 	eelf32rx_linux.c \
@@ -923,6 +927,9 @@ ALL_64_EMULATION_SOURCES = \
 	eelf64lriscv.c \
 	eelf64lriscv_lp64f.c \
 	eelf64lriscv_lp64.c \
+	eelf64briscv.c \
+	eelf64briscv_lp64f.c \
+	eelf64briscv_lp64.c \
 	eelf64ltsmip.c \
 	eelf64ltsmip_fbsd.c \
 	eelf64mmix.c \
@@ -1318,6 +1325,9 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bfinfd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bmipn32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32bsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32btsmip_fbsd.Po@am__quote@
@@ -1403,6 +1413,9 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64alpha_nbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64btsmip_fbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64hppa.Po@am__quote@
@@ -2403,6 +2416,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32lriscv_ilp32.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32briscv_ilp32.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx_linux.Pc@am__quote@
@@ -2568,6 +2584,9 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64f.Pc@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64briscv_lp64.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Pc@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Pc@am__quote@
diff --git a/ld/emulparams/elf32briscv.sh b/ld/emulparams/elf32briscv.sh
new file mode 100644
index 0000000000..bad02bd5cf
--- /dev/null
+++ b/ld/emulparams/elf32briscv.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf32briscv_ilp32.sh b/ld/emulparams/elf32briscv_ilp32.sh
new file mode 100644
index 0000000000..c150108d3a
--- /dev/null
+++ b/ld/emulparams/elf32briscv_ilp32.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv_ilp32.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf32briscv_ilp32f.sh b/ld/emulparams/elf32briscv_ilp32f.sh
new file mode 100644
index 0000000000..52117e6b0c
--- /dev/null
+++ b/ld/emulparams/elf32briscv_ilp32f.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf32lriscv_ilp32f.sh
+OUTPUT_FORMAT="elf32-bigriscv"
diff --git a/ld/emulparams/elf64briscv.sh b/ld/emulparams/elf64briscv.sh
new file mode 100644
index 0000000000..86a429f10f
--- /dev/null
+++ b/ld/emulparams/elf64briscv.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv.sh
+OUTPUT_FORMAT="elf64-bigriscv"
diff --git a/ld/emulparams/elf64briscv_lp64.sh b/ld/emulparams/elf64briscv_lp64.sh
new file mode 100644
index 0000000000..b00717c31a
--- /dev/null
+++ b/ld/emulparams/elf64briscv_lp64.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv_lp64.sh
+OUTPUT_FORMAT="elf64-bigriscv"
diff --git a/ld/emulparams/elf64briscv_lp64f.sh b/ld/emulparams/elf64briscv_lp64f.sh
new file mode 100644
index 0000000000..a54a3f41c6
--- /dev/null
+++ b/ld/emulparams/elf64briscv_lp64f.sh
@@ -0,0 +1,2 @@
+source_sh ${srcdir}/emulparams/elf64lriscv_lp64f.sh
+OUTPUT_FORMAT="elf64-bigriscv"
-- 
2.26.2

[PATCH v2 4/6] RISC-V: Recognize riscvNNbe* as target

[Marcus Comstedt]

bfd/
	* config.bfd (riscvbe-*-*, riscv32be*-*-*),
	(riscv64be*-*-*): Add target.

ld/
	* configure.tgt: Add riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
	riscv32be*-*-linux*, and riscv64be*-*-linux*.
---
 bfd/config.bfd   | 10 ++++++++++
 config.sub       |  2 +-
 ld/configure.tgt | 25 +++++++++++++++++++++----
 3 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/bfd/config.bfd b/bfd/config.bfd
index 2ae8b1a4cc..f792bd01df 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -1158,11 +1158,21 @@ case "${targ}" in
     ;;
 
 #ifdef BFD64
+  riscvbe-*-* | riscv32be*-*-*)
+    targ_defvec=riscv_elf32_be_vec
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
+    want64=true
+    ;;
   riscv-*-* | riscv32*-*-*)
     targ_defvec=riscv_elf32_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
     want64=true
     ;;
+  riscv64be*-*-*)
+    targ_defvec=riscv_elf64_be_vec
+    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
+    want64=true
+    ;;
   riscv64*-*-*)
     targ_defvec=riscv_elf64_vec
     targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
diff --git a/config.sub b/config.sub
index f02d43ad50..7bb0fa6b83 100755
--- a/config.sub
+++ b/config.sub
@@ -1227,7 +1227,7 @@ case $cpu-$vendor in
 			| powerpc | powerpc64 | powerpc64le | powerpcle | powerpcspe \
 			| pru \
 			| pyramid \
-			| riscv | riscv32 | riscv64 \
+			| riscv | riscv32 | riscv64 | riscvbe | riscv32be | riscv64be \
 			| rl78 | romp | rs6000 | rx \
 			| score \
 			| sh | shl \
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 70359301b5..1a5cd476c4 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -738,21 +738,38 @@ powerpc-*-windiss*)	targ_emul=elf32ppcwindiss
 			;;
 pru*-*-*)		targ_emul=pruelf
 			;;
+riscv32be*-*-linux*)	targ_emul=elf32briscv
+			targ_extra_emuls="elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
 riscv32*-*-linux*)	targ_emul=elf32lriscv
-			targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
+			targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscvbe-*-* | riscv32be*-*-*)
+			targ_emul=elf32briscv
+			targ_extra_emuls="elf64briscv elf32lriscv elf64lriscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv-*-* | riscv32*-*-*)
 			targ_emul=elf32lriscv
-			targ_extra_emuls="elf64lriscv"
+			targ_extra_emuls="elf64lriscv elf32briscv elf64briscv"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscv64be*-*-linux*)	targ_emul=elf64briscv
+			targ_extra_emuls="elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv64*-*-linux*)	targ_emul=elf64lriscv
-			targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
+			targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32"
+			targ_extra_libpath=$targ_extra_emuls
+			;;
+riscv64be*-*-*)		targ_emul=elf64briscv
+			targ_extra_emuls="elf32briscv elf64lriscv elf32lriscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 riscv64*-*-*)		targ_emul=elf64lriscv
-			targ_extra_emuls="elf32lriscv"
+			targ_extra_emuls="elf32lriscv elf64briscv elf32briscv"
 			targ_extra_libpath=$targ_extra_emuls
 			;;
 rs6000-*-aix[5-9]*)	targ_emul=aix5rs6
-- 
2.26.2

Re: [PATCH v2 4/6] RISC-V: Recognize riscvNNbe* as target

[Nelson Chu]

On Sun, Dec 20, 2020 at 7:29 PM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
> bfd/
>         * config.bfd (riscvbe-*-*, riscv32be*-*-*),
>         (riscv64be*-*-*): Add target.
>
> ld/
>         * configure.tgt: Add riscvbe-*-*, riscv32be*-*-*, riscv64be*-*-*,
>         riscv32be*-*-linux*, and riscv64be*-*-linux*.
> ---
>  bfd/config.bfd   | 10 ++++++++++
>  config.sub       |  2 +-
>  ld/configure.tgt | 25 +++++++++++++++++++++----
>  3 files changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/bfd/config.bfd b/bfd/config.bfd
> index 2ae8b1a4cc..f792bd01df 100644
> --- a/bfd/config.bfd
> +++ b/bfd/config.bfd
> @@ -1158,11 +1158,21 @@ case "${targ}" in
>      ;;
>
>  #ifdef BFD64
> +  riscvbe-*-* | riscv32be*-*-*)
> +    targ_defvec=riscv_elf32_be_vec
> +    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
> +    want64=true
> +    ;;
>    riscv-*-* | riscv32*-*-*)
>      targ_defvec=riscv_elf32_vec
>      targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
>      want64=true
>      ;;
> +  riscv64be*-*-*)
> +    targ_defvec=riscv_elf64_be_vec
> +    targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"
> +    want64=true
> +    ;;
>    riscv64*-*-*)
>      targ_defvec=riscv_elf64_vec
>      targ_selvecs="riscv_elf32_vec riscv_elf64_vec riscv_elf32_be_vec riscv_elf64_be_vec"

I'm OK with this.  But we don't own the ISA spec, so we need to
discuss the new target triplets with RISC-V International in the
psabi, here is the open issue I opened,
https://github.com/riscv/riscv-elf-psabi-doc/issues/167.

> diff --git a/ld/configure.tgt b/ld/configure.tgt
> index 70359301b5..1a5cd476c4 100644
> --- a/ld/configure.tgt
> +++ b/ld/configure.tgt
> @@ -738,21 +738,38 @@ powerpc-*-windiss*)       targ_emul=elf32ppcwindiss
>                         ;;
>  pru*-*-*)              targ_emul=pruelf
>                         ;;
> +riscv32be*-*-linux*)   targ_emul=elf32briscv
> +                       targ_extra_emuls="elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
>  riscv32*-*-linux*)     targ_emul=elf32lriscv
> -                       targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64"
> +                       targ_extra_emuls="elf32lriscv_ilp32f elf32lriscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscvbe-*-* | riscv32be*-*-*)
> +                       targ_emul=elf32briscv
> +                       targ_extra_emuls="elf64briscv elf32lriscv elf64lriscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv-*-* | riscv32*-*-*)
>                         targ_emul=elf32lriscv
> -                       targ_extra_emuls="elf64lriscv"
> +                       targ_extra_emuls="elf64lriscv elf32briscv elf64briscv"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscv64be*-*-linux*)   targ_emul=elf64briscv
> +                       targ_extra_emuls="elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32 elf64lriscv elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv64*-*-linux*)     targ_emul=elf64lriscv
> -                       targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32"
> +                       targ_extra_emuls="elf64lriscv_lp64f elf64lriscv_lp64 elf32lriscv elf32lriscv_ilp32f elf32lriscv_ilp32 elf64briscv elf64briscv_lp64f elf64briscv_lp64 elf32briscv elf32briscv_ilp32f elf32briscv_ilp32"
> +                       targ_extra_libpath=$targ_extra_emuls
> +                       ;;
> +riscv64be*-*-*)                targ_emul=elf64briscv
> +                       targ_extra_emuls="elf32briscv elf64lriscv elf32lriscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;
>  riscv64*-*-*)          targ_emul=elf64lriscv
> -                       targ_extra_emuls="elf32lriscv"
> +                       targ_extra_emuls="elf32lriscv elf64briscv elf32briscv"
>                         targ_extra_libpath=$targ_extra_emuls
>                         ;;

I get at least 11 riscv ld testcases failed,

FAIL: call relaxation with alignment
FAIL: lui to c.lui relaxation
FAIL: c.lui to c.li relaxation
FAIL: jalr zero-offset symbols
FAIL: ld-riscv-elf/attr-merge-arch-01
FAIL: ld-riscv-elf/attr-merge-arch-02
FAIL: ld-riscv-elf/attr-merge-arch-03
FAIL: ld-riscv-elf/attr-merge-arch-failed-01
FAIL: ld-riscv-elf/attr-merge-arch-failed-02
FAIL: Weak reference 32
FAIL: Weak reference 64

The root cause is that these testcases set "-melf[32|64]lriscv" to
choose the right emulate files.  It's fine in the past since we
haven't support big endians, but we should find a way to fix them
after applying the big endian patches.  Ideally, I think we can refer
to what MIPS did in their ld-mips-elf/mips-elf.exp, use the
abi_asflags/abi_ldflags to choose the abi and emulate files.  But in
the short-term, I can accept the workaround that set your new
assembler option, -mlittle-endian, to always test the little endian
and pass these test cases temporarily.

Thanks
Nelson

Re: [PATCH v2 4/6] RISC-V: Recognize riscvNNbe* as target

[Marcus Comstedt]

Nelson Chu <nelson.chu@sifive.com> writes:

> I'm OK with this.  But we don't own the ISA spec, so we need to
> discuss the new target triplets with RISC-V International in the
> psabi, here is the open issue I opened,
> https://github.com/riscv/riscv-elf-psabi-doc/issues/167.

Thanks!  I must confess that the correct process to introducing a new
triplet was something of a mystery to me.  :-)


> I get at least 11 riscv ld testcases failed,
>
> FAIL: call relaxation with alignment
> FAIL: lui to c.lui relaxation
> FAIL: c.lui to c.li relaxation
> FAIL: jalr zero-offset symbols
> FAIL: ld-riscv-elf/attr-merge-arch-01
> FAIL: ld-riscv-elf/attr-merge-arch-02
> FAIL: ld-riscv-elf/attr-merge-arch-03
> FAIL: ld-riscv-elf/attr-merge-arch-failed-01
> FAIL: ld-riscv-elf/attr-merge-arch-failed-02
> FAIL: Weak reference 32
> FAIL: Weak reference 64

Ok, I'll take a look at this.  Thanks for the pointers!


  // Marcus

[PATCH v2 5/6] RISC-V: Fix branch frag conversion on big endian

[Marcus Comstedt]

gas/
	config/tc-riscv.c: (md_convert_frag_branch): Use fixed little
	endian memory access functions for accesing instructions.
---
 gas/config/tc-riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 622eb48448..4ede91847f 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -3486,14 +3486,14 @@ md_convert_frag_branch (fragS *fragp)
       insn = bfd_getl32 (buf);
       insn ^= MATCH_BEQ ^ MATCH_BNE;
       insn |= ENCODE_SBTYPE_IMM (8);
-      md_number_to_chars ((char *) buf, insn, 4);
+      bfd_putl32 (insn, buf);
       buf += 4;
 
     jump:
       /* Jump to the target.  */
       fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
 			  4, &exp, FALSE, BFD_RELOC_RISCV_JMP);
-      md_number_to_chars ((char *) buf, MATCH_JAL, 4);
+      bfd_putl32 (MATCH_JAL, buf);
       buf += 4;
       break;
 
-- 
2.26.2

[PATCH v2 6/6] RISC-V: Mention -mbig-endian and -mlittle-endian in doc

[Marcus Comstedt]

gas/
	* doc/as.texi: Add -mlittle-endian and -mbig-endian to docs.
	* doc/c-riscv.texi: Likewise.
---
 gas/doc/as.texi      |  1 +
 gas/doc/c-riscv.texi | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 983cec3cbf..2f8142472f 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -536,6 +536,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
    [@b{-march}=@var{ISA}]
    [@b{-mabi}=@var{ABI}]
+   [@b{-mlittle}|@b{-mlittle-endian}|@b{-mbig}|@b{-mbig-endian}]
 @end ifset
 @ifset RL78
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index d63b1f3990..481bfbbfbb 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -99,6 +99,16 @@ read-only CSR can not be written by the CSR instructions.
 @cindex @samp{-mno-csr-check} option, RISC-V
 @item -mno-csr-check
 Don't do CSR checking.
+
+@cindex @samp{-mlittle} option, RISC-V
+@cindex @samp{-mlittle-endian} option, RISC-V
+@item -mlittle, -mlittle-endian
+Generate code for a little endian machine.
+
+@cindex @samp{-mbig} option, RISC-V
+@cindex @samp{-mbig-endian} option, RISC-V
+@item -mbig, -mbig-endian
+Generate code for a big endian machine.
 @end table
 @c man end
 
-- 
2.26.2