From: Nelson Chu <nelson.chu@sifive.com>
To: Binutils <binutils@sourceware.org>, gdb-patches@sourceware.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>, Jim Wilson <jimw@sifive.com>,
Andrew Waterman <andrew@sifive.com>,
Andrew Burgess <andrew.burgess@embecosm.com>,
Alex Bradbury <asb@lowrisc.org>,
Maxim Blinov <maxim.blinov@embecosm.com>
Subject: Re: [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case.
Date: Tue, 19 May 2020 17:07:41 +0800 [thread overview]
Message-ID: <CAJYME4G2u5cx9MHsJ4oxeksfc+PzQ1VQT0cuOODNQEApLLnjZg@mail.gmail.com> (raw)
In-Reply-To: <1588733747-18787-3-git-send-email-nelson.chu@sifive.com>
PING :)
On Wed, May 6, 2020 at 10:55 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> priv-reg and priv-reg-fail-read-only-01 should be updated at the same time.
> The fromer checks all CSR by csrr instructions, and the later uses csrw to
> check whether the CSR is read only or not.
>
> gas/
> * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
> ---
> .../gas/riscv/priv-reg-fail-read-only-01.s | 114 ++++++++++-----------
> 1 file changed, 57 insertions(+), 57 deletions(-)
>
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> index 501a52e..3646c80 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s
> @@ -1,7 +1,8 @@
> .macro csr val
> csrw \val, a1
> .endm
> -# 1.9.1 registers
> +
> + # Supported the current priv spec 1.11.
> csr ustatus
> csr uie
> csr utvec
> @@ -9,7 +10,7 @@
> csr uscratch
> csr uepc
> csr ucause
> - csr ubadaddr
> + csr utval # Added in 1.10
> csr uip
>
> csr fflags
> @@ -86,26 +87,15 @@
> csr sideleg
> csr sie
> csr stvec
> + csr scounteren # Added in 1.10
>
> csr sscratch
> csr sepc
> csr scause
> - csr sbadaddr
> + csr stval # Added in 1.10
> csr sip
>
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> + csr satp # Added in 1.10
>
> csr mvendorid
> csr marchid
> @@ -113,24 +103,39 @@
> csr mhartid
>
> csr mstatus
> - csr misa
> + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> csr medeleg
> csr mideleg
> csr mie
> csr mtvec
> + csr mcounteren # Added in 1.10
>
> csr mscratch
> csr mepc
> csr mcause
> - csr mbadaddr
> + csr mtval # Added in 1.10
> csr mip
>
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> + csr pmpcfg0 # Added in 1.10
> + csr pmpcfg1 # Added in 1.10
> + csr pmpcfg2 # Added in 1.10
> + csr pmpcfg3 # Added in 1.10
> + csr pmpaddr0 # Added in 1.10
> + csr pmpaddr1 # Added in 1.10
> + csr pmpaddr2 # Added in 1.10
> + csr pmpaddr3 # Added in 1.10
> + csr pmpaddr4 # Added in 1.10
> + csr pmpaddr5 # Added in 1.10
> + csr pmpaddr6 # Added in 1.10
> + csr pmpaddr7 # Added in 1.10
> + csr pmpaddr8 # Added in 1.10
> + csr pmpaddr9 # Added in 1.10
> + csr pmpaddr10 # Added in 1.10
> + csr pmpaddr11 # Added in 1.10
> + csr pmpaddr12 # Added in 1.10
> + csr pmpaddr13 # Added in 1.10
> + csr pmpaddr14 # Added in 1.10
> + csr pmpaddr15 # Added in 1.10
>
> csr mcycle
> csr minstret
> @@ -195,10 +200,7 @@
> csr mhpmcounter30h
> csr mhpmcounter31h
>
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> + csr mcountinhibit # Added in 1.11
> csr mhpmevent3
> csr mhpmevent4
> csr mhpmevent5
> @@ -236,34 +238,32 @@
>
> csr dcsr
> csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> + csr dscratch0 # Added in 1.11
> + csr dscratch1 # Added in 1.11
>
> - csr mcounteren
> - csr mtval
> + # Supported in previous priv spec, but dropped now.
> + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
>
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> + csr hstatus # 0x200, dropped in 1.10
> + csr hedeleg # 0x202, dropped in 1.10
> + csr hideleg # 0x203, dropped in 1.10
> + csr hie # 0x204, dropped in 1.10
> + csr htvec # 0x205, dropped in 1.10
> + csr hscratch # 0x240, dropped in 1.10
> + csr hepc # 0x241, dropped in 1.10
> + csr hcause # 0x242, dropped in 1.10
> + csr hbadaddr # 0x243, dropped in 1.10
> + csr hip # 0x244, dropped in 1.10
> + csr mbase # 0x380, dropped in 1.10
> + csr mbound # 0x381, dropped in 1.10
> + csr mibase # 0x382, dropped in 1.10
> + csr mibound # 0x383, dropped in 1.10
> + csr mdbase # 0x384, dropped in 1.10
> + csr mdbound # 0x385, dropped in 1.10
> + csr mscounteren # 0x321, dropped in 1.10
> + csr mhcounteren # 0x322, dropped in 1.10
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-19 9:07 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-06 2:55 [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-06 2:55 ` [PATCH v2 1/9] RISC-V: Remove the redundant gas test file Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 2/9] RISC-V: Forgot to update the priv-reg-fail-read-only-01 test case Nelson Chu
2020-05-19 9:07 ` Nelson Chu [this message]
2020-05-06 2:55 ` [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default Nelson Chu
2020-05-19 9:07 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 6/9] RISC-V: Support configure option to choose the " Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 7/9] RISC-V: Make privilege spec attributes workable Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 8/9] RISC-V: Disassembler dumps the CSR according to the chosen privilege spec Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-06 2:55 ` [PATCH v2 9/9] RISC-V: Add documents and --help for the new GAS and OBJDUMP options Nelson Chu
2020-05-19 9:08 ` Nelson Chu
2020-05-19 9:07 ` [PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR Nelson Chu
2020-05-20 16:27 ` Nick Clifton
2020-05-21 2:38 ` Nelson Chu
2020-05-21 7:29 ` Nick Clifton
2020-05-21 9:11 ` Nelson Chu
2020-05-28 20:09 ` Jim Wilson
2020-05-29 1:02 ` Nelson Chu
2020-06-01 21:35 ` Jim Wilson
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