* [PATCH] RISCV:Create zmmul extension
@ 2021-10-28 1:54 shihua
2021-11-02 8:11 ` Jan Beulich
2021-11-09 4:23 ` Nelson Chu
0 siblings, 2 replies; 3+ messages in thread
From: shihua @ 2021-10-28 1:54 UTC (permalink / raw)
To: binutils
Cc: kito.cheng, jimw, cmuellner, palmer, andrew, lazyparser, jiawei,
anku.anand, Liaoshihua
From: Liaoshihua <shihua@iscas.ac.cn>
The Zmmul extension implements the multiplication subset of the M extension.I had added it in Gcc and Binutils.This patch is the realization of Zmmul.
You can see them in https://github.com/Liaoshihua/riscv-binutils-gdb/tree/riscv-binutils-2.37-zmmul and https://github.com/Liaoshihua/riscv-gcc/tree/riscv-gcc-11.1.0-zmmul. The run results are in https://ci.rvperf.org/job/gnu-toolchain-zmmul-extension/.
bfd/elfxx-riscv.c | 2 +-
gas/config/tc-riscv.c | 5 +++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 10 +++++-----
4 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 39b69e2b0a..616c759487 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1077,7 +1077,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
static const char * const riscv_std_z_ext_strtab[] =
{
- "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL
+ "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", "zmmul", NULL
};
static const char * const riscv_std_s_ext_strtab[] =
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 70cbc8190f..f904c6baa0 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -143,6 +143,8 @@ static const struct riscv_ext_version ext_version_table[] =
{"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
{"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
+ {"zmmul", ISA_SPEC_CLASS_DRAFT, 0, 1},
+
/* Terminate the list. */
{NULL, 0, 0, 0}
};
@@ -343,6 +345,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZBC:
return riscv_subset_supports ("zbc");
+ case INSN_CLASS_ZMMUL:
+ return riscv_subset_supports ("zmmul");
+
default:
as_fatal ("internal: unreachable");
return false;
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index fdf3df4f5c..6b62f059ea 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -319,6 +319,7 @@ enum riscv_insn_class
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
+ INSN_CLASS_ZMMUL,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f55a01b071..9781e400ca 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -489,15 +489,15 @@ const struct riscv_opcode riscv_opcodes[] =
{"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
/* Multiply/Divide instruction subset. */
-{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
-{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
-{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
-{"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
+{"mul", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
+{"mulh", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
+{"mulhu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
+{"mulhsu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
{"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 },
{"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
{"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 },
{"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 },
-{"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
+{"mulw", 64, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
{"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
{"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
{"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
--
2.31.1.windows.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISCV:Create zmmul extension
2021-10-28 1:54 [PATCH] RISCV:Create zmmul extension shihua
@ 2021-11-02 8:11 ` Jan Beulich
2021-11-09 4:23 ` Nelson Chu
1 sibling, 0 replies; 3+ messages in thread
From: Jan Beulich @ 2021-11-02 8:11 UTC (permalink / raw)
To: shihua; +Cc: cmuellner, jiawei, anku.anand, kito.cheng, binutils
On 28.10.2021 03:54, shihua@iscas.ac.cn wrote:
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -319,6 +319,7 @@ enum riscv_insn_class
> INSN_CLASS_ZBA,
> INSN_CLASS_ZBB,
> INSN_CLASS_ZBC,
> + INSN_CLASS_ZMMUL,
This being enumerators I don't think you can ...
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -489,15 +489,15 @@ const struct riscv_opcode riscv_opcodes[] =
> {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>
> /* Multiply/Divide instruction subset. */
> -{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
> -{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
> -{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
> -{"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
> +{"mul", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
> +{"mulh", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
> +{"mulhu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
> +{"mulhsu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
> {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 },
> {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
> {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 },
> {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 },
> -{"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
> +{"mulw", 64, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
... combine them with || (or | for that matter) - you effectively produce
INSN_CLASS_I here afaict.
Jan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISCV:Create zmmul extension
2021-10-28 1:54 [PATCH] RISCV:Create zmmul extension shihua
2021-11-02 8:11 ` Jan Beulich
@ 2021-11-09 4:23 ` Nelson Chu
1 sibling, 0 replies; 3+ messages in thread
From: Nelson Chu @ 2021-11-09 4:23 UTC (permalink / raw)
To: shihua; +Cc: Binutils, cmuellner, jiawei, anku.anand, Kito Cheng
Hi Shihua,
I have checked the status of zmmul, it hasn't been frozen for now, so
we probably should place it in the users/riscv/integration branch,
rather than mainline.
On Thu, Oct 28, 2021 at 9:55 AM <shihua@iscas.ac.cn> wrote:
>
> From: Liaoshihua <shihua@iscas.ac.cn>
>
> The Zmmul extension implements the multiplication subset of the M extension.I had added it in Gcc and Binutils.This patch is the realization of Zmmul.
> You can see them in https://github.com/Liaoshihua/riscv-binutils-gdb/tree/riscv-binutils-2.37-zmmul and https://github.com/Liaoshihua/riscv-gcc/tree/riscv-gcc-11.1.0-zmmul. The run results are in https://ci.rvperf.org/job/gnu-toolchain-zmmul-extension/.
>
> bfd/elfxx-riscv.c | 2 +-
> gas/config/tc-riscv.c | 5 +++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 10 +++++-----
> 4 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 39b69e2b0a..616c759487 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1077,7 +1077,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>
> static const char * const riscv_std_z_ext_strtab[] =
> {
> - "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL
> + "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", "zmmul", NULL
> };
This is the old code base. I suppose you should add the zmmul entry
in the riscv_supported_std_z_ext, with the ISA_SPEC_CLASS_DRAFT and
maybe version 0.1 (not sure about this)?
> static const char * const riscv_std_s_ext_strtab[] =
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 70cbc8190f..f904c6baa0 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -143,6 +143,8 @@ static const struct riscv_ext_version ext_version_table[] =
> {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
> {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
>
> + {"zmmul", ISA_SPEC_CLASS_DRAFT, 0, 1},
> +
> /* Terminate the list. */
> {NULL, 0, 0, 0}
> };
We don't need these anymore, since these information are combined into
the riscv_supported_std_* tables.
> @@ -343,6 +345,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
> case INSN_CLASS_ZBC:
> return riscv_subset_supports ("zbc");
>
> + case INSN_CLASS_ZMMUL:
> + return riscv_subset_supports ("zmmul");
> +
Consider to add this in the riscv_extended_subset_supports, and should be,
case INSN_CLASS_ZMMUL:
return (riscv_subset_supports ("m")
|| riscv_subset_supports ("zmmul"));
> default:
> as_fatal ("internal: unreachable");
> return false;
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index fdf3df4f5c..6b62f059ea 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -319,6 +319,7 @@ enum riscv_insn_class
> INSN_CLASS_ZBA,
> INSN_CLASS_ZBB,
> INSN_CLASS_ZBC,
> + INSN_CLASS_ZMMUL,
> };
Add INSN_CLASS_ZMMUL in the enum riscv_extended_insn_class.
> /* This structure holds information for a particular instruction. */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index f55a01b071..9781e400ca 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -489,15 +489,15 @@ const struct riscv_opcode riscv_opcodes[] =
> {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
>
> /* Multiply/Divide instruction subset. */
> -{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
> -{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
> -{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
> -{"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
> +{"mul", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
> +{"mulh", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 },
> +{"mulhu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 },
> +{"mulhsu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 },
Yes, like what Jan commented, this won't work as expected. Just
changing the classes to INSN_CLASS_ZMMUL is enough, and then we check
the details in the riscv_extended_subset_supports.
> {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 },
> {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 },
> {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 },
> {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 },
> -{"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
> +{"mulw", 64, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 },
> {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 },
> {"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 },
> {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 },
> --
> 2.31.1.windows.1
>
Thanks
Nelson
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-10-28 1:54 [PATCH] RISCV:Create zmmul extension shihua
2021-11-02 8:11 ` Jan Beulich
2021-11-09 4:23 ` Nelson Chu
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