From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by sourceware.org (Postfix) with ESMTPS id 83FA23858C60 for ; Tue, 9 Nov 2021 04:23:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 83FA23858C60 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-io1-xd32.google.com with SMTP id z26so4372248iod.10 for ; Mon, 08 Nov 2021 20:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gRE6GiXXVTnLafH3aIM/+QMJK9lJXlWBBIpKa7sZwIg=; b=iyhNKEnrb5z9VrK0W2VFKb8EHDNCt+gjl0vWGTnJ7nnuxG8NU95c1yJRIF/OUPtAlS r7eqExwoNo+Dm+CyjueOEHR/OnehKn8BNuTx/x4hfsoBepmcCpCyxCwG/78exIyjxdq5 4gm+XomFi3+elBLG+qpS9PJqa8jLIRumlDpltwtRAD0wOv202/5BIgkqqd+FNjLXrdcV +CDpRg7DgKPq5LiFfdtkPncj542P3OgvtNeCDE0ITGg4HP6IQwylIzcXamKqKuea5WoK dosgZ4MMCAxNE90Oa5nfeLJjSwGvZSum9Fo4cFAJ7lKO065CYB9wUZYHeNY2S9sqAhya Tx4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gRE6GiXXVTnLafH3aIM/+QMJK9lJXlWBBIpKa7sZwIg=; b=DakGUIgLFf+MK3wHSxmTy2Y5DnzG7680J0dGmdbRa4TZR88woiuKNUBSNBNnEqrgbO ZfxbLWxDvFN2vTJBqY3tSpQSm2f+6aqbqhLv2/iQE6EGfe93vJUe6J666amQBRV/07ej ENte7BKAZMIKd7MjnVg2DQUQuwikJ6EkDDjrSXY03LqcSWEpzZn8ZcoGOriBGcFb1A+3 X7Aky3a8FlFDxWxxnH+f4A1R2VTAqMo2LiT4Ireo4UQIBQIXrjEenTObMe41eRTTacDC eno3R92Z8YWvslZwRRSggMcDsPdBMDWIEzhwDNsj4VYTNyNBUeEtR+QCvnV3m62txMSG unjw== X-Gm-Message-State: AOAM530dfc+6EViD9JyXx1FoAtT9Iv+9xmIrxQqoT26qni8RgnGiBm+7 ksyizIplyUMlTLrUIGp2f0X+eOvXG1ADSdq6/RI2NA== X-Google-Smtp-Source: ABdhPJzHpWFEEgh5UMBNxpRZcWeBU7GVctTkHQcgAQ1yg+4szOUHiP+x6HKxiVG9xaJ14SYsUHiNpuo7DGEVj+3DVMI= X-Received: by 2002:a05:6602:2ccf:: with SMTP id j15mr2942156iow.77.1636431798789; Mon, 08 Nov 2021 20:23:18 -0800 (PST) MIME-Version: 1.0 References: <20211028015426.1501-1-shihua@iscas.ac.cn> In-Reply-To: <20211028015426.1501-1-shihua@iscas.ac.cn> From: Nelson Chu Date: Tue, 9 Nov 2021 12:23:08 +0800 Message-ID: Subject: Re: [PATCH] RISCV:Create zmmul extension To: shihua@iscas.ac.cn Cc: Binutils , cmuellner@ventanamicro.com, jiawei , anku.anand@gmail.com, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Nov 2021 04:23:21 -0000 Hi Shihua, I have checked the status of zmmul, it hasn't been frozen for now, so we probably should place it in the users/riscv/integration branch, rather than mainline. On Thu, Oct 28, 2021 at 9:55 AM wrote: > > From: Liaoshihua > > The Zmmul extension implements the multiplication subset of the M extension.I had added it in Gcc and Binutils.This patch is the realization of Zmmul. > You can see them in https://github.com/Liaoshihua/riscv-binutils-gdb/tree/riscv-binutils-2.37-zmmul and https://github.com/Liaoshihua/riscv-gcc/tree/riscv-gcc-11.1.0-zmmul. The run results are in https://ci.rvperf.org/job/gnu-toolchain-zmmul-extension/. > > bfd/elfxx-riscv.c | 2 +- > gas/config/tc-riscv.c | 5 +++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 10 +++++----- > 4 files changed, 12 insertions(+), 6 deletions(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 39b69e2b0a..616c759487 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1077,7 +1077,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = > > static const char * const riscv_std_z_ext_strtab[] = > { > - "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL > + "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", "zmmul", NULL > }; This is the old code base. I suppose you should add the zmmul entry in the riscv_supported_std_z_ext, with the ISA_SPEC_CLASS_DRAFT and maybe version 0.1 (not sure about this)? > static const char * const riscv_std_s_ext_strtab[] = > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index 70cbc8190f..f904c6baa0 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -143,6 +143,8 @@ static const struct riscv_ext_version ext_version_table[] = > {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93}, > {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93}, > > + {"zmmul", ISA_SPEC_CLASS_DRAFT, 0, 1}, > + > /* Terminate the list. */ > {NULL, 0, 0, 0} > }; We don't need these anymore, since these information are combined into the riscv_supported_std_* tables. > @@ -343,6 +345,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) > case INSN_CLASS_ZBC: > return riscv_subset_supports ("zbc"); > > + case INSN_CLASS_ZMMUL: > + return riscv_subset_supports ("zmmul"); > + Consider to add this in the riscv_extended_subset_supports, and should be, case INSN_CLASS_ZMMUL: return (riscv_subset_supports ("m") || riscv_subset_supports ("zmmul")); > default: > as_fatal ("internal: unreachable"); > return false; > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index fdf3df4f5c..6b62f059ea 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -319,6 +319,7 @@ enum riscv_insn_class > INSN_CLASS_ZBA, > INSN_CLASS_ZBB, > INSN_CLASS_ZBC, > + INSN_CLASS_ZMMUL, > }; Add INSN_CLASS_ZMMUL in the enum riscv_extended_insn_class. > /* This structure holds information for a particular instruction. */ > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index f55a01b071..9781e400ca 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -489,15 +489,15 @@ const struct riscv_opcode riscv_opcodes[] = > {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, > > /* Multiply/Divide instruction subset. */ > -{"mul", 0, INSN_CLASS_M, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, > -{"mulh", 0, INSN_CLASS_M, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, > -{"mulhu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, > -{"mulhsu", 0, INSN_CLASS_M, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, > +{"mul", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, > +{"mulh", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, > +{"mulhu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, > +{"mulhsu", 0, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, Yes, like what Jan commented, this won't work as expected. Just changing the classes to INSN_CLASS_ZMMUL is enough, and then we check the details in the riscv_extended_subset_supports. > {"div", 0, INSN_CLASS_M, "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, > {"divu", 0, INSN_CLASS_M, "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, > {"rem", 0, INSN_CLASS_M, "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, > {"remu", 0, INSN_CLASS_M, "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, > -{"mulw", 64, INSN_CLASS_M, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, > +{"mulw", 64, INSN_CLASS_M || INSN_CLASS_ZMMUL, "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, > {"divw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, > {"divuw", 64, INSN_CLASS_M, "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, > {"remw", 64, INSN_CLASS_M, "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, > -- > 2.31.1.windows.1 > Thanks Nelson