* [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0
2021-10-06 20:26 [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Philipp Tomsich
@ 2021-10-06 20:26 ` Philipp Tomsich
2021-10-07 4:02 ` Nelson Chu
2021-10-06 20:26 ` [PATCH v3 3/4] RISC-V: Add support for Zbs instructions Philipp Tomsich
` (2 subsequent siblings)
3 siblings, 1 reply; 17+ messages in thread
From: Philipp Tomsich @ 2021-10-06 20:26 UTC (permalink / raw)
To: binutils; +Cc: Kito Cheng, Jim Wilson, Jan Beulich, Philipp Tomsich
2021-10-06 Philipp Tomsich <philipp.tomsich@vrull.eu>
bfd/
* elfxx-riscv.c (riscv_supported_std_z_ext): Update the version
number for zba, zbb and zbc to 1.0.0
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Version-changes: 3
- Updated version numbers for zba, zbb and zbc to 1.0.0
---
(no changes since v1)
bfd/elfxx-riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 044cc63d09e..39a7d693469 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1142,9 +1142,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
- {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
- {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
- {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
+ {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0
2021-10-06 20:26 ` [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0 Philipp Tomsich
@ 2021-10-07 4:02 ` Nelson Chu
0 siblings, 0 replies; 17+ messages in thread
From: Nelson Chu @ 2021-10-07 4:02 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Binutils, Kito Cheng
LGTM, thanks.
Nelson
On Thu, Oct 7, 2021 at 4:27 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> 2021-10-06 Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> bfd/
> * elfxx-riscv.c (riscv_supported_std_z_ext): Update the version
> number for zba, zbb and zbc to 1.0.0
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> Version-changes: 3
> - Updated version numbers for zba, zbb and zbc to 1.0.0
>
> ---
>
> (no changes since v1)
>
> bfd/elfxx-riscv.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 044cc63d09e..39a7d693469 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1142,9 +1142,9 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
> {"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> - {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
> - {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
> - {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93, 0 },
> + {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 3/4] RISC-V: Add support for Zbs instructions
2021-10-06 20:26 [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Philipp Tomsich
2021-10-06 20:26 ` [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0 Philipp Tomsich
@ 2021-10-06 20:26 ` Philipp Tomsich
2021-10-07 4:02 ` Nelson Chu
2021-10-07 6:57 ` Jan Beulich
2021-10-06 20:26 ` [PATCH v3 4/4] RISC-V: Support aliases " Philipp Tomsich
2021-10-07 4:01 ` [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Nelson Chu
3 siblings, 2 replies; 17+ messages in thread
From: Philipp Tomsich @ 2021-10-06 20:26 UTC (permalink / raw)
To: binutils; +Cc: Kito Cheng, Jim Wilson, Jan Beulich, Philipp Tomsich
This change adds the Zbs instructions from the Zbs 1.0.0 specification.
See
https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
for the frozen specification.
2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu>
bfd/
* elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS.
* testsuite/gas/riscv/b-ext.d: Test Zbs instructions.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS.
opcodes/
* riscv-opc.c (riscv_supported_std_z_ext): Add zbs.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v3:
- Updated to 1.0.0 specification and rebased to master
bfd/elfxx-riscv.c | 1 +
gas/config/tc-riscv.c | 3 +++
gas/testsuite/gas/riscv/b-ext-64.d | 18 +++++++++++++++++-
gas/testsuite/gas/riscv/b-ext-64.s | 16 ++++++++++++++++
gas/testsuite/gas/riscv/b-ext.d | 14 +++++++++++++-
gas/testsuite/gas/riscv/b-ext.s | 12 ++++++++++++
include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 9 +++++++++
9 files changed, 96 insertions(+), 2 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 39a7d693469..cdb4fa0996a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1145,6 +1145,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e7b733a4e6d..f7e0c929aa0 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -283,6 +283,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZBC:
return riscv_subset_supports ("zbc");
+ case INSN_CLASS_ZBS:
+ return riscv_subset_supports ("zbs");
+
default:
as_fatal ("internal: unreachable");
return false;
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
index f4a7abf02d7..339fa20a367 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i_zba_zbb_zbc
+#as: -march=rv64i_zba_zbb_zbc_zbs
#source: b-ext-64.s
#objdump: -d
@@ -46,3 +46,19 @@ Disassembly of section .text:
[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
+[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
index c3ac377f4bd..8ceb2b4fd1c 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -37,3 +37,19 @@ target:
add.uw a0, a1, a2
zext.w a0, a1
slli.uw a0, a1, 2
+ bclri a0, a1, 0
+ bclri a0, a1, 31
+ bseti a0, a1, 0
+ bseti a0, a1, 31
+ binvi a0, a1, 0
+ binvi a0, a1, 31
+ bexti a0, a1, 0
+ bexti a0, a1, 31
+ bclri a0, a1, 63
+ bseti a0, a1, 63
+ binvi a0, a1, 63
+ bexti a0, a1, 63
+ bclr a0, a1, a2
+ bset a0, a1, a2
+ binv a0, a1, a2
+ bext a0, a1, a2
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
index 7410796a3b7..748c218fdd0 100644
--- a/gas/testsuite/gas/riscv/b-ext.d
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -1,4 +1,4 @@
-#as: -march=rv32i_zba_zbb_zbc
+#as: -march=rv32i_zba_zbb_zbc_zbs
#source: b-ext.s
#objdump: -d
@@ -33,3 +33,15 @@ Disassembly of section .text:
[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
index 051dafd1719..a13a797f0dc 100644
--- a/gas/testsuite/gas/riscv/b-ext.s
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -24,3 +24,15 @@ target:
clmul a0, a1, a2
clmulh a0, a1, a2
clmulr a0, a1, a2
+ bclri a0, a1, 0
+ bclri a0, a1, 31
+ bseti a0, a1, 0
+ bseti a0, a1, 31
+ binvi a0, a1, 0
+ binvi a0, a1, 31
+ bexti a0, a1, 0
+ bexti a0, a1, 31
+ bclr a0, a1, a2
+ bset a0, a1, a2
+ binv a0, a1, a2
+ bext a0, a1, a2
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9999da6241a..45a207da0cd 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -495,6 +495,22 @@
#define MASK_CLMULH 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
+#define MATCH_BCLRI 0x48001013
+#define MASK_BCLRI 0xfc00707f
+#define MATCH_BSETI 0x28001013
+#define MASK_BSETI 0xfc00707f
+#define MATCH_BINVI 0x68001013
+#define MASK_BINVI 0xfc00707f
+#define MATCH_BEXTI 0x48005013
+#define MASK_BEXTI 0xfc00707f
+#define MATCH_BCLR 0x48001033
+#define MASK_BCLR 0xfe00707f
+#define MATCH_BSET 0x28001033
+#define MASK_BSET 0xfe00707f
+#define MATCH_BINV 0x68001033
+#define MASK_BINV 0xfe00707f
+#define MATCH_BEXT 0x48005033
+#define MASK_BEXT 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
@@ -1102,6 +1118,14 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
+DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
+DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
+DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
+DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
+DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
+DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
+DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
+DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index a8f47419f75..afcd41ff1dd 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -319,6 +319,7 @@ enum riscv_insn_class
INSN_CLASS_ZBA,
INSN_CLASS_ZBB,
INSN_CLASS_ZBC,
+ INSN_CLASS_ZBS,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e0621503b79..1a4c9f0e4fe 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -833,6 +833,15 @@ const struct riscv_opcode riscv_opcodes[] =
{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+/* Zbs instructions */
+{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
+{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
+{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
+{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
+{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
+{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
+{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 3/4] RISC-V: Add support for Zbs instructions
2021-10-06 20:26 ` [PATCH v3 3/4] RISC-V: Add support for Zbs instructions Philipp Tomsich
@ 2021-10-07 4:02 ` Nelson Chu
2021-10-07 6:57 ` Jan Beulich
1 sibling, 0 replies; 17+ messages in thread
From: Nelson Chu @ 2021-10-07 4:02 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Binutils, Kito Cheng
LGTM, thanks.
Nelson
On Thu, Oct 7, 2021 at 4:28 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> This change adds the Zbs instructions from the Zbs 1.0.0 specification.
> See
> https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0
> for the frozen specification.
>
> 2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> bfd/
> * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs.
> gas/
> * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS.
> * testsuite/gas/riscv/b-ext.d: Test Zbs instructions.
> * testsuite/gas/riscv/b-ext.s: Likewise.
> * testsuite/gas/riscv/b-ext-64.d: Likewise.
> * testsuite/gas/riscv/b-ext-64.s: Likewise.
> include/
> * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs.
> * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS.
> opcodes/
> * riscv-opc.c (riscv_supported_std_z_ext): Add zbs.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> ---
>
> Changes in v3:
> - Updated to 1.0.0 specification and rebased to master
>
> bfd/elfxx-riscv.c | 1 +
> gas/config/tc-riscv.c | 3 +++
> gas/testsuite/gas/riscv/b-ext-64.d | 18 +++++++++++++++++-
> gas/testsuite/gas/riscv/b-ext-64.s | 16 ++++++++++++++++
> gas/testsuite/gas/riscv/b-ext.d | 14 +++++++++++++-
> gas/testsuite/gas/riscv/b-ext.s | 12 ++++++++++++
> include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 9 +++++++++
> 9 files changed, 96 insertions(+), 2 deletions(-)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 39a7d693469..cdb4fa0996a 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1145,6 +1145,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index e7b733a4e6d..f7e0c929aa0 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -283,6 +283,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
> case INSN_CLASS_ZBC:
> return riscv_subset_supports ("zbc");
>
> + case INSN_CLASS_ZBS:
> + return riscv_subset_supports ("zbs");
> +
> default:
> as_fatal ("internal: unreachable");
> return false;
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
> index f4a7abf02d7..339fa20a367 100644
> --- a/gas/testsuite/gas/riscv/b-ext-64.d
> +++ b/gas/testsuite/gas/riscv/b-ext-64.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv64i_zba_zbb_zbc
> +#as: -march=rv64i_zba_zbb_zbc_zbs
> #source: b-ext-64.s
> #objdump: -d
>
> @@ -46,3 +46,19 @@ Disassembly of section .text:
> [ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
> [ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
> [ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
> +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
> index c3ac377f4bd..8ceb2b4fd1c 100644
> --- a/gas/testsuite/gas/riscv/b-ext-64.s
> +++ b/gas/testsuite/gas/riscv/b-ext-64.s
> @@ -37,3 +37,19 @@ target:
> add.uw a0, a1, a2
> zext.w a0, a1
> slli.uw a0, a1, 2
> + bclri a0, a1, 0
> + bclri a0, a1, 31
> + bseti a0, a1, 0
> + bseti a0, a1, 31
> + binvi a0, a1, 0
> + binvi a0, a1, 31
> + bexti a0, a1, 0
> + bexti a0, a1, 31
> + bclri a0, a1, 63
> + bseti a0, a1, 63
> + binvi a0, a1, 63
> + bexti a0, a1, 63
> + bclr a0, a1, a2
> + bset a0, a1, a2
> + binv a0, a1, a2
> + bext a0, a1, a2
> diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
> index 7410796a3b7..748c218fdd0 100644
> --- a/gas/testsuite/gas/riscv/b-ext.d
> +++ b/gas/testsuite/gas/riscv/b-ext.d
> @@ -1,4 +1,4 @@
> -#as: -march=rv32i_zba_zbb_zbc
> +#as: -march=rv32i_zba_zbb_zbc_zbs
> #source: b-ext.s
> #objdump: -d
>
> @@ -33,3 +33,15 @@ Disassembly of section .text:
> [ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
> [ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
> [ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
> index 051dafd1719..a13a797f0dc 100644
> --- a/gas/testsuite/gas/riscv/b-ext.s
> +++ b/gas/testsuite/gas/riscv/b-ext.s
> @@ -24,3 +24,15 @@ target:
> clmul a0, a1, a2
> clmulh a0, a1, a2
> clmulr a0, a1, a2
> + bclri a0, a1, 0
> + bclri a0, a1, 31
> + bseti a0, a1, 0
> + bseti a0, a1, 31
> + binvi a0, a1, 0
> + binvi a0, a1, 31
> + bexti a0, a1, 0
> + bexti a0, a1, 31
> + bclr a0, a1, a2
> + bset a0, a1, a2
> + binv a0, a1, a2
> + bext a0, a1, a2
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 9999da6241a..45a207da0cd 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -495,6 +495,22 @@
> #define MASK_CLMULH 0xfe00707f
> #define MATCH_CLMULR 0xa002033
> #define MASK_CLMULR 0xfe00707f
> +#define MATCH_BCLRI 0x48001013
> +#define MASK_BCLRI 0xfc00707f
> +#define MATCH_BSETI 0x28001013
> +#define MASK_BSETI 0xfc00707f
> +#define MATCH_BINVI 0x68001013
> +#define MASK_BINVI 0xfc00707f
> +#define MATCH_BEXTI 0x48005013
> +#define MASK_BEXTI 0xfc00707f
> +#define MATCH_BCLR 0x48001033
> +#define MASK_BCLR 0xfe00707f
> +#define MATCH_BSET 0x28001033
> +#define MASK_BSET 0xfe00707f
> +#define MATCH_BINV 0x68001033
> +#define MASK_BINV 0xfe00707f
> +#define MATCH_BEXT 0x48005033
> +#define MASK_BEXT 0xfe00707f
> #define MATCH_FLW 0x2007
> #define MASK_FLW 0x707f
> #define MATCH_FLD 0x3007
> @@ -1102,6 +1118,14 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
> DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
> DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
> DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
> +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
> +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
> +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
> +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
> +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
> +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
> +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
> +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
> DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
> DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
> DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index a8f47419f75..afcd41ff1dd 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -319,6 +319,7 @@ enum riscv_insn_class
> INSN_CLASS_ZBA,
> INSN_CLASS_ZBB,
> INSN_CLASS_ZBC,
> + INSN_CLASS_ZBS,
> };
>
> /* This structure holds information for a particular instruction. */
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index e0621503b79..1a4c9f0e4fe 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -833,6 +833,15 @@ const struct riscv_opcode riscv_opcodes[] =
> {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
>
> +/* Zbs instructions */
> +{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
> +{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
> +{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
> +{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
> +{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
> +{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
> +{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
> +{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
>
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 3/4] RISC-V: Add support for Zbs instructions
2021-10-06 20:26 ` [PATCH v3 3/4] RISC-V: Add support for Zbs instructions Philipp Tomsich
2021-10-07 4:02 ` Nelson Chu
@ 2021-10-07 6:57 ` Jan Beulich
2021-10-07 11:51 ` Delivery delayed:Re: " postmaster
1 sibling, 1 reply; 17+ messages in thread
From: Jan Beulich @ 2021-10-07 6:57 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Kito Cheng, Jim Wilson, binutils
On 06.10.2021 22:26, Philipp Tomsich wrote:
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -833,6 +833,15 @@ const struct riscv_opcode riscv_opcodes[] =
> {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
>
> +/* Zbs instructions */
> +{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 },
> +{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 },
> +{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
> +{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
To be consistent with other insns with immediate operands, shouldn't all
of these have aliases without the i suffix?
Jan
> +{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
> +{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
> +{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
> +{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
>
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Delivery delayed:Re: [PATCH v3 3/4] RISC-V: Add support for Zbs instructions
2021-10-07 6:57 ` Jan Beulich
@ 2021-10-07 11:51 ` postmaster
0 siblings, 0 replies; 17+ messages in thread
From: postmaster @ 2021-10-07 11:51 UTC (permalink / raw)
To: binutils
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Subject: Re: [PATCH v3 3/4] RISC-V: Add support for Zbs instructions
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-06 20:26 [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Philipp Tomsich
2021-10-06 20:26 ` [PATCH v3 2/4] RISC-V: Update extension version for Zb[abc] to 1.0.0 Philipp Tomsich
2021-10-06 20:26 ` [PATCH v3 3/4] RISC-V: Add support for Zbs instructions Philipp Tomsich
@ 2021-10-06 20:26 ` Philipp Tomsich
2021-10-07 4:05 ` Nelson Chu
2021-10-07 6:58 ` Jan Beulich
2021-10-07 4:01 ` [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Nelson Chu
3 siblings, 2 replies; 17+ messages in thread
From: Philipp Tomsich @ 2021-10-06 20:26 UTC (permalink / raw)
To: binutils; +Cc: Kito Cheng, Jim Wilson, Jan Beulich, Philipp Tomsich
Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
yencode the respective immediate insn b{set,clr,inv,ext}i when the
second source operand is an immediate.
2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
gas/
* testsuite/gas/riscv/b-ext.d: Add tests.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext-64.s: Likewise.
opcodes/
* riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
Suggested-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
(no changes since v2)
Changes in v2:
- Add aliases for the b{set,clr,inv,ext} when called with an immediate
as a second source operand.
gas/testsuite/gas/riscv/b-ext-64.d | 8 ++++++++
gas/testsuite/gas/riscv/b-ext-64.s | 9 +++++++++
gas/testsuite/gas/riscv/b-ext.d | 4 ++++
gas/testsuite/gas/riscv/b-ext.s | 5 +++++
opcodes/riscv-opc.c | 4 ++++
5 files changed, 30 insertions(+)
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
index 339fa20a367..9b6e6b7ab2a 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.d
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -62,3 +62,11 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
+[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
index 8ceb2b4fd1c..57e501e9a41 100644
--- a/gas/testsuite/gas/riscv/b-ext-64.s
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -53,3 +53,12 @@ target:
bset a0, a1, a2
binv a0, a1, a2
bext a0, a1, a2
+ #aliases
+ bclr a0, a1, 31
+ bset a0, a1, 31
+ binv a0, a1, 31
+ bext a0, a1, 31
+ bclr a0, a1, 63
+ bset a0, a1, 63
+ binv a0, a1, 63
+ bext a0, a1, 63
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
index 748c218fdd0..c1c5f918a84 100644
--- a/gas/testsuite/gas/riscv/b-ext.d
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -45,3 +45,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
+[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
index a13a797f0dc..9de3fc32806 100644
--- a/gas/testsuite/gas/riscv/b-ext.s
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -36,3 +36,8 @@ target:
bset a0, a1, a2
binv a0, a1, a2
bext a0, a1, a2
+ #aliases
+ bclr a0, a1, 31
+ bset a0, a1, 31
+ binv a0, a1, 31
+ bext a0, a1, 31
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1a4c9f0e4fe..b756bae64ab 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -839,9 +839,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
+{"bclr", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
+{"bset", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
+{"binv", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
+{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-06 20:26 ` [PATCH v3 4/4] RISC-V: Support aliases " Philipp Tomsich
@ 2021-10-07 4:05 ` Nelson Chu
2021-10-07 6:58 ` Jan Beulich
1 sibling, 0 replies; 17+ messages in thread
From: Nelson Chu @ 2021-10-07 4:05 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Binutils, Kito Cheng
LGTM. Do you have binutils write access? If so, then please commit
the four rvb patches when you think it is time. Or let me know if you
don't have, I can commit the patches. Anyway, Thanks for helping the
rvb stuff, we do need these.
Nelson
On Thu, Oct 7, 2021 at 4:28 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
> yencode the respective immediate insn b{set,clr,inv,ext}i when the
> second source operand is an immediate.
>
> 2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> gas/
> * testsuite/gas/riscv/b-ext.d: Add tests.
> * testsuite/gas/riscv/b-ext.s: Likewise.
> * testsuite/gas/riscv/b-ext-64.d: Likewise.
> * testsuite/gas/riscv/b-ext-64.s: Likewise.
> opcodes/
> * riscv-opc.c (riscv_opcodes): Add aliases for Zbs.
>
> Suggested-by: Jan Beulich <jbeulich@suse.com>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Add aliases for the b{set,clr,inv,ext} when called with an immediate
> as a second source operand.
>
> gas/testsuite/gas/riscv/b-ext-64.d | 8 ++++++++
> gas/testsuite/gas/riscv/b-ext-64.s | 9 +++++++++
> gas/testsuite/gas/riscv/b-ext.d | 4 ++++
> gas/testsuite/gas/riscv/b-ext.s | 5 +++++
> opcodes/riscv-opc.c | 4 ++++
> 5 files changed, 30 insertions(+)
>
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
> index 339fa20a367..9b6e6b7ab2a 100644
> --- a/gas/testsuite/gas/riscv/b-ext-64.d
> +++ b/gas/testsuite/gas/riscv/b-ext-64.d
> @@ -62,3 +62,11 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f
> +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f
> diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
> index 8ceb2b4fd1c..57e501e9a41 100644
> --- a/gas/testsuite/gas/riscv/b-ext-64.s
> +++ b/gas/testsuite/gas/riscv/b-ext-64.s
> @@ -53,3 +53,12 @@ target:
> bset a0, a1, a2
> binv a0, a1, a2
> bext a0, a1, a2
> + #aliases
> + bclr a0, a1, 31
> + bset a0, a1, 31
> + binv a0, a1, 31
> + bext a0, a1, 31
> + bclr a0, a1, 63
> + bset a0, a1, 63
> + binv a0, a1, 63
> + bext a0, a1, 63
> diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
> index 748c218fdd0..c1c5f918a84 100644
> --- a/gas/testsuite/gas/riscv/b-ext.d
> +++ b/gas/testsuite/gas/riscv/b-ext.d
> @@ -45,3 +45,7 @@ Disassembly of section .text:
> [ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2
> [ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f
> +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f
> diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
> index a13a797f0dc..9de3fc32806 100644
> --- a/gas/testsuite/gas/riscv/b-ext.s
> +++ b/gas/testsuite/gas/riscv/b-ext.s
> @@ -36,3 +36,8 @@ target:
> bset a0, a1, a2
> binv a0, a1, a2
> bext a0, a1, a2
> + #aliases
> + bclr a0, a1, 31
> + bset a0, a1, 31
> + binv a0, a1, 31
> + bext a0, a1, 31
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 1a4c9f0e4fe..b756bae64ab 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -839,9 +839,13 @@ const struct riscv_opcode riscv_opcodes[] =
> {"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 },
> {"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 },
> {"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 },
> +{"bclr", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, INSN_ALIAS },
> {"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 },
> +{"bset", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, INSN_ALIAS },
> {"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 },
> +{"binv", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, INSN_ALIAS },
> {"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 },
> +{"bext", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, INSN_ALIAS },
>
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-06 20:26 ` [PATCH v3 4/4] RISC-V: Support aliases " Philipp Tomsich
2021-10-07 4:05 ` Nelson Chu
@ 2021-10-07 6:58 ` Jan Beulich
2021-10-07 9:13 ` Nelson Chu
2021-10-07 11:06 ` Delivery delayed:Re: " postmaster
1 sibling, 2 replies; 17+ messages in thread
From: Jan Beulich @ 2021-10-07 6:58 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Kito Cheng, Jim Wilson, binutils
On 06.10.2021 22:26, Philipp Tomsich wrote:
> Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
> yencode the respective immediate insn b{set,clr,inv,ext}i when the
> second source operand is an immediate.
Oh, sorry - here the aliases get added. Should have looked at all the
titles first ...
Jan
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-07 6:58 ` Jan Beulich
@ 2021-10-07 9:13 ` Nelson Chu
2021-10-27 23:54 ` Vineet Gupta
2021-10-07 11:06 ` Delivery delayed:Re: " postmaster
1 sibling, 1 reply; 17+ messages in thread
From: Nelson Chu @ 2021-10-07 9:13 UTC (permalink / raw)
To: Jan Beulich; +Cc: Philipp Tomsich, Kito Cheng, Binutils
On Thu, Oct 7, 2021 at 2:59 PM Jan Beulich via Binutils
<binutils@sourceware.org> wrote:
>
> On 06.10.2021 22:26, Philipp Tomsich wrote:
> > Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
> > yencode the respective immediate insn b{set,clr,inv,ext}i when the
> > second source operand is an immediate.
>
> Oh, sorry - here the aliases get added. Should have looked at all the
> titles first ...
Hi Jan,
Thanks for confirming this.
Hi Philipp,
Thanks for helping with this, the series of patches looks good and we
do need these. Committed.
Nelson
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-07 9:13 ` Nelson Chu
@ 2021-10-27 23:54 ` Vineet Gupta
2021-10-28 2:28 ` Nelson Chu
0 siblings, 1 reply; 17+ messages in thread
From: Vineet Gupta @ 2021-10-27 23:54 UTC (permalink / raw)
To: Nelson Chu, Jan Beulich; +Cc: Kito Cheng, Binutils, Philipp Tomsich, Jim Wilson
Hi Nelson, Kito, Jim
On 10/7/21 2:13 AM, Nelson Chu wrote:
> On Thu, Oct 7, 2021 at 2:59 PM Jan Beulich via Binutils
> <binutils@sourceware.org> wrote:
>>
>> On 06.10.2021 22:26, Philipp Tomsich wrote:
>>> Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to
>>> yencode the respective immediate insn b{set,clr,inv,ext}i when the
>>> second source operand is an immediate.
>>
>> Oh, sorry - here the aliases get added. Should have looked at all the
>> titles first ...
>
> Hi Jan,
>
> Thanks for confirming this.
>
> Hi Philipp,
>
> Thanks for helping with this, the series of patches looks good and we
> do need these. Committed.
Will it be possible to backport these 4 patches to
upstream/user/riscv/binutils-integration-branch.
That way it becomes a single place where we could use all bleeding edge
features rather than downstream users/companies having to maintain forks ?
Thx,
-Vineet
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-27 23:54 ` Vineet Gupta
@ 2021-10-28 2:28 ` Nelson Chu
2021-10-28 3:24 ` Vineet Gupta
0 siblings, 1 reply; 17+ messages in thread
From: Nelson Chu @ 2021-10-28 2:28 UTC (permalink / raw)
To: Vineet Gupta
Cc: Jan Beulich, Kito Cheng, Binutils, Philipp Tomsich, Jim Wilson
Hi Vineet,
On Thu, Oct 28, 2021 at 7:54 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>
> Hi Nelson, Kito, Jim
>
> Will it be possible to backport these 4 patches to
> upstream/user/riscv/binutils-integration-branch.
I have rebased the integration branch until 20211027, so it should
include the v1.0 zba, zbb, zbc and zbs extensions for now.
> That way it becomes a single place where we could use all bleeding edge
> features rather than downstream users/companies having to maintain forks ?
Yes, this is the main purpose of the integration branch. However, I'm
thinking about how to make maintenance more convenient for everyone,
both in the mainline and integration branch. Perhaps it will be
better that we move the released vendor stuff from the integration
branch to the mainline, so that all the released things are maintained
in the mainline, and they should be stable enough and must consider
the compatible issues. But for the integration branch, it will only
have the purpose of temporarily putting the draft extensions, maybe we
could also try to move them back to mainline, just that we could drop
the draft things directly once they are updated. In other words, we
only keep the implementation of the extensions if their versions are
at least v1.0 (released), otherwise, we could drop them (< v1.0) and
always keep the newest one.
Thanks
Nelson
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-28 2:28 ` Nelson Chu
@ 2021-10-28 3:24 ` Vineet Gupta
2021-10-28 8:08 ` Kito Cheng
0 siblings, 1 reply; 17+ messages in thread
From: Vineet Gupta @ 2021-10-28 3:24 UTC (permalink / raw)
To: Nelson Chu; +Cc: Jan Beulich, Kito Cheng, Binutils, Philipp Tomsich, Jim Wilson
Hi Nelson,
On 10/27/21 7:28 PM, Nelson Chu wrote:
> Hi Vineet,
>
> On Thu, Oct 28, 2021 at 7:54 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>> Hi Nelson, Kito, Jim
>>
>> Will it be possible to backport these 4 patches to
>> upstream/user/riscv/binutils-integration-branch.
> I have rebased the integration branch until 20211027, so it should
> include the v1.0 zba, zbb, zbc and zbs extensions for now.
Awesome, thx for that. I saw earlier that it has vector stuff in there
too - Last month Jim had some concerns [1] about vector support in gcc,
how is that coming along ?
>> That way it becomes a single place where we could use all bleeding edge
>> features rather than downstream users/companies having to maintain forks ?
> Yes, this is the main purpose of the integration branch. However, I'm
> thinking about how to make maintenance more convenient for everyone,
> both in the mainline and integration branch. Perhaps it will be
> better that we move the released vendor stuff from the integration
> branch to the mainline, so that all the released things are maintained
> in the mainline, and they should be stable enough and must consider
> the compatible issues.
Totally agree.
> But for the integration branch, it will only
> have the purpose of temporarily putting the draft extensions, maybe we
> could also try to move them back to mainline, just that we could drop
> the draft things directly once they are updated. In other words, we
> only keep the implementation of the extensions if their versions are
> at least v1.0 (released), otherwise, we could drop them (< v1.0) and
> always keep the newest one.
Great, I'd say we run with this approach.
Thx,
-Vineet
[1] https://sourceware.org/pipermail/libc-alpha/2021-September/131051.html
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-28 3:24 ` Vineet Gupta
@ 2021-10-28 8:08 ` Kito Cheng
0 siblings, 0 replies; 17+ messages in thread
From: Kito Cheng @ 2021-10-28 8:08 UTC (permalink / raw)
To: Vineet Gupta
Cc: Nelson Chu, Jan Beulich, Binutils, Philipp Tomsich, Jim Wilson
Hi Vineet:
> Awesome, thx for that. I saw earlier that it has vector stuff in there
> too - Last month Jim had some concerns [1] about vector support in gcc,
> how is that coming along ?
My plan is only to add minimal support for RVV on GCC before next GCC release,
As Jim mentioned we didn't invest RVV intrinsic function on GCC, but
for glibc support,
that only requires minimal support on GCC.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Delivery delayed:Re: [PATCH v3 4/4] RISC-V: Support aliases for Zbs instructions
2021-10-07 6:58 ` Jan Beulich
2021-10-07 9:13 ` Nelson Chu
@ 2021-10-07 11:06 ` postmaster
1 sibling, 0 replies; 17+ messages in thread
From: postmaster @ 2021-10-07 11:06 UTC (permalink / raw)
To: binutils
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To: Philipp Tomsich <philipp.tomsich@vrull.eu>
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=?utf-8?B?VXdrc0dST0JscVZpd25qcWdidU1PckY4MUZXTE1HUVVEZGZUUXBqOU1SNmNj?=
=?utf-8?B?cllnUGdEZXVKcjBmaC9BVm12T3NiQVRabTlaUHVDakZJOFJncFBnL2dUVjFP?=
=?utf-8?B?dkpKUFNHTk5hdkk4L09VdnkwZlVPNFFoV2hONFdiRHV3em1nQ1YvTllta0ZO?=
=?utf-8?B?MlJNOWhXdDk3b3RTbVJGSmZMY29kdm1iSjlnVGZiU0h3NVN4NEtDM0M2S0t0?=
=?utf-8?B?a25KNzBrOERqVkJ3UHpOTHRYVk9uTXUwYWdvL3I3TXlvSWJsR1dROWU2QWt3?=
=?utf-8?B?a3FjYVlDR0Npam5McFFQM0J6dlJpZEwwL2FSczZrbDB0ZTRtd2ZwZ1JXOGVY?=
=?utf-8?B?bk1zbTR6bEN0RjNISFpiNURVN3pOeURYcy9RMVFKRTRoa2ZnbVJhRmc2R3Bl?=
=?utf-8?B?RDZPVWtzQjUxWlZydXhqMG5GREpRWXQycDZEOVN2Nmx6VXNINXZWWUM5ZHlE?=
=?utf-8?B?SE9pWURTQlVKck5EZzhhbjlubytBbWpXLzVDSUxWdUw5cjlsU0NGbjhhaGNt?=
=?utf-8?B?amtNRGNROXYwNnlSSHlNbVhrdS9QSkhTZ2gyNEwyRG5zZWtMUndCZjlwYkdE?=
=?utf-8?B?Y09uQ3dJRXV3U1FMT2h3dFdUM3dvbDNQaDFVWHB3dFZmN21TYmtEUjZFMkd5?=
=?utf-8?B?TzlrMEJOd0dXaEwrLzBvdE9XakZGQ2w4anhaVzRJcHpMcmZ4bGt4SFY3Nm1E?=
=?utf-8?B?bVg0UGIyQjlmdndPRU93VGV0THl3WnI0cDRZV1ljTTFucjJBbTRQVkZaUnNo?=
=?utf-8?B?Z0FPQlZKTEtPMTRDbzRaT2l4eVYrdnJXLzRMUkMyQ1JYcmxuaGtPTDVHQXdD?=
=?utf-8?B?cXNDSVZWenNqRllnMVRCdXMyS08wWDllLzZPLzFqL1hudEp3dFlvSEIvTi9y?=
=?utf-8?B?QTk4UDhoMmNva3BvaVA2OGgvYjRtRzBKU1JhOTV0elNnbDhWSWlxNEh5emk0?=
=?utf-8?B?SkEwQ01nSU41bDIwRXZDanpUNzZKVmg4bDJGSER4bk5FbXBDNVRJR0d6WDdI?=
=?utf-8?B?cnMvQTZqRE5QSFB2blJuZXEwOWZrRE1JN0N6LzZHQXJBRjY0N2dXa3M5WFpQ?=
=?utf-8?B?eDlDOWxtUmtsMzMxbndBbklYTGkyOW53UjhHSXVIUDFEdFFRZjRMOEFGQ3Fx?=
=?utf-8?B?aTlkUU5VZGF5bkxMTVZtRVRKbzFzeTU1d2ZWWDhBT3VjVW9BY0JRWXVtbjZN?=
=?utf-8?B?ZlduenBXZkh6NHNkLytRK3V4elRGOVZTaTlOV0lHWndsNHp6c3pWMkhkTHZB?=
=?utf-8?Q?v7lLb81tWYM2X8xRBhtsWVn78tP7EavjiENLCJ2?=
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* Re: [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections
2021-10-06 20:26 [PATCH v3 1/4] RISC-V: Split Zb[abc] into commented sections Philipp Tomsich
` (2 preceding siblings ...)
2021-10-06 20:26 ` [PATCH v3 4/4] RISC-V: Support aliases " Philipp Tomsich
@ 2021-10-07 4:01 ` Nelson Chu
3 siblings, 0 replies; 17+ messages in thread
From: Nelson Chu @ 2021-10-07 4:01 UTC (permalink / raw)
To: Philipp Tomsich; +Cc: Binutils, Kito Cheng
LGTM, thanks.
Nelson
On Thu, Oct 7, 2021 at 4:27 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The Zb[abc] opcodes are bundled just below the Privileged opcodes in
> riscv_opcodes, possibly giving the appearance that they are part of
> the Privileged spec for an uninitiated reader. This separates them
> out and adds comments above each section to clearly identify them as
> Zba, Zbb or Zbc opcodes.
>
> 2021-10-04 Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> opcodes/
> * riscv-opc.c: Split of Zb[abc] instructions and add comments.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> ---
>
> Changes in v3:
> - Added patch to regroup/add comments for instructions in riscv-opc.c
>
> opcodes/riscv-opc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index f55a01b071c..e0621503b79 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -782,6 +782,8 @@ const struct riscv_opcode riscv_opcodes[] =
> {"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS },
> {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
> {"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
> +
> +/* Zbb instructions */
> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
> {"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
> @@ -813,6 +815,8 @@ const struct riscv_opcode riscv_opcodes[] =
> {"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> {"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
> {"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
> +
> +/* Zba instructions */
> {"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
> {"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
> {"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
> @@ -823,6 +827,8 @@ const struct riscv_opcode riscv_opcodes[] =
> {"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
> {"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
> {"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
> +
> +/* Zbc instructions */
> {"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
> {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
> {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread