* [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc
@ 2020-03-04 5:08 Nelson Chu
2020-03-04 5:08 ` [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to " Nelson Chu
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Nelson Chu @ 2020-03-04 5:08 UTC (permalink / raw)
To: binutils, jimw, jrtc27; +Cc: kito.cheng, palmerdabbelt
Hi Jim,
I appreciate your help very much :) I also do some minor changes for the
examples, and add the missing right parenthesis and dot.
And I should need to take an English writing grammar class recently... QAQ
Thanks
Nelson
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to as doc. 2020-03-04 5:08 [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Nelson Chu @ 2020-03-04 5:08 ` Nelson Chu 2020-03-04 5:08 ` [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi Nelson Chu 2020-03-05 1:15 ` [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Jim Wilson 2 siblings, 0 replies; 7+ messages in thread From: Nelson Chu @ 2020-03-04 5:08 UTC (permalink / raw) To: binutils, jimw, jrtc27; +Cc: kito.cheng, palmerdabbelt gas/ * doc/c-riscv.texi (relocation modifiers): Add documentation. (RISC-V-Formats): Update the section name from "Instruction Formats" to "RISC-V Instruction Formats". --- gas/doc/c-riscv.texi | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 599b5cf..6e932dc 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -17,6 +17,7 @@ @menu * RISC-V-Options:: RISC-V Options * RISC-V-Directives:: RISC-V Directives +* RISC-V-Modifiers:: RISC-V Assembler Modifiers * RISC-V-Formats:: RISC-V Instruction Formats * RISC-V-ATTRIBUTE:: RISC-V Object Attribute @end menu @@ -207,8 +208,117 @@ The @var{tag} is either an attribute number, or one of the following: @end table +@node RISC-V-Modifiers +@section RISC-V Assembler Modifiers + +The RISC-V assembler supports following modifiers for relocatable addresses +used in RISC-V instruction operands. However, we also support some pseudo +instructions that are easier to use than these modifiers. + +@table @code +@item %lo(@var{symbol}) +The low 12 bits of absolute address for @var{symbol}. + +@item %hi(@var{symbol}) +The high 20 bits of absolute address for @var{symbol}. This is usually +used with the %lo modifier to represent a 32-bit absolute address. + +@smallexample + lui a0, %hi(@var{symbol}) // R_RISCV_HI20 + addi a0, a0, %lo(@var{symbol}) // R_RISCV_LO12_I + + lui a0, %hi(@var{symbol}) // R_RISCV_HI20 + load/store a0, %lo(@var{symbol})(a0) // R_RISCV_LO12_I/S +@end smallexample + +@item %pcrel_lo(@var{label}) +The low 12 bits of relative address between pc and @var{symbol}. +The @var{symbol} is related to the high part instruction which is marked +by @var{label}. + +@item %pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and @var{symbol}. +This is usually used with the %pcrel_lo modifier to represent a +/-2GB +pc-relative range. + +@smallexample +@var{label}: + auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I + +@var{label}: + auipc a0, %pcrel_hi(@var{symbol}) // R_RISCV_PCREL_HI20 + load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S +@end smallexample + +Or you can use the pseudo lla/lw/sw/... instruction to do this. + +@smallexample + lla a0, @var{symbol} +@end smallexample + +@item %tprel_add(@var{symbol}) +This is used purely to associate the R_RISCV_TPREL_ADD relocation for +TLS relaxation. This one is only valid as the fourth operand to the normally +3 operand add instruction. + +@item %tprel_lo(@var{symbol}) +The low 12 bits of relative address between tp and @var{symbol}. + +@item %tprel_hi(@var{symbol}) +The high 20 bits of relative address between tp and @var{symbol}. This is +usually used with the %tprel_lo and %tprel_add modifiers to access the thread +local variable @var{symbol} in TLS Local Exec. + +@smallexample + lui a5, %tprel_hi(@var{symbol}) // R_RISCV_TPREL_HI20 + add a5, a5, tp, %tprel_add(@var{symbol}) // R_RISCV_TPREL_ADD + load/store t0, %tprel_lo(@var{symbol})(a5) // R_RISCV_TPREL_LO12_I/S +@end smallexample + +@item %tls_ie_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local +variable @var{symbol} in TLS Initial Exec. + +@smallexample + la.tls.ie a5, @var{symbol} + add a5, a5, tp + load/store t0, 0(a5) +@end smallexample + +The pseudo la.tls.ie instruction can be expended to + +@smallexample +@var{label}: + auipc a5, %tls_ie_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GOT_HI20 + load a5, %pcrel_lo(@var{label})(a5) // R_RISCV_PCREL_LO12_I +@end smallexample + +@item %tls_gd_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and GOT entry. It is +usually used with the %pcrel_lo modifier to access the thread local variable +@var{symbol} in TLS Global Dynamic. + +@smallexample + la.tls.gd a0, @var{symbol} + call __tls_get_addr@@plt + mv a5, a0 + load/store t0, 0(a5) +@end smallexample + +The pseudo la.tls.gd instruction can be expended to + +@smallexample +@var{label}: + auipc a0, %tls_gd_pcrel_hi(@var{symbol}) // R_RISCV_TLS_GD_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I +@end smallexample + +@end table + @node RISC-V-Formats -@section Instruction Formats +@section RISC-V Instruction Formats @cindex instruction formats, risc-v @cindex RISC-V instruction formats -- 2.7.4 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 5:08 [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Nelson Chu 2020-03-04 5:08 ` [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to " Nelson Chu @ 2020-03-04 5:08 ` Nelson Chu 2020-03-08 5:46 ` Fangrui Song 2020-03-05 1:15 ` [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Jim Wilson 2 siblings, 1 reply; 7+ messages in thread From: Nelson Chu @ 2020-03-04 5:08 UTC (permalink / raw) To: binutils, jimw, jrtc27; +Cc: kito.cheng, palmerdabbelt gas/ * config/tc-riscv.c: Support the modifier %got_pcrel_hi. * doc/c-riscv.texi: Add documentation. * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new modifier %got_pcrel_hi. * testsuite/gas/riscv/no-relax-reloc.s: Likewise. * testsuite/gas/riscv/relax-reloc.d: Likewise. * testsuite/gas/riscv/relax-reloc.s: Likewise. --- gas/config/tc-riscv.c | 1 + gas/doc/c-riscv.texi | 17 +++++++++++++++++ gas/testsuite/gas/riscv/no-relax-reloc.d | 4 +++- gas/testsuite/gas/riscv/no-relax-reloc.s | 7 +++++-- gas/testsuite/gas/riscv/relax-reloc.d | 7 +++++-- gas/testsuite/gas/riscv/relax-reloc.s | 7 +++++-- 6 files changed, 36 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index ddd4d14..168561e 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] = { {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, + {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, {"%hi", BFD_RELOC_RISCV_HI20}, diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 6e932dc..488cf56 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -257,6 +257,23 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this. lla a0, @var{symbol} @end smallexample +@item %got_pcrel_hi(@var{symbol}) +The high 20 bits of relative address between pc and the GOT entry of +@var{symbol}. This is usually used with the %pcrel_lo modifier to access +the GOT entry. + +@smallexample +@var{label}: + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 + addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I + +@var{label}: + auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 + load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S +@end smallexample + +Also, the pseudo la instruction with PIC has similar behavior. + @item %tprel_add(@var{symbol}) This is used purely to associate the R_RISCV_TPREL_ADD relocation for TLS relaxation. This one is only valid as the fourth operand to the normally diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d index 62f28e0..c2ca1aa 100644 --- a/gas/testsuite/gas/riscv/no-relax-reloc.d +++ b/gas/testsuite/gas/riscv/no-relax-reloc.d @@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .* 0+4 R_RISCV_LO12_I.* 0+8 R_RISCV_PCREL_HI20.* 0+c R_RISCV_PCREL_LO12_I.* -0+10 R_RISCV_CALL.* +0+10 R_RISCV_GOT_HI20.* +0+14 R_RISCV_PCREL_LO12_I.* +0+18 R_RISCV_CALL.* diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s index 7f1a484..2aab995 100644 --- a/gas/testsuite/gas/riscv/no-relax-reloc.s +++ b/gas/testsuite/gas/riscv/no-relax-reloc.s @@ -2,7 +2,10 @@ target: lui a5,%hi(target) lw a5,%lo(target)(a5) - .LA0: auipc a5,%pcrel_hi(bar) - lw a0,%pcrel_lo(.LA0)(a5) + .LA0: auipc a5,%pcrel_hi(symbol1) + lw a0,%pcrel_lo(.LA0)(a5) + + .LA1: auipc a5,%got_pcrel_hi(symbol2) + lw a0,%pcrel_lo(.LA1)(a5) call target diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d index f5f592c..623218e 100644 --- a/gas/testsuite/gas/riscv/relax-reloc.d +++ b/gas/testsuite/gas/riscv/relax-reloc.d @@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .* 0+8 R_RISCV_RELAX.* 0+c R_RISCV_PCREL_LO12_I.* 0+c R_RISCV_RELAX.* -0+10 R_RISCV_CALL.* -0+10 R_RISCV_RELAX.* +0+10 R_RISCV_GOT_HI20.* +0+14 R_RISCV_PCREL_LO12_I.* +0+14 R_RISCV_RELAX.* +0+18 R_RISCV_CALL.* +0+18 R_RISCV_RELAX.* diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s index 7f1a484..2aab995 100644 --- a/gas/testsuite/gas/riscv/relax-reloc.s +++ b/gas/testsuite/gas/riscv/relax-reloc.s @@ -2,7 +2,10 @@ target: lui a5,%hi(target) lw a5,%lo(target)(a5) - .LA0: auipc a5,%pcrel_hi(bar) - lw a0,%pcrel_lo(.LA0)(a5) + .LA0: auipc a5,%pcrel_hi(symbol1) + lw a0,%pcrel_lo(.LA0)(a5) + + .LA1: auipc a5,%got_pcrel_hi(symbol2) + lw a0,%pcrel_lo(.LA1)(a5) call target -- 2.7.4 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-04 5:08 ` [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi Nelson Chu @ 2020-03-08 5:46 ` Fangrui Song 2020-03-09 1:41 ` Nelson Chu 0 siblings, 1 reply; 7+ messages in thread From: Fangrui Song @ 2020-03-08 5:46 UTC (permalink / raw) To: Nelson Chu; +Cc: binutils, jimw, jrtc27, kito.cheng, palmerdabbelt Is "assembler operator" more conventional than "assembler modifier"? On 2020-03-03, Nelson Chu wrote: > gas/ > * config/tc-riscv.c: Support the modifier %got_pcrel_hi. > * doc/c-riscv.texi: Add documentation. > * testsuite/gas/riscv/no-relax-reloc.d: Add test case for the new > modifier %got_pcrel_hi. > * testsuite/gas/riscv/no-relax-reloc.s: Likewise. > * testsuite/gas/riscv/relax-reloc.d: Likewise. > * testsuite/gas/riscv/relax-reloc.s: Likewise. >--- > gas/config/tc-riscv.c | 1 + > gas/doc/c-riscv.texi | 17 +++++++++++++++++ > gas/testsuite/gas/riscv/no-relax-reloc.d | 4 +++- > gas/testsuite/gas/riscv/no-relax-reloc.s | 7 +++++-- > gas/testsuite/gas/riscv/relax-reloc.d | 7 +++++-- > gas/testsuite/gas/riscv/relax-reloc.s | 7 +++++-- > 6 files changed, 36 insertions(+), 7 deletions(-) > >diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c >index ddd4d14..168561e 100644 >--- a/gas/config/tc-riscv.c >+++ b/gas/config/tc-riscv.c >@@ -1308,6 +1308,7 @@ static const struct percent_op_match percent_op_utype[] = > { > {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, > {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, >+ {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, > {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, > {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, > {"%hi", BFD_RELOC_RISCV_HI20}, >diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi >index 6e932dc..488cf56 100644 >--- a/gas/doc/c-riscv.texi >+++ b/gas/doc/c-riscv.texi >@@ -257,6 +257,23 @@ Or you can use the pseudo lla/lw/sw/... instruction to do this. > lla a0, @var{symbol} > @end smallexample > >+@item %got_pcrel_hi(@var{symbol}) >+The high 20 bits of relative address between pc and the GOT entry of >+@var{symbol}. This is usually used with the %pcrel_lo modifier to access >+the GOT entry. >+ >+@smallexample >+@var{label}: >+ auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 >+ addi a0, a0, %pcrel_lo(@var{label}) // R_RISCV_PCREL_LO12_I >+ >+@var{label}: >+ auipc a0, %got_pcrel_hi(@var{symbol}) // R_RISCV_GOT_HI20 >+ load/store a0, %pcrel_lo(@var{label})(a0) // R_RISCV_PCREL_LO12_I/S >+@end smallexample >+ >+Also, the pseudo la instruction with PIC has similar behavior. >+ > @item %tprel_add(@var{symbol}) > This is used purely to associate the R_RISCV_TPREL_ADD relocation for > TLS relaxation. This one is only valid as the fourth operand to the normally >diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.d b/gas/testsuite/gas/riscv/no-relax-reloc.d >index 62f28e0..c2ca1aa 100644 >--- a/gas/testsuite/gas/riscv/no-relax-reloc.d >+++ b/gas/testsuite/gas/riscv/no-relax-reloc.d >@@ -9,4 +9,6 @@ RELOCATION RECORDS FOR .* > 0+4 R_RISCV_LO12_I.* > 0+8 R_RISCV_PCREL_HI20.* > 0+c R_RISCV_PCREL_LO12_I.* >-0+10 R_RISCV_CALL.* >+0+10 R_RISCV_GOT_HI20.* >+0+14 R_RISCV_PCREL_LO12_I.* >+0+18 R_RISCV_CALL.* >diff --git a/gas/testsuite/gas/riscv/no-relax-reloc.s b/gas/testsuite/gas/riscv/no-relax-reloc.s >index 7f1a484..2aab995 100644 >--- a/gas/testsuite/gas/riscv/no-relax-reloc.s >+++ b/gas/testsuite/gas/riscv/no-relax-reloc.s >@@ -2,7 +2,10 @@ target: > lui a5,%hi(target) > lw a5,%lo(target)(a5) > >- .LA0: auipc a5,%pcrel_hi(bar) >- lw a0,%pcrel_lo(.LA0)(a5) >+ .LA0: auipc a5,%pcrel_hi(symbol1) >+ lw a0,%pcrel_lo(.LA0)(a5) >+ >+ .LA1: auipc a5,%got_pcrel_hi(symbol2) >+ lw a0,%pcrel_lo(.LA1)(a5) > > call target >diff --git a/gas/testsuite/gas/riscv/relax-reloc.d b/gas/testsuite/gas/riscv/relax-reloc.d >index f5f592c..623218e 100644 >--- a/gas/testsuite/gas/riscv/relax-reloc.d >+++ b/gas/testsuite/gas/riscv/relax-reloc.d >@@ -13,5 +13,8 @@ RELOCATION RECORDS FOR .* > 0+8 R_RISCV_RELAX.* > 0+c R_RISCV_PCREL_LO12_I.* > 0+c R_RISCV_RELAX.* >-0+10 R_RISCV_CALL.* >-0+10 R_RISCV_RELAX.* >+0+10 R_RISCV_GOT_HI20.* >+0+14 R_RISCV_PCREL_LO12_I.* >+0+14 R_RISCV_RELAX.* >+0+18 R_RISCV_CALL.* >+0+18 R_RISCV_RELAX.* >diff --git a/gas/testsuite/gas/riscv/relax-reloc.s b/gas/testsuite/gas/riscv/relax-reloc.s >index 7f1a484..2aab995 100644 >--- a/gas/testsuite/gas/riscv/relax-reloc.s >+++ b/gas/testsuite/gas/riscv/relax-reloc.s >@@ -2,7 +2,10 @@ target: > lui a5,%hi(target) > lw a5,%lo(target)(a5) > >- .LA0: auipc a5,%pcrel_hi(bar) >- lw a0,%pcrel_lo(.LA0)(a5) >+ .LA0: auipc a5,%pcrel_hi(symbol1) >+ lw a0,%pcrel_lo(.LA0)(a5) >+ >+ .LA1: auipc a5,%got_pcrel_hi(symbol2) >+ lw a0,%pcrel_lo(.LA1)(a5) > > call target ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi. 2020-03-08 5:46 ` Fangrui Song @ 2020-03-09 1:41 ` Nelson Chu 0 siblings, 0 replies; 7+ messages in thread From: Nelson Chu @ 2020-03-09 1:41 UTC (permalink / raw) To: Fangrui Song Cc: Binutils, Jim Wilson, James Clarke, Kito Cheng, Palmer Dabbelt Hi MaskRay, On Sun, Mar 8, 2020 at 1:46 PM Fangrui Song <i@maskray.me> wrote: > > Is "assembler operator" more conventional than "assembler modifier"? > In GNU assembler document, many targets use similar names for these. ARC calls this "Assembler Modifiers", AVR and LM32 call this "Relocatable Expression Modifiers". However, many targets use "Symbolic Operand Modifiers", including M32C, M68HC11(12), RL78, RX, TILE-Gx and TILEPro. I also see CR16 calls this "Operand Qualifiers". For our RISC-V asm manual, we call this "Assembler Relocation Functions". I'm not sure which one is better, but it seems like the "Symbolic Operand Modifiers" is more clear to understand what it means? Thanks Nelson ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc 2020-03-04 5:08 [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Nelson Chu 2020-03-04 5:08 ` [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to " Nelson Chu 2020-03-04 5:08 ` [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi Nelson Chu @ 2020-03-05 1:15 ` Jim Wilson 2020-03-05 3:08 ` Nelson Chu 2 siblings, 1 reply; 7+ messages in thread From: Jim Wilson @ 2020-03-05 1:15 UTC (permalink / raw) To: Nelson Chu; +Cc: Binutils, James Clarke, Kito Cheng, Palmer Dabbelt On Tue, Mar 3, 2020 at 9:08 PM Nelson Chu <nelson.chu@sifive.com> wrote: > I appreciate your help very much :) I also do some minor changes for the > examples, and add the missing right parenthesis and dot. Looks good. I committed and pushed. Jim ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc 2020-03-05 1:15 ` [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Jim Wilson @ 2020-03-05 3:08 ` Nelson Chu 0 siblings, 0 replies; 7+ messages in thread From: Nelson Chu @ 2020-03-05 3:08 UTC (permalink / raw) To: Jim Wilson; +Cc: Binutils, James Clarke, Kito Cheng, Palmer Dabbelt Thanks Jim :) Nelson On Thu, Mar 5, 2020 at 9:15 AM Jim Wilson <jimw@sifive.com> wrote: > > On Tue, Mar 3, 2020 at 9:08 PM Nelson Chu <nelson.chu@sifive.com> wrote: > > I appreciate your help very much :) I also do some minor changes for the > > examples, and add the missing right parenthesis and dot. > > Looks good. I committed and pushed. > > Jim ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-03-09 1:41 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-03-04 5:08 [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Nelson Chu 2020-03-04 5:08 ` [PATCH v2 1/2] RISC-V: Add description for RISC-V Modifiers to " Nelson Chu 2020-03-04 5:08 ` [PATCH v2 2/2] RISC-V: Support assembler modifier %got_pcrel_hi Nelson Chu 2020-03-08 5:46 ` Fangrui Song 2020-03-09 1:41 ` Nelson Chu 2020-03-05 1:15 ` [PATCH v2 0/2] Add description for the RISC-V relocatable modifiers in as doc Jim Wilson 2020-03-05 3:08 ` Nelson Chu
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