From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe31.google.com (mail-vs1-xe31.google.com [IPv6:2607:f8b0:4864:20::e31]) by sourceware.org (Postfix) with ESMTPS id 269773858D3C for ; Wed, 20 Apr 2022 01:37:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 269773858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-vs1-xe31.google.com with SMTP id b128so206572vsc.13 for ; Tue, 19 Apr 2022 18:37:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Dcn5Vf7RlSHws/4uK6dwOFuiKSY/WyX7a13V4scfwJ8=; b=FuZkfEyEVWYAd4Oh4+OOlpaqtgI2nJI5mTi2AiFd1vJxwFGV5FYEOfnnJ/4ZeLUuzT lVPhXW7F/4Pw5COuXb3VkteKAdRjgLs///Vjrsn0nFdnQH8BWtepVbxwRYQ7lo7Lg9Lh PH75+jrJIs6FJ/V6uGU9cnoxD54Xoi2wCBjvg0/XXSDuHxRvpVQdiqKHWtb6i1VWfXlG b8IjMWzbeT38s2l5JJlgLaxUw7wJABVebkmTlHkXosNMJxzf050ph41xRpk/FavHcngy 3mSXmbVGneaaQeWlOYhwIvwqOm+XncoB0nIjXlRexOCJHIOkYXcWrEkpE0E3uMouFIup znNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Dcn5Vf7RlSHws/4uK6dwOFuiKSY/WyX7a13V4scfwJ8=; b=axpGwGm/taqJ9ora+ZA9neTiGavzo24aL90wU0N8Nh4QjQbpl7cEouMmE+jmxiHeYn j5/eQIYkCLsdTzOO08h8X5PF4SvD8dKZ4ANBu8nSQPV3XSlX4s3qUGPR6upKBxmPh32X 79xBeMrK4+HV9w513AA9leLpYt/e+VL6iNsjJgM5LyXt4NR3GoYGWl81Vn+z013Yo32R +y+IfiPU/GKGrQX+Bb03WWz8MZ6zhKCW1dJLKyVSOPCPfCqmolS7oPa/DPdJcGbSwbP1 w94BkPBpZPoTBtPs3OEGS553ptMYzIZsNc6rk2TaswtN9z875+w9qWWpHc1WKdN9hsiS dqRQ== X-Gm-Message-State: AOAM533p7gwn/UDRcz3CB+xxBOdK95NWY5b3O+UrgLzIXEAHf4QpH4bG uPMjFERs3XaK0JswprG5wwdKddmTJ56GHd85zk8mOr755FvbCw== X-Google-Smtp-Source: ABdhPJxDC3ALdkG3wUzL9fOGzskPxRx6F3uiM4erOmj3wZxa9BPTkb2hcN+nhaUySQ7eCjUyQ8QlH9Lofcva69V2+AE= X-Received: by 2002:a67:f1d9:0:b0:32a:2056:7598 with SMTP id v25-20020a67f1d9000000b0032a20567598mr6130502vsm.83.1650418629345; Tue, 19 Apr 2022 18:37:09 -0700 (PDT) MIME-Version: 1.0 References: <20220419235137.345598-1-patrick@rivosinc.com> In-Reply-To: <20220419235137.345598-1-patrick@rivosinc.com> From: Nelson Chu Date: Wed, 20 Apr 2022 09:37:00 +0800 Message-ID: Subject: Re: [PATCH] RISCV: Add T-Head Cache Instructions To: "Patrick O'Neill" Cc: Binutils , Lifang Xia , Lifang Xia Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Apr 2022 01:37:12 -0000 Hi Patrick, I believe these are parts of the t-head extensions, and we should have fully supported them in the users/riscv/binutils-integration-branch branch. Just that I still don't have time to move the vendor frameworks and stuff from there back to master. I am not sure if supporting the vendor extensions in master is urgent or not. But if the t-head cache stuff are, then I personally hope the patch should at least add Lifang Xia as the (main) author, and get his/their approval since these are vendor extensions, which ideally should be mainly maintained by each vendor. BTW, moving the existing whole t-head extension back to master rather than parts of them should be better to me. Thanks Nelson On Wed, Apr 20, 2022 at 7:52 AM Patrick O'Neill wrote: > > Add the cache instructions as described in Appendix B-1 of the XaunTie > Cseries Instruction Manual. > https://github.com/rjiejie/XuanTie-doc/blob/master/XuanTieCseriesinstructionmanual.pdf > > This extension can be enabled by including "_xtheadcache" in the -march > string. > > Signed-off-by: Patrick O'Neill > --- > bfd/elfxx-riscv.c | 11 +++- > gas/testsuite/gas/riscv/xtheadcache-ext.d | 31 +++++++++++ > gas/testsuite/gas/riscv/xtheadcache-ext.s | 22 ++++++++ > include/opcode/riscv-opc.h | 64 +++++++++++++++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 23 ++++++++ > 6 files changed, 150 insertions(+), 2 deletions(-) > create mode 100644 gas/testsuite/gas/riscv/xtheadcache-ext.d > create mode 100644 gas/testsuite/gas/riscv/xtheadcache-ext.s > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 9f52bb545a..d10611cb60 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1225,6 +1225,12 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {NULL, 0, 0, 0, 0} > }; > > +static struct riscv_supported_ext riscv_supported_std_x_ext[] = > +{ > + {"xtheadcache", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {NULL, 0, 0, 0, 0} > +}; > + > static struct riscv_supported_ext riscv_supported_std_s_ext[] = > { > {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > @@ -1513,8 +1519,7 @@ riscv_get_default_ext_version (enum riscv_spec_class *default_isa_spec, > case RV_ISA_CLASS_Z: table = riscv_supported_std_z_ext; break; > case RV_ISA_CLASS_S: table = riscv_supported_std_s_ext; break; > case RV_ISA_CLASS_H: table = riscv_supported_std_h_ext; break; > - case RV_ISA_CLASS_X: > - break; > + case RV_ISA_CLASS_X: table = riscv_supported_std_x_ext; break; > default: > table = riscv_supported_std_ext; > } > @@ -2408,6 +2413,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, > || riscv_subset_supports (rps, "zve32f")); > case INSN_CLASS_SVINVAL: > return riscv_subset_supports (rps, "svinval"); > + case INSN_CLASS_XTHEADCACHE: > + return riscv_subset_supports (rps, "xtheadcache"); > default: > rps->error_handler > (_("internal: unreachable INSN_CLASS_*")); > diff --git a/gas/testsuite/gas/riscv/xtheadcache-ext.d b/gas/testsuite/gas/riscv/xtheadcache-ext.d > new file mode 100644 > index 0000000000..c0f47f65e5 > --- /dev/null > +++ b/gas/testsuite/gas/riscv/xtheadcache-ext.d > @@ -0,0 +1,31 @@ > +#as: -march=rv64i_xtheadcache > +#source: xtheadcache-ext.s > +#objdump: -d > + > +.*:[ ]+file format .* > + > + > +Disassembly of section .text: > + > +0+000 : > +[ ]+0:[ ]+0010000b[ ]+dcache.call > +[ ]+4:[ ]+0030000b[ ]+dcache.ciall > +[ ]+8:[ ]+02b5000b[ ]+dcache.cipa[ ]+a0 > +[ ]+c:[ ]+0235000b[ ]+dcache.cisw[ ]+a0 > +[ ]+10:[ ]+0275000b[ ]+dcache.civa[ ]+a0 > +[ ]+14:[ ]+0295000b[ ]+dcache.cpa[ ]+a0 > +[ ]+18:[ ]+0285000b[ ]+dcache.cpal1[ ]+a0 > +[ ]+1c:[ ]+0255000b[ ]+dcache.cva[ ]+a0 > +[ ]+20:[ ]+0245000b[ ]+dcache.cval1[ ]+a0 > +[ ]+24:[ ]+02a5000b[ ]+dcache.ipa[ ]+a0 > +[ ]+28:[ ]+0225000b[ ]+dcache.isw[ ]+a0 > +[ ]+2c:[ ]+0265000b[ ]+dcache.iva[ ]+a0 > +[ ]+30:[ ]+0020000b[ ]+dcache.iall > +[ ]+34:[ ]+0100000b[ ]+icache.iall > +[ ]+38:[ ]+0110000b[ ]+icache.ialls > +[ ]+3c:[ ]+0385000b[ ]+icache.ipa[ ]+a0 > +[ ]+40:[ ]+0305000b[ ]+icache.iva[ ]+a0 > +[ ]+44:[ ]+0150000b[ ]+l2cache.call > +[ ]+48:[ ]+0170000b[ ]+l2cache.ciall > +[ ]+4c:[ ]+0160000b[ ]+l2cache.iall > +[ ]+50:[ ]+0215000b[ ]+dcache.csw[ ]+a0 > diff --git a/gas/testsuite/gas/riscv/xtheadcache-ext.s b/gas/testsuite/gas/riscv/xtheadcache-ext.s > new file mode 100644 > index 0000000000..7302d0461a > --- /dev/null > +++ b/gas/testsuite/gas/riscv/xtheadcache-ext.s > @@ -0,0 +1,22 @@ > +target: > + dcache.call > + dcache.ciall > + dcache.cipa a0 > + dcache.cisw a0 > + dcache.civa a0 > + dcache.cpa a0 > + dcache.cpal1 a0 > + dcache.cva a0 > + dcache.cval1 a0 > + dcache.ipa a0 > + dcache.isw a0 > + dcache.iva a0 > + dcache.iall > + icache.iall > + icache.ialls > + icache.ipa a0 > + icache.iva a0 > + l2cache.call > + l2cache.ciall > + l2cache.iall > + dcache.csw a0 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 0b8cc6c7dd..255203a3ff 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -2029,6 +2029,49 @@ > #define MASK_HSV_W 0xfe007fff > #define MATCH_HSV_D 0x6e004073 > #define MASK_HSV_D 0xfe007fff > +/* T-Head Cache Instructions. */ > +#define MATCH_DCACHE_CALL 0x0010000B > +#define MASK_DCACHE_CALL 0xffffffff > +#define MATCH_DCACHE_CIALL 0x0030000B > +#define MASK_DCACHE_CIALL 0xffffffff > +#define MATCH_DCACHE_CIPA 0x02b0000b > +#define MASK_DCACHE_CIPA 0xfff07fff > +#define MATCH_DCACHE_CISW 0x0230000b > +#define MASK_DCACHE_CISW 0xfff07fff > +#define MATCH_DCACHE_CIVA 0x0270000b > +#define MASK_DCACHE_CIVA 0xfff07fff > +#define MATCH_DCACHE_CPA 0x0290000b > +#define MASK_DCACHE_CPA 0xfff07fff > +#define MATCH_DCACHE_CPAL1 0x0280000b > +#define MASK_DCACHE_CPAL1 0xfff07fff > +#define MATCH_DCACHE_CVA 0x0250000b > +#define MASK_DCACHE_CVA 0xfff07fff > +#define MATCH_DCACHE_CVAL1 0x0240000b > +#define MASK_DCACHE_CVAL1 0xfff07fff > +#define MATCH_DCACHE_IPA 0x02a0000b > +#define MASK_DCACHE_IPA 0xfff07fff > +#define MATCH_DCACHE_ISW 0x0220000b > +#define MASK_DCACHE_ISW 0xfff07fff > +#define MATCH_DCACHE_IVA 0x0260000b > +#define MASK_DCACHE_IVA 0xfff07fff > +#define MATCH_DCACHE_IALL 0x0020000b > +#define MASK_DCACHE_IALL 0xffffffff > +#define MATCH_ICACHE_IALL 0x0100000b > +#define MASK_ICACHE_IALL 0xffffffff > +#define MATCH_ICACHE_IALLS 0x0110000b > +#define MASK_ICACHE_IALLS 0xffffffff > +#define MATCH_ICACHE_IPA 0x0380000b > +#define MASK_ICACHE_IPA 0xfff07fff > +#define MATCH_ICACHE_IVA 0x0300000b > +#define MASK_ICACHE_IVA 0xfff07fff > +#define MATCH_L2CACHE_CALL 0x0150000b > +#define MASK_L2CACHE_CALL 0xffffffff > +#define MATCH_L2CACHE_CIALL 0x0170000b > +#define MASK_L2CACHE_CIALL 0xffffffff > +#define MATCH_L2CACHE_IALL 0x0160000b > +#define MASK_L2CACHE_IALL 0xffffffff > +#define MATCH_DCACHE_CSW 0x0210000b > +#define MASK_DCACHE_CSW 0xfff07fff > /* Privileged CSR addresses. */ > #define CSR_USTATUS 0x0 > #define CSR_UIE 0x4 > @@ -2628,6 +2671,27 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) > DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) > DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) > DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) > +DECLARE_INSN(dcache_call, MATCH_DCACHE_CALL, MASK_DCACHE_CALL) > +DECLARE_INSN(dcache_ciall, MATCH_DCACHE_CIALL, MASK_DCACHE_CIALL) > +DECLARE_INSN(dcache_cipa, MATCH_DCACHE_CIPA, MASK_DCACHE_CIPA) > +DECLARE_INSN(dcache_cisw, MATCH_DCACHE_CISW, MASK_DCACHE_CISW) > +DECLARE_INSN(dcache_civa, MATCH_DCACHE_CIVA, MASK_DCACHE_CIVA) > +DECLARE_INSN(dcache_cpa, MATCH_DCACHE_CPA, MASK_DCACHE_CPA) > +DECLARE_INSN(dcache_cpal1, MATCH_DCACHE_CPAL1, MASK_DCACHE_CPAL1) > +DECLARE_INSN(dcache_cva, MATCH_DCACHE_CVA, MASK_DCACHE_CVA) > +DECLARE_INSN(dcache_cval1, MATCH_DCACHE_CVAL1, MASK_DCACHE_CVAL1) > +DECLARE_INSN(dcache_ipa, MATCH_DCACHE_IPA, MASK_DCACHE_IPA) > +DECLARE_INSN(dcache_isw, MATCH_DCACHE_ISW, MASK_DCACHE_ISW) > +DECLARE_INSN(dcache_iva, MATCH_DCACHE_IVA, MASK_DCACHE_IVA) > +DECLARE_INSN(dcache_iall, MATCH_DCACHE_IALL, MASK_DCACHE_IALL) > +DECLARE_INSN(icache_iall, MATCH_ICACHE_IALL, MASK_ICACHE_IALL) > +DECLARE_INSN(icache_ialls, MATCH_ICACHE_IALLS, MASK_ICACHE_IALLS) > +DECLARE_INSN(icache_ipa, MATCH_ICACHE_IPA, MASK_ICACHE_IPA) > +DECLARE_INSN(icache_iva, MATCH_ICACHE_IVA, MASK_ICACHE_IVA) > +DECLARE_INSN(l2cache_call, MATCH_L2CACHE_CALL, MATCH_L2CACHE_CALL) > +DECLARE_INSN(l2cache_ciall, MATCH_L2CACHE_CIALL, MATCH_L2CACHE_CIALL) > +DECLARE_INSN(l2cache_iall, MATCH_L2CACHE_IALL, MATCH_L2CACHE_IALL) > +DECLARE_INSN(dcache_csw, MATCH_DCACHE_CSW, MATCH_DCACHE_CSW) > #endif /* DECLARE_INSN */ > #ifdef DECLARE_CSR > /* Privileged CSRs. */ > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index 048ab0a5d6..e150919633 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -388,6 +388,7 @@ enum riscv_insn_class > INSN_CLASS_V, > INSN_CLASS_ZVEF, > INSN_CLASS_SVINVAL, > + INSN_CLASS_XTHEADCACHE, > }; > > /* This structure holds information for a particular instruction. */ > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index 2da0f7cf0a..b6c1c89f42 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -1753,6 +1753,29 @@ const struct riscv_opcode riscv_opcodes[] = > {"hsv.w", 0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE }, > {"hsv.d", 64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE }, > > +/* T-Head cache instructions */ > +{"dcache.call", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_DCACHE_CALL, MASK_DCACHE_CALL, match_opcode, 0 }, > +{"dcache.ciall", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_DCACHE_CIALL, MASK_DCACHE_CIALL, match_opcode, 0 }, > +{"dcache.cipa", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CIPA, MASK_DCACHE_CIPA, match_opcode, 0 }, > +{"dcache.cisw", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CISW, MASK_DCACHE_CISW, match_opcode, 0 }, > +{"dcache.civa", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CIVA, MASK_DCACHE_CIVA, match_opcode, 0 }, > +{"dcache.cpa", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CPA, MASK_DCACHE_CPA, match_opcode, 0 }, > +{"dcache.cpal1", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CPAL1, MASK_DCACHE_CPAL1, match_opcode, 0 }, > +{"dcache.cva", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CVA, MASK_DCACHE_CVA, match_opcode, 0 }, > +{"dcache.cval1", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CVAL1, MASK_DCACHE_CVAL1, match_opcode, 0 }, > +{"dcache.ipa", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_IPA, MASK_DCACHE_IPA, match_opcode, 0 }, > +{"dcache.isw", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_ISW, MASK_DCACHE_ISW, match_opcode, 0 }, > +{"dcache.iva", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_IVA, MASK_DCACHE_IVA, match_opcode, 0 }, > +{"dcache.iall", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_DCACHE_IALL, MASK_DCACHE_IALL, match_opcode, 0 }, > +{"icache.iall", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_ICACHE_IALL, MASK_ICACHE_IALL, match_opcode, 0 }, > +{"icache.ialls", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_ICACHE_IALLS, MASK_ICACHE_IALLS, match_opcode, 0 }, > +{"icache.ipa", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_ICACHE_IPA, MASK_ICACHE_IPA, match_opcode, 0 }, > +{"icache.iva", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_ICACHE_IVA, MASK_ICACHE_IVA, match_opcode, 0 }, > +{"l2cache.call", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_L2CACHE_CALL, MASK_L2CACHE_CALL, match_opcode, 0 }, > +{"l2cache.ciall", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_L2CACHE_CIALL, MASK_L2CACHE_CIALL, match_opcode, 0 }, > +{"l2cache.iall", 0, INSN_CLASS_XTHEADCACHE, "", MATCH_L2CACHE_IALL, MASK_L2CACHE_IALL, match_opcode, 0 }, > +{"dcache.csw", 0, INSN_CLASS_XTHEADCACHE, "s", MATCH_DCACHE_CSW, MASK_DCACHE_CSW, match_opcode, 0 }, > + > /* Terminate the list. */ > {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} > }; > -- > 2.25.1 >