From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-vs1-xe2e.google.com (mail-vs1-xe2e.google.com [IPv6:2607:f8b0:4864:20::e2e]) by sourceware.org (Postfix) with ESMTPS id 3E52A385840A for ; Fri, 29 Jul 2022 01:52:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3E52A385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-vs1-xe2e.google.com with SMTP id o4so3224700vsc.12 for ; Thu, 28 Jul 2022 18:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7bQpapbUAKxtuWEdTMw77u25BLp3Q64WOBRILLtGqMU=; b=TxLZX2XRSPU1h9cCMFJG0iy/viwYk/0HhhggrOPzkV1aG5Snb34D5O4uN/9yJ5C9+p Tfayd4ymJmPyTAdQVqxkuiwelLUW0h+iR/GgpF1oG/jqwLa9pHcdkdRAtAl7/v64dRKX a0TvrbmTFvO1TSr44afZ18m6r3duibjjrURM0E32XA9F1f8St1UNltK7ckQmlc57cBUI 3+nUMirJJMbHImRapYigPJ9YeyQCqHR+itfFNej0hsLlsuqxPQMx/eWKkGVde51J0VgQ OFjsFGzcSPvr4lFV4SnnuXPHfo461MK2wst7QUWDpwqDnmDmIgEFtSE0RXv8ffh4f0OI p5fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7bQpapbUAKxtuWEdTMw77u25BLp3Q64WOBRILLtGqMU=; b=sXong5g3tnoaqu210cX+Tqlp28L5oqaZHz0mPmlwgAxrDZ5YbaHW8TIREx+fpi22Px arm5/DlU+B9O5K3h10/X0qNupJTzx3GIV5QSks9nBHNgZo/bSTzkwnuce2JBcIWs6ET7 8EgTpF/Phc1EWPLPzguMwWNGgfDt+1+nnKz7BkuMWqc4p+P8kLdx4HsYnURX813HZomY U38esrOTA6tG4o7KpN6wWsAOVkJ2j/kL0k76cXOmuhZn2bB99SZIngcLO9ZT+rTyMmeH jLrWo7+tTOrcFGdkPbGUJ5UGUM7UuTsKwzGw4h7OTV6JfYHtOsRYTYydCIVM5SmsKghh O3UA== X-Gm-Message-State: AJIora9nQGG/wxykVXXIK63VCR7/f/lKAnkQoNitW6IGV4VTXQ6pZuGm b3ng1dwZBWzIAbVO/aVSL6+ufX3ovt964uvuEz7F9Q== X-Google-Smtp-Source: AGRyM1tRkzTNLPCG0j06jG/pS7IDAs/UsxlKh0Z7ZHR4xCTdVCHB9EobevQ/w98Eb4O4f+d4qjCoYQ/0VnUFAev0lks= X-Received: by 2002:a67:d91c:0:b0:358:432b:135b with SMTP id t28-20020a67d91c000000b00358432b135bmr490645vsj.31.1659059526405; Thu, 28 Jul 2022 18:52:06 -0700 (PDT) MIME-Version: 1.0 References: <60b65d0e0a3cde2edb6c3276a5d31b29d628c60e.1659013304.git.research_trasio@irq.a4lg.com> In-Reply-To: From: Nelson Chu Date: Fri, 29 Jul 2022 09:51:57 +0800 Message-ID: Subject: Re: [PATCH v2 1/1] RISC-V: Add `OP_V' to .insn named opcodes To: Kito Cheng Cc: Tsukasa OI , Kito Cheng , Palmer Dabbelt , Binutils Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jul 2022 01:52:09 -0000 On Thu, Jul 28, 2022 at 9:29 PM Kito Cheng wrote: > > LGTM Thanks for helping reviewing. > On Thu, Jul 28, 2022 at 9:03 PM Tsukasa OI via Binutils > wrote: > > > > This commit adds `OP_V' (OP-V: vector instruction opcode for now > > ratified `V' extension) to .insn opcode name list. Although vector > > instruction encoding is not implemented in `.insn' directive, it will > > help future implementation of custom vector `.insn'. Yes, the original discussion was raised by Jim, and here is the link, https://github.com/riscv/riscv-v-spec/issues/93 As mentioned in the link, we also have similar supports in the riscv github, https://github.com/riscv-collab/riscv-binutils-gdb/pull/184/files Using r type here makes sense, since we don't have any instruction format names for rvv. However, maybe it is worth adding Vd/Vs/Vt registers for r type when v is enabled, just like what we did for fpr registers. But I think it is minor, and we can add it in the future if needed, so this patch is committed by passing the regressions. Thanks Nelson > > gas/ChangeLog: > > > > * config/tc-riscv.c (opcode_name_list): Add `OP_V'. > > * testsuite/gas/riscv/insn.s: Add testcase. > > * testsuite/gas/riscv/insn.d: Likewise. > > * testsuite/gas/riscv/insn-dwarf.d: Reflect insn.s update. > > --- > > gas/config/tc-riscv.c | 2 +- > > gas/testsuite/gas/riscv/insn-dwarf.d | 17 +++++++++-------- > > gas/testsuite/gas/riscv/insn.d | 3 ++- > > gas/testsuite/gas/riscv/insn.s | 2 ++ > > 4 files changed, 14 insertions(+), 10 deletions(-) > > > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > > index 291d07f6d8f..ecdffbef589 100644 > > --- a/gas/config/tc-riscv.c > > +++ b/gas/config/tc-riscv.c > > @@ -749,7 +749,7 @@ static const struct opcode_name_t opcode_name_list[] = > > {"NMADD", 0x4f}, > > {"NMSUB", 0x4b}, > > {"OP_FP", 0x53}, > > - /*reserved 0x57. */ > > + {"OP_V", 0x57}, > > {"CUSTOM_2", 0x5b}, > > /* 48b 0x5f. */ > > > > diff --git a/gas/testsuite/gas/riscv/insn-dwarf.d b/gas/testsuite/gas/riscv/insn-dwarf.d > > index 72d54d47acf..a975b1464c0 100644 > > --- a/gas/testsuite/gas/riscv/insn-dwarf.d > > +++ b/gas/testsuite/gas/riscv/insn-dwarf.d > > @@ -60,12 +60,13 @@ insn.s +53 +0x9a.* > > insn.s +54 +0x9e.* > > insn.s +55 +0xa2.* > > insn.s +57 +0xa6.* > > -insn.s +58 +0xa8.* > > -insn.s +59 +0xac.* > > -insn.s +60 +0xb2.* > > -insn.s +61 +0xba.* > > -insn.s +62 +0xbc.* > > -insn.s +63 +0xc0.* > > -insn.s +64 +0xc6.* > > -insn.s +- +0xce > > +insn.s +59 +0xaa.* > > +insn.s +60 +0xac.* > > +insn.s +61 +0xb0.* > > +insn.s +62 +0xb6.* > > +insn.s +63 +0xbe.* > > +insn.s +64 +0xc0.* > > +insn.s +65 +0xc4.* > > +insn.s +66 +0xca.* > > +insn.s +- +0xd2 > > #pass > > diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d > > index b5780f42861..d177f313d23 100644 > > --- a/gas/testsuite/gas/riscv/insn.d > > +++ b/gas/testsuite/gas/riscv/insn.d > > @@ -1,4 +1,4 @@ > > -#as: -march=rv32ifc > > +#as: -march=rv32ifdcv Just a minor thing that we don't need to add d-ext here. > > #objdump: -dr > > > > .*:[ ]+file format .* > > @@ -69,6 +69,7 @@ Disassembly of section .text: > > [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 > > [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 > > [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 > > +[^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3 > > [^:]+:[ ]+0001[ ]+nop > > [^:]+:[ ]+00000013[ ]+nop > > [^:]+:[ ]+001f 0000 0000[ ].* > > diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s > > index ec41acb30bd..993615eb747 100644 > > --- a/gas/testsuite/gas/riscv/insn.s > > +++ b/gas/testsuite/gas/riscv/insn.s > > @@ -54,6 +54,8 @@ target: > > .insn r 0x33, 0, 0, a0, fa1, fa2 > > .insn r 0x33, 0, 0, fa0, fa1, fa2 > > > > + .insn r OP_V, 0, 1, x1, x3, x2 > > + > > .insn 0x0001 > > .insn 0x00000013 > > .insn 0x0000001f > > -- > > 2.34.1 > >