From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io1-xd2d.google.com (mail-io1-xd2d.google.com [IPv6:2607:f8b0:4864:20::d2d]) by sourceware.org (Postfix) with ESMTPS id 5A0F4385843E for ; Thu, 7 Oct 2021 04:02:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5A0F4385843E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-io1-xd2d.google.com with SMTP id h189so2379401iof.1 for ; Wed, 06 Oct 2021 21:02:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=F1B7lV1GWTFle6lvnsW2gxr1VPTRCsbh3kix+Lk7z8Y=; b=f/lVYTWxudEE5sGTQRjBzj/IzttMFdwqrDB4t8NAHZEgMt0Db9L/2m6/X1dxNGnUnv do9p28AVKGBmbwWcUQC/HVVlbKYvqQjWqq2cqa+Sc8W3/KRCy/pTlg4snsc3UIbhzNUs jfdGzRfUMlQn2f24OM/RhSU5lFnVLNleahRy+IJ0QbRbUSsRBPIa+YG+pIjymh/gHEb4 2cgFVaGYTjwbKucgwwgbDBolwkqgNgwVznOtJBrKjmVHv7gm8Y1GRs7CdmODFz6DRrCz +gxKqzgLDN+Vsfab9hzw3y3Ajl25xVA/6inULhyCn0cBZv5NnUXP01Sqsz2++V9D7Avg Ub4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=F1B7lV1GWTFle6lvnsW2gxr1VPTRCsbh3kix+Lk7z8Y=; b=AnFv0M11gKUqrrwdY2HPAq3KUV/aUZKKo/gHhOoHxRK6lY0m/rm1Q1Bj8J+FHZ3y5N C4CcFxOIwzsFm9QQj9R1W6k6ZKy6RQYOudkZ3oUdM+gIYWVMI1U/REkQ0YLdQZZIpkIy uKAIkElrFc9B00HY5+/9qtigmSzw3P/8Gu2TTZbREFAEfNPd4tY0tGyDaMMU3lQp4vUq ZVZehd8BaddTuCfKEb8rQQSXmULufkniSVeyhwooDZHa5t4HNQiR707aA8844GQYkvOb LCuPgyBz37eGQ/VPJB+8QG/ivK3iLWsdlC2lXFXeArkzZy9eMWDEWMEUwGTPjV8sIcym LfsQ== X-Gm-Message-State: AOAM533h1zm+5V3sDfVEtN0duhuFRD3uKGvHN5a5ymPwYdmWYMCdME1V vUwCR59sd9rpsmdwmiPbEY4gw6tT3C0pFvuVvfq9DwLzXpeVkQ== X-Google-Smtp-Source: ABdhPJzBR2R240qEiaVAiSa8eJgcO0zN6OdpDPP7ILl3erGCFNGmINVjdjIkLWRpt0WgzetVGeTx4JEUyoAhTO6cpls= X-Received: by 2002:a05:6638:1b2:: with SMTP id b18mr1187402jaq.95.1633579343790; Wed, 06 Oct 2021 21:02:23 -0700 (PDT) MIME-Version: 1.0 References: <20211006202647.328777-1-philipp.tomsich@vrull.eu> <20211006202647.328777-3-philipp.tomsich@vrull.eu> In-Reply-To: <20211006202647.328777-3-philipp.tomsich@vrull.eu> From: Nelson Chu Date: Thu, 7 Oct 2021 12:02:13 +0800 Message-ID: Subject: Re: [PATCH v3 3/4] RISC-V: Add support for Zbs instructions To: Philipp Tomsich Cc: Binutils , Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 04:02:26 -0000 LGTM, thanks. Nelson On Thu, Oct 7, 2021 at 4:28 AM Philipp Tomsich wrote: > > This change adds the Zbs instructions from the Zbs 1.0.0 specification. > See > https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0 > for the frozen specification. > > 2021-01-09 Philipp Tomsich > > bfd/ > * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs. > gas/ > * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS. > * testsuite/gas/riscv/b-ext.d: Test Zbs instructions. > * testsuite/gas/riscv/b-ext.s: Likewise. > * testsuite/gas/riscv/b-ext-64.d: Likewise. > * testsuite/gas/riscv/b-ext-64.s: Likewise. > include/ > * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs. > * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS. > opcodes/ > * riscv-opc.c (riscv_supported_std_z_ext): Add zbs. > > Signed-off-by: Philipp Tomsich > > --- > > Changes in v3: > - Updated to 1.0.0 specification and rebased to master > > bfd/elfxx-riscv.c | 1 + > gas/config/tc-riscv.c | 3 +++ > gas/testsuite/gas/riscv/b-ext-64.d | 18 +++++++++++++++++- > gas/testsuite/gas/riscv/b-ext-64.s | 16 ++++++++++++++++ > gas/testsuite/gas/riscv/b-ext.d | 14 +++++++++++++- > gas/testsuite/gas/riscv/b-ext.s | 12 ++++++++++++ > include/opcode/riscv-opc.h | 24 ++++++++++++++++++++++++ > include/opcode/riscv.h | 1 + > opcodes/riscv-opc.c | 9 +++++++++ > 9 files changed, 96 insertions(+), 2 deletions(-) > > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c > index 39a7d693469..cdb4fa0996a 100644 > --- a/bfd/elfxx-riscv.c > +++ b/bfd/elfxx-riscv.c > @@ -1145,6 +1145,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = > {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > + {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, > {NULL, 0, 0, 0, 0} > }; > > diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c > index e7b733a4e6d..f7e0c929aa0 100644 > --- a/gas/config/tc-riscv.c > +++ b/gas/config/tc-riscv.c > @@ -283,6 +283,9 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class) > case INSN_CLASS_ZBC: > return riscv_subset_supports ("zbc"); > > + case INSN_CLASS_ZBS: > + return riscv_subset_supports ("zbs"); > + > default: > as_fatal ("internal: unreachable"); > return false; > diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d > index f4a7abf02d7..339fa20a367 100644 > --- a/gas/testsuite/gas/riscv/b-ext-64.d > +++ b/gas/testsuite/gas/riscv/b-ext-64.d > @@ -1,4 +1,4 @@ > -#as: -march=rv64i_zba_zbb_zbc > +#as: -march=rv64i_zba_zbb_zbc_zbs > #source: b-ext-64.s > #objdump: -d > > @@ -46,3 +46,19 @@ Disassembly of section .text: > [ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2 > [ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1 > [ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2 > +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+4bf59513[ ]+bclri[ ]+a0,a1,0x3f > +[ ]+[0-9a-f]+:[ ]+2bf59513[ ]+bseti[ ]+a0,a1,0x3f > +[ ]+[0-9a-f]+:[ ]+6bf59513[ ]+binvi[ ]+a0,a1,0x3f > +[ ]+[0-9a-f]+:[ ]+4bf5d513[ ]+bexti[ ]+a0,a1,0x3f > +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2 > diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s > index c3ac377f4bd..8ceb2b4fd1c 100644 > --- a/gas/testsuite/gas/riscv/b-ext-64.s > +++ b/gas/testsuite/gas/riscv/b-ext-64.s > @@ -37,3 +37,19 @@ target: > add.uw a0, a1, a2 > zext.w a0, a1 > slli.uw a0, a1, 2 > + bclri a0, a1, 0 > + bclri a0, a1, 31 > + bseti a0, a1, 0 > + bseti a0, a1, 31 > + binvi a0, a1, 0 > + binvi a0, a1, 31 > + bexti a0, a1, 0 > + bexti a0, a1, 31 > + bclri a0, a1, 63 > + bseti a0, a1, 63 > + binvi a0, a1, 63 > + bexti a0, a1, 63 > + bclr a0, a1, a2 > + bset a0, a1, a2 > + binv a0, a1, a2 > + bext a0, a1, a2 > diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d > index 7410796a3b7..748c218fdd0 100644 > --- a/gas/testsuite/gas/riscv/b-ext.d > +++ b/gas/testsuite/gas/riscv/b-ext.d > @@ -1,4 +1,4 @@ > -#as: -march=rv32i_zba_zbb_zbc > +#as: -march=rv32i_zba_zbb_zbc_zbs > #source: b-ext.s > #objdump: -d > > @@ -33,3 +33,15 @@ Disassembly of section .text: > [ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2 > [ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2 > [ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+48059513[ ]+bclri[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+49f59513[ ]+bclri[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+28059513[ ]+bseti[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+29f59513[ ]+bseti[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+68059513[ ]+binvi[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+69f59513[ ]+binvi[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+4805d513[ ]+bexti[ ]+a0,a1,0x0 > +[ ]+[0-9a-f]+:[ ]+49f5d513[ ]+bexti[ ]+a0,a1,0x1f > +[ ]+[0-9a-f]+:[ ]+48c59533[ ]+bclr[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+28c59533[ ]+bset[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+68c59533[ ]+binv[ ]+a0,a1,a2 > +[ ]+[0-9a-f]+:[ ]+48c5d533[ ]+bext[ ]+a0,a1,a2 > diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s > index 051dafd1719..a13a797f0dc 100644 > --- a/gas/testsuite/gas/riscv/b-ext.s > +++ b/gas/testsuite/gas/riscv/b-ext.s > @@ -24,3 +24,15 @@ target: > clmul a0, a1, a2 > clmulh a0, a1, a2 > clmulr a0, a1, a2 > + bclri a0, a1, 0 > + bclri a0, a1, 31 > + bseti a0, a1, 0 > + bseti a0, a1, 31 > + binvi a0, a1, 0 > + binvi a0, a1, 31 > + bexti a0, a1, 0 > + bexti a0, a1, 31 > + bclr a0, a1, a2 > + bset a0, a1, a2 > + binv a0, a1, a2 > + bext a0, a1, a2 > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h > index 9999da6241a..45a207da0cd 100644 > --- a/include/opcode/riscv-opc.h > +++ b/include/opcode/riscv-opc.h > @@ -495,6 +495,22 @@ > #define MASK_CLMULH 0xfe00707f > #define MATCH_CLMULR 0xa002033 > #define MASK_CLMULR 0xfe00707f > +#define MATCH_BCLRI 0x48001013 > +#define MASK_BCLRI 0xfc00707f > +#define MATCH_BSETI 0x28001013 > +#define MASK_BSETI 0xfc00707f > +#define MATCH_BINVI 0x68001013 > +#define MASK_BINVI 0xfc00707f > +#define MATCH_BEXTI 0x48005013 > +#define MASK_BEXTI 0xfc00707f > +#define MATCH_BCLR 0x48001033 > +#define MASK_BCLR 0xfe00707f > +#define MATCH_BSET 0x28001033 > +#define MASK_BSET 0xfe00707f > +#define MATCH_BINV 0x68001033 > +#define MASK_BINV 0xfe00707f > +#define MATCH_BEXT 0x48005033 > +#define MASK_BEXT 0xfe00707f > #define MATCH_FLW 0x2007 > #define MASK_FLW 0x707f > #define MATCH_FLD 0x3007 > @@ -1102,6 +1118,14 @@ DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) > DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) > DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) > DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) > +DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) > +DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) > +DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) > +DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) > +DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) > +DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) > +DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) > +DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) > DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) > DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) > DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) > diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h > index a8f47419f75..afcd41ff1dd 100644 > --- a/include/opcode/riscv.h > +++ b/include/opcode/riscv.h > @@ -319,6 +319,7 @@ enum riscv_insn_class > INSN_CLASS_ZBA, > INSN_CLASS_ZBB, > INSN_CLASS_ZBC, > + INSN_CLASS_ZBS, > }; > > /* This structure holds information for a particular instruction. */ > diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c > index e0621503b79..1a4c9f0e4fe 100644 > --- a/opcodes/riscv-opc.c > +++ b/opcodes/riscv-opc.c > @@ -833,6 +833,15 @@ const struct riscv_opcode riscv_opcodes[] = > {"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 }, > {"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 }, > > +/* Zbs instructions */ > +{"bclri", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BCLRI, MASK_BCLRI, match_opcode, 0 }, > +{"bseti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BSETI, MASK_BSETI, match_opcode, 0 }, > +{"binvi", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BINVI, MASK_BINVI, match_opcode, 0 }, > +{"bexti", 0, INSN_CLASS_ZBS, "d,s,>", MATCH_BEXTI, MASK_BEXTI, match_opcode, 0 }, > +{"bclr", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BCLR, MASK_BCLR, match_opcode, 0 }, > +{"bset", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BSET, MASK_BSET, match_opcode, 0 }, > +{"binv", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BINV, MASK_BINV, match_opcode, 0 }, > +{"bext", 0, INSN_CLASS_ZBS, "d,s,t", MATCH_BEXT, MASK_BEXT, match_opcode, 0 }, > > /* Terminate the list. */ > {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0} > -- > 2.25.1 >