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From: Nelson Chu <nelson.chu@sifive.com>
To: Jim Wilson <jimw@sifive.com>
Cc: Binutils <binutils@sourceware.org>, Alan Modra <amodra@gmail.com>,
	 Nick Clifton <nickc@redhat.com>,
	Kito Cheng <kito.cheng@sifive.com>,
	 Andrew Waterman <andrew@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Simon Cook <simon.cook@embecosm.com>,
	Jeremy Bennett <jeremy.bennett@embecosm.com>
Subject: Re: [Integration 0/6] RISC-V: The prototype of the integration and working branches for binutils.
Date: Fri, 16 Apr 2021 10:32:48 +0800	[thread overview]
Message-ID: <CAJYME4Hnnpt6qp80RGiNwMn38H=k4Oq6AU-YV=OiQy+0uVVsVQ@mail.gmail.com> (raw)
In-Reply-To: <CAFyWVaaAx+c4BV4xX3ZL4_d9up0uGe9mjDNEQ4NKFHc2Udnx+w@mail.gmail.com>

On Wed, Mar 31, 2021 at 7:16 AM Jim Wilson <jimw@sifive.com> wrote:
>
> On Tue, Mar 30, 2021 at 2:37 AM Nelson Chu <nelson.chu@sifive.com> wrote:
>>
>> RISC-V GNU binutils will have another two FSF develop branches to let
>> developers can contribute their works, but these works are not ratified
>> yet, so they aren't allowed to merge into mainline.  The two branches are
>> integration branch and working branch.  The series of patches are the
>> prototypes for these two develop branches, and they won't be applied to
>> the mainline.  Please see the details in the comments of the patches,
>> and feels free to share any thought and suggestion, if you are interested.
>
>
> The series looks OK to me.  I made some minor comments, other than the Zfh fcvt.q.h and fcvt.h.q which I think are broken and need to be fixed.

Oh forgot to mention that I have fixed the following issues, and then
sent the v2 series of the patches yesterday.

* Removed the vendor stuff since it is still discussing, so only keep
the draft v and zfh at this stage.
* Fixed the header issue (data and author) for the new added headers.
* Fixed the wrong encoding of fcvt.q.h and fcvt.h.q.
* Added f as the implicit extension of zfh, and changed
INSN_CLASS_F_AND_ZFH to INSN_CLASS_ZFH.

I see that ARM had created their branches in the user folders,
remotes/upstream/users/ARM/embedded-binutils-2_26-branch
remotes/upstream/users/ARM/embedded-gdb-7.10-branch
remotes/upstream/users/ARM/morello-binutils-gdb-master
remotes/upstream/users/ARM/sve

so RISC-V probably can create our integration and working branch to
/users/RISCV/riscv-binutils-integration-branch
/users/RISCV/riscv-binutils-working-branch

These branches are based on the mainline, and will merge the features
from mainline regularity.  I cannot find any spec or discussion that
mention the branch names, so the above names can be changed before we
created them.

However, I don't know if we need to have the stable released branch
with specific versions of the draft/vendor features.  For example, we
are working on the riscv-binutils-integration-branch which is based on
the manline.  Once the new stable released branch is created, like
2.37, then we should create the
riscv-binutils-integration-2.37-branch, and port the features from
riscv-binutils-integration-branch to there.  Therefore, we may have
the following branches in the future,
/users/RISCV/riscv-binutils-integration-branch, with newest zext v0.9
/users/RISCV/riscv-binutils-integration-2.38-branch, with zext v0.8
/users/RISCV/riscv-binutils-integration-2.37-branch, with zext v0.5
...
Or we don't need to do this, just keep the
riscv-binutils-integration-branch with the newest versions of drafts,
and based on the mainline.  This is not very urgent, so we still have
time to discuss it.  Anyway, if the name of the branch is fine to you,
I will create the /users/RISCV/riscv-binutils-integration-branch first
recently.  Please feel free to share your thoughts and suggestions.
It would be great if you can send the mail to me or reply to this mail
directly.

Thanks
Nelson

  reply	other threads:[~2021-04-16  2:33 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-30  9:36 Nelson Chu
2021-03-30  9:36 ` [Integration 1/6] RISC-V/extended: Add extended extension hooks when parsing architecture string Nelson Chu
2021-03-30 22:46   ` Jim Wilson
2021-03-30  9:36 ` [Integration 2/6] RISC-V/extended: Add assembler and dis-assembler hooks for extended extensions Nelson Chu
2021-03-30 22:53   ` Jim Wilson
2021-03-30  9:36 ` [Integration 3/6] RISC-V/sifive: Add sifive cache control instructions Nelson Chu
2021-03-30 22:56   ` Jim Wilson
2021-03-30  9:36 ` [Integration 4/6] RISC-V/rvv: Add rvv v0.10 instructions Nelson Chu
2021-03-30  9:36 ` [Integration 5/6] RISC-V/zfh: Add half-precision floating-point v0.1 instructions Nelson Chu
2021-03-30 23:09   ` Jim Wilson
2021-04-06  2:01     ` Nelson Chu
2021-03-30  9:36 ` [Integration 6/6] RISC-V/zfh: Support .float16 directive for assembler Nelson Chu
2021-03-30 23:14   ` Jim Wilson
2021-03-30 23:16 ` [Integration 0/6] RISC-V: The prototype of the integration and working branches for binutils Jim Wilson
2021-04-16  2:32   ` Nelson Chu [this message]
2021-04-20 19:10     ` Jim Wilson
2021-04-20 21:07       ` Mike Frysinger
2021-04-22  1:39         ` Nelson Chu
2021-04-22  1:27       ` Nelson Chu

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