From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-f44.google.com (mail-pj1-f44.google.com [209.85.216.44]) by sourceware.org (Postfix) with ESMTPS id EDED73858D1E for ; Sun, 5 Mar 2023 13:38:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EDED73858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=debian.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-f44.google.com with SMTP id m8-20020a17090a4d8800b002377bced051so10667848pjh.0 for ; Sun, 05 Mar 2023 05:38:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678023520; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vq+qbLD3h7oVh5y1892bi2GSGl7XzoSHQXa2vZyNmGU=; b=uCyWoXnue/3t4Xlzz1smaFgtYmEVgTIKG1jd8RptC99Fk0r2L0bRvUwqQIvLJFqJnA IlqN6ZN0sAuJVm+Un6uYpMiW2KJpgGJ+j1i+vmkkZtExfJJFnmdTKfKZsaj2nZVSRzck G2lrWayKzNrzZxnTZTNoctTgG4EQYjO7xq5q5ZcexPsSGZKGi906vfVbIXgbVzoOj6H4 XKe2y33YjDWeVBfGvaqOo3XkoGiOZqVVsVXi/JhLu0raLJsLGlrldes52NzYWf6Lik/P 5AWSv9urNlWUwls/NFx0IM8fEgYG5O1Tl17EWu8LDDuaD079z+QyQcyNyoxVIN6hP3al /1EQ== X-Gm-Message-State: AO0yUKWeDnTnvynnAXueKR58fyvLsG25zCdZKucO1UcTherlMl20gsTL PREDPx1t0qw4bCVF1v1RFTM+InrbWFwT8IS/PkN4jZR5 X-Google-Smtp-Source: AK7set9hqRNXyy2xoM9GwvrfbO31ba6pCSuUqHqpiYY0nhIMjt8AK7cLVxRTYBvEfTVDpwsJ2WwcWwfkK5d2WbOT+bw= X-Received: by 2002:a17:903:328e:b0:19a:f3f8:c31a with SMTP id jh14-20020a170903328e00b0019af3f8c31amr2993688plb.10.1678023519913; Sun, 05 Mar 2023 05:38:39 -0800 (PST) MIME-Version: 1.0 References: <20230221040650.2337395-1-yunqiang.su@cipunited.com> <20230302015222.291088-1-yunqiang.su@cipunited.com> In-Reply-To: <20230302015222.291088-1-yunqiang.su@cipunited.com> From: YunQiang Su Date: Sun, 5 Mar 2023 21:38:28 +0800 Message-ID: Subject: Re: [PATCH v2] MIPS: make mipsisa32 and mipsisa64 link more systematic To: YunQiang Su Cc: binutils@sourceware.org, macro@orcam.me.uk, xry111@xry111.site, richard.sandiford@arm.com, jiaxun.yang@flygoat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00,BODY_8BITS,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,GIT_PATCH_0,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: @Rickard can you help to submit this patch to git? I have no permission to do so. YunQiang Su =E4=BA=8E2023=E5=B9=B43=E6=9C=882= =E6=97=A5=E5=91=A8=E5=9B=9B 09:52=E5=86=99=E9=81=93=EF=BC=9A > > Introduce `static const struct mips_mach_extension mips_mach_32_64[]` > and `mips_mach_extends_32_64 (unsigned long base, unsigned long extension= )`, > to make mipsisa32 and mipsisa64 interlink more systemtic. > > Normally, the ISA mipsisa64rN has two subset: mipsisa64r(N-1) and > mipsisa32rN. `mips_mach_extensions` can hold only mipsisa64r(N-1), > so we need to introduce a new instruction `mips_mach_32_64`, which holds = the pair 32vs64. > > Note: R6 is not compatible with pre-R6. > > bfd/ChangeLog: > > * elfxx-mips.c (mips_mach_extends_p): make mipsisa32 and > mipsisa64 interlink more systematic. > (mips_mach_32_64): new struct added. > (mips_mach_extends_32_64): new function added. > --- > bfd/elfxx-mips.c | 40 +++++++++++++++++++++++++++++----------- > 1 file changed, 29 insertions(+), 11 deletions(-) > > diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c > index 35bbd86044b..21e6396609b 100644 > --- a/bfd/elfxx-mips.c > +++ b/bfd/elfxx-mips.c > @@ -14524,6 +14524,16 @@ struct mips_mach_extension > unsigned long extension, base; > }; > > +/* An array that maps 64-bit architectures to the corresponding 32-bit > + architectures. */ > +static const struct mips_mach_extension mips_mach_32_64[] =3D > +{ > + { bfd_mach_mipsisa64r6, bfd_mach_mipsisa32r6 }, > + { bfd_mach_mipsisa64r5, bfd_mach_mipsisa32r5 }, > + { bfd_mach_mipsisa64r3, bfd_mach_mipsisa32r3 }, > + { bfd_mach_mipsisa64r2, bfd_mach_mipsisa32r2 }, > + { bfd_mach_mipsisa64, bfd_mach_mipsisa32 } > +}; > > /* An array describing how BFD machines relate to one another. The entr= ies > are ordered topologically with MIPS I extensions listed last. */ > @@ -14601,29 +14611,37 @@ static const struct mips_mach_extension mips_ma= ch_extensions[] =3D > { bfd_mach_mips3900, bfd_mach_mips3000 } > }; > > -/* Return true if bfd machine EXTENSION is an extension of machine BASE.= */ > +/* Return true if bfd machine EXTENSION is the same as BASE, or if > + EXTENSION is the 64-bit equivalent of a 32-bit BASE. */ > + > +static bool > +mips_mach_extends_32_64 (unsigned long base, unsigned long extension) > +{ > + size_t i; > + > + if (extension =3D=3D base) > + return true; > + > + for (i =3D 0; i < ARRAY_SIZE (mips_mach_64_32); i++) > + if (extension =3D=3D mips_mach_32_64[i].extension) > + return base =3D=3D mips_mach_32_64[i].base; > + > + return false; > +} > > static bool > mips_mach_extends_p (unsigned long base, unsigned long extension) > { > size_t i; > > - if (extension =3D=3D base) > - return true; > - > - if (base =3D=3D bfd_mach_mipsisa32 > - && mips_mach_extends_p (bfd_mach_mipsisa64, extension)) > - return true; > - > - if (base =3D=3D bfd_mach_mipsisa32r2 > - && mips_mach_extends_p (bfd_mach_mipsisa64r2, extension)) > + if (mips_mach_extends_32_64 (base, extension)) > return true; > > for (i =3D 0; i < ARRAY_SIZE (mips_mach_extensions); i++) > if (extension =3D=3D mips_mach_extensions[i].extension) > { > extension =3D mips_mach_extensions[i].base; > - if (extension =3D=3D base) > + if (mips_mach_extends_32_64 (base, extension)) > return true; > } > > -- > 2.30.2 >