From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id A316D3858D32 for ; Sun, 20 Aug 2023 13:53:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A316D3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bf55a81eeaso4030215ad.0 for ; Sun, 20 Aug 2023 06:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692539606; x=1693144406; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=P1bNoyDZ7QGbob/bCU4/aV6hmsMkjvXtU9p5ZBzc744=; b=HZVJ28K2my6eKZ6uAQ+NDV7Uwx7aawTdzd2JPNv1Z7nyJcZqBww/U6hiqbhkV4rL9m PHZUeU8RW+7/Y0dcm1dDhn13gzaBQ1IbutquSMItyP35Zw+Nj/Wnzid+GElb5RrSJs1Y euUWD7AmwP3zgidvCwuS2ZK5Z4VX81RLi+4fcTBgZP3P8rdCtHEBOJpCoVVN0ZEUmRqH AEK0w1pibxjuVYNKJRcyXf+15fSZyV38IE3Veqdoten5/E8Hi6cHPHiqy5YpxuLY1Vpv daO3QGoE2vwzh5Yr1FwotmITWbY2QVcQict3hkIonB8ZFqhXGMm1DFv9DK2drmA6dl+9 fmIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692539606; x=1693144406; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P1bNoyDZ7QGbob/bCU4/aV6hmsMkjvXtU9p5ZBzc744=; b=PXnZ33CzuPgqovS+froCfJe+Ffd8rCFHDM1IbLIkNMQgSVPNo0g6yyvbDfVY8umUnu 3+d6nwvUTdpgg88htF2l5pyS9q0niIiPUvaa/9fm+RXiBjuGYq8ui7sy0KEQZ3WXUaRX +7nDWaMeyS978H5dQkWnpP98HZnCVib37wi/MguoQcO9LIMawcbEyPolM3ta67gcYfkD PFaPnvOQ8+BokvTl4/K1e3xSW0GAticQ75EMKD1yx+e3UyFj2wE5+VAyuDOK9yYFRcot cFHcPw/5J6c3KqGOC2TEPqd2FsI05TjKxhCe2e33Y4cqcobwdSL9XeORmLFkXIRHqbnr K2pw== X-Gm-Message-State: AOJu0YxIWMAdO4+8y727SIN1jcX23hAEzyfSgMWrtNp2nahBk6z/Zerc IJ4RtCUWBSKBiaP9NXnIOTQTGUzRfbJXeo9yReV0RO3j78iC+Q== X-Google-Smtp-Source: AGHT+IHFhcntqSd8PRi87knMVBMiRHkgeT06CezO2jg3B5x2RVGHtBFiCHPVksnjaeF0WkWG/PfPAz6msp0/W2lgtJA= X-Received: by 2002:a17:902:e809:b0:1bb:de7f:a4d4 with SMTP id u9-20020a170902e80900b001bbde7fa4d4mr2864735plg.61.1692539606320; Sun, 20 Aug 2023 06:53:26 -0700 (PDT) MIME-Version: 1.0 References: <20230815104821.41855-1-yunqiang.su@cipunited.com> In-Reply-To: From: YunQiang Su Date: Sun, 20 Aug 2023 21:53:14 +0800 Message-ID: Subject: Re: [PATCH] MIPS: recoginze mipsisa64 as 64bit CPU To: "Maciej W. Rozycki" Cc: YunQiang Su , binutils@sourceware.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Maciej W. Rozycki =E4=BA=8E2023=E5=B9=B48=E6=9C=8817=E6= =97=A5=E5=91=A8=E5=9B=9B 20:37=E5=86=99=E9=81=93=EF=BC=9A > > On Tue, 15 Aug 2023, YunQiang Su wrote: > > > In GCC, mipsisa64* in triples are recoginzed as 64bit CPU. > > Let's do the same. > > > > The default ABI is determined by the abi section of triples, > > which is same with the `mips64*' CPU: > > -gnuabi64 and -openbsd for N64 > > otherwise, N32. > > The change description has to be explicit in that we only refer to Linux > configurations here, as it doesn't change the semantics of `mipsisa64*' > CPUs for other OSes. And it's not that we don't consider the CPU 64-bit > for `mipsisa64*-*-linux*' configurations. We just don't use a 64-bit ABI > by default. Finally there's no need to repeat the rules for ABI selectio= n > as we just follow the existing ones for `mips64*-*-linux*' configurations= . > > How about: > > MIPS: Use a 64-bit ABI by default for `mipsisa64*-*-linux*' targets > I use ABIs here, since they are both N32 and/or N64. > Following the arrangement in GCC select a 64-bit ABI by default, either > n32 or n64, rather than o32 for `mipsisa64*-*-linux*' targets, just as > with the corresponding `mips64*-*-linux*' targets. > > then? > > NB please remember to capitalise the sentence in change headings, whethe= r > it's there on its own or prefixed with a subsystem name such as "MIPS:". > And use a hyphen in combined number-word adjectives such as "64-bit". > > > diff --git a/gas/configure.ac b/gas/configure.ac > > index c3bd1178d41..617a5ca1473 100644 > > --- a/gas/configure.ac > > +++ b/gas/configure.ac > > @@ -394,10 +394,10 @@ changequote([,])dnl > > esac > > # Decide which ABI to target by default. > > case ${target} in > > - mips64*-openbsd* | mips64*-linux-gnuabi64) > > + mips64*-openbsd* | mips64*-linux-gnuabi64 | mipsisa64*-linux-gn= uabi64) > > mips_default_abi=3DN64_ABI > > ;; > > - mips64*-linux* | mips-sgi-irix6* | mips64*-freebsd* \ > > + mips64*-linux* | mipsisa64*-linux* | mips-sgi-irix6* | mips64*-= freebsd* \ > > These lines overrun 79 columns and need to be wrapped; there's a reason > for the existing wrapping. > > > diff --git a/gold/configure.tgt b/gold/configure.tgt > > index 4b54e08d27f..d09bb76ef02 100644 > > --- a/gold/configure.tgt > > +++ b/gold/configure.tgt > > @@ -153,13 +153,27 @@ aarch64*-*) > > targ_big_endian=3Dfalse > > targ_extra_big_endian=3Dtrue > > ;; > > -mips*el*-*-*|mips*le*-*-*) > > +mips64*el*-*-* | mipsisa64*le*-*-*) > > + targ_obj=3Dmips > > + targ_machine=3DEM_MIPS_RS3_LE > > + targ_size=3D64 > > + targ_big_endian=3Dfalse > > + targ_extra_big_endian=3Dtrue > > + ;; > > +mips*el*-*-*) > > You are removing the `mips*le*-*-*' configuration here. It may well be > the right move given that no other binutils component has it, but it has > to be a separate change. > You are right. I will add it back. > Also the use of EM_MIPS_RS3_LE has been deprecated since forever, so > please don't introduce a new case. I have no idea why the existing case > has been accepted into GOLD in the first place as BFD has never emitted i= t > and it was never intended to be used for newly-produced ELF files (the > extra MIPS ELF machine type allocation was essentially an accident in the > psABI design, it's not even named correctly). > Thank you. I will change it to EM_MIPS. > NB `mips*el*-*-*' isn't right either, it should be `mips*el-*-*' just as > elsewhere, because we'll otherwise take a CPU name with "el" in the middl= e > for the endianness. > Sure... Let's correct them. > > targ_obj=3Dmips > > targ_machine=3DEM_MIPS_RS3_LE > > targ_size=3D32 > > targ_big_endian=3Dfalse > > targ_extra_big_endian=3Dtrue > > ;; > > +mips64*-*-* | mipsisa64*-*-*) > > + targ_obj=3Dmips > > + targ_machine=3DEM_MIPS > > + targ_size=3D64 > > + targ_big_endian=3Dtrue > > + targ_extra_big_endian=3Dfalse > > + ;; > > Also you're adding new 64-bit MIPS support to GOLD here, so it has to be > a separate patch too from the changes to the other binutils components. > Is it a working configuration for GOLD even? Doesn't it need to have In fact, the current configure.tgt makes something wrong, if we configure it with --with-targets=3Dmips64-linux-gnuabi64. https://buildd.debian.org/status/fetch.php?pkg=3Dbinutils-mipsen&arch=3Damd= 64&ver=3D10%2Bc5&stamp=3D1692086940&raw=3D0 That's why I'd like to put them in a single patch. > `targ_extra_size' also set? > Maybe no. Since `configure.tgt` is used for --enable-targets=3Dxx,yy option. WIth this option, only the list extra targets should be support. If we set it, 32bit targets will be supported anyway. If user wants to support all targets, they need to use --with-targets=3Dall > Please resubmit with these issues addressed. > > Maciej --=20 YunQiang Su