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[209.85.214.170]) by smtp.gmail.com with ESMTPSA id js12-20020a17090b148c00b002960a58b04bsm2698147pjb.28.2024.02.06.20.37.19 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Feb 2024 20:37:19 -0800 (PST) Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1d93edfa76dso2178185ad.1 for ; Tue, 06 Feb 2024 20:37:19 -0800 (PST) X-Received: by 2002:a17:902:e5c4:b0:1d9:a5ec:30d2 with SMTP id u4-20020a170902e5c400b001d9a5ec30d2mr4461255plf.12.1707280639430; Tue, 06 Feb 2024 20:37:19 -0800 (PST) MIME-Version: 1.0 References: <20240206170538.2937169-1-syq@gcc.gnu.org> In-Reply-To: From: YunQiang Su Date: Wed, 7 Feb 2024 12:37:07 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4] MIPS/Gas: Disallow branch to absolute address for PIC To: "Maciej W. Rozycki" Cc: Nick Clifton , binutils@sourceware.org, xry111@xry111.site Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,BODY_8BITS,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Maciej W. Rozycki =E4=BA=8E2024=E5=B9=B42=E6=9C=887=E6= =97=A5=E5=91=A8=E4=B8=89 03:20=E5=86=99=E9=81=93=EF=BC=9A > > On Wed, 7 Feb 2024, YunQiang Su wrote: > > > The asm code like > > b (0) > > will generate binary like: > > > > 00000000 <.text>: > > 0: 1000ffff b 0x0 > > 0: R_MIPS_PC16 *ABS* > > 4: 00000000 nop > > If this object is linked into an PIC/PIC dynamic executable, > > this branch instruction will jump to a wrong address, with low > > 16bit unset. > > NAK, `mips_pic' may be set to SVR4_PIC and still produce de facto non-PI= C > code, as per the original SVR4 MIPS ABI (with lazy binding stubs rather > than PLT). We continue supporting this mode. > > Originally NO_PIC was intended for bare metal code only, statically > linked only, which was later extended to Linux, etc. with the addition of > PLT and copy reloc support. > > PR31343 has to be sorted in the linker. > So, what's the expected behavior? Let's use the example: .set noreorder .set nomicromips .set nomips16 b (4) INSN0 INSN1 INSN2 INSN3 At least we have 2 choice: 1. jump to INSN0, if we treat (4) same with (. + 4). 2. jump to INSN1, if we treat (4) as the offset in ISA document: "An 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target addre= ss." Currently, this syntax is not supported by ld even for static at all: xx: b (8) ssnop ssnop ssnop ssnop mipsel-linux-gnu-gcc -mno-shared -mno-abicalls -static -nostdlib 1.s warning: cannot find entry symbol __start; defaulting to 00400110 /tmp/ccdHuq6V.o: in function `xx': (.text+0x0): relocation truncated to fit: R_MIPS_PC16 against `*UND*' I don't think that we should generate such confusion binary at all. So, I prefer to disable this syntax for all cases, even for static objects: only branch to label is allowed.