[PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Faraz Shahbazker]

From: Matthew Fortune <matthew.fortune@mips.com>

gas/
	* config/tc-mips.c (mips_cpu_info_table): Add i6500.  Update
	default ASEs for i6400.
	* doc/c-mips.texi (-march): Document i6500.
	* testsuite/gas/mips/elf_mach_i6400.d: New test.
	* testsuite/gas/mips/elf_mach_i6500.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.
---
 gas/config/tc-mips.c                    |  4 +++-
 gas/doc/c-mips.texi                     |  1 +
 gas/testsuite/gas/mips/elf_mach_i6400.d | 23 +++++++++++++++++++++++
 gas/testsuite/gas/mips/elf_mach_i6500.d | 25 +++++++++++++++++++++++++
 gas/testsuite/gas/mips/mips.exp         |  2 ++
 5 files changed, 54 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/mips/elf_mach_i6400.d
 create mode 100644 gas/testsuite/gas/mips/elf_mach_i6500.d

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 45e8f38..7eab392 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -20018,7 +20018,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "xlp",	      0, 0,			ISA_MIPS64R2, CPU_XLR },
 
   /* MIPS 64 Release 6.  */
-  { "i6400",	      0, ASE_MSA,		ISA_MIPS64R6, CPU_MIPS64R6},
+  { "i6400",	      0, ASE_VIRT | ASE_MSA,	ISA_MIPS64R6, CPU_MIPS64R6},
+  { "i6500",	      0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV,
+						ISA_MIPS64R6, CPU_MIPS64R6},
   { "p6600",	      0, ASE_VIRT | ASE_MSA,	ISA_MIPS64R6, CPU_MIPS64R6},
 
   /* End marker.  */
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 1ef289a..1df28c6 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -449,6 +449,7 @@ p5600,
 sb1,
 sb1a,
 i6400,
+i6500,
 p6600,
 loongson2e,
 loongson2f,
diff --git a/gas/testsuite/gas/mips/elf_mach_i6400.d b/gas/testsuite/gas/mips/elf_mach_i6400.d
new file mode 100644
index 0000000..ca1619a
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf_mach_i6400.d
@@ -0,0 +1,23 @@
+#readelf: -Ah
+#name: ELF i6400 markings
+#as: -64 -march=i6400
+#source: empty.s
+
+ELF Header:
+#...
+  Flags: +0xa......., .*mips64r6.*
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r6
+GPR size: 64
+CPR1 size: 128
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: None
+ASEs:
+	VZ ASE
+	MSA ASE
+FLAGS 1: .*
+FLAGS 2: .*
diff --git a/gas/testsuite/gas/mips/elf_mach_i6500.d b/gas/testsuite/gas/mips/elf_mach_i6500.d
new file mode 100644
index 0000000..f1bb235
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf_mach_i6500.d
@@ -0,0 +1,25 @@
+#readelf: -Ah
+#name: ELF i6500 markings
+#as: -64 -march=i6500
+#source: empty.s
+
+ELF Header:
+#...
+  Flags: +0xa......., .*mips64r6.*
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r6
+GPR size: 64
+CPR1 size: 128
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: None
+ASEs:
+	VZ ASE
+	MSA ASE
+	CRC ASE
+	GINV ASE
+FLAGS 1: .*
+FLAGS 2: .*
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 5969c59..635c7dc 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1152,6 +1152,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "elf_mach_5900"
     run_dump_test "elf_mach_interaptiv-mr2"
     run_dump_test "elf_mach_p6600"
+    run_dump_test "elf_mach_i6400"
+    run_dump_test "elf_mach_i6500"
 
     run_dump_test "mips-gp32-fp32-pic"
     run_dump_test "mips-gp32-fp64-pic"
-- 
2.9.5

[PATCH 1/2] [MIPS] Apply ASE information for the selected processor

[Faraz Shahbazker]

From: Matthew Fortune <matthew.fortune@mips.com>

GAS does not enable implicit ASEs for most MIPS processors.
The rework of option handling done as part of .module implementation
left the implicit ASE logic broken and default enabled ASEs for
most processors did not get applied.  This patch ensures the ASE
information is carried forward to the point where it is required.

gas/
	* config/tc-mips.c (mips_set_options) <init_ase>: New field.
	(file_mips_opts, mips_opts) <init_ase>: Initialize new field.
	(file_mips_check_options): Track and propagate the initial ASE
	settings for a CPU.
	* testsuite/gas/mips/elf_mach_p6600.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new test.
---
 gas/config/tc-mips.c                    | 22 +++++++++++++++-------
 gas/testsuite/gas/mips/elf_mach_p6600.d | 23 +++++++++++++++++++++++
 gas/testsuite/gas/mips/mips.exp         |  1 +
 3 files changed, 39 insertions(+), 7 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/elf_mach_p6600.d

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 81b729a..45e8f38 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -268,6 +268,12 @@ struct mips_set_options
   /* 1 if single-precision operations on odd-numbered registers are
      allowed.  */
   int oddspreg;
+
+  /* The set of ASEs that should be enabled for the user specified
+     architecture.  This cannot be inferred from 'arch' for all cores
+     as processors only have a unique 'arch' if they add architecture
+     specific instructions (UDI).  */
+  int init_ase;
 };
 
 /* Specifies whether module level options have been checked yet.  */
@@ -289,7 +295,8 @@ static struct mips_set_options file_mips_opts =
   /* noreorder */ 0,  /* at */ ATREG, /* warn_about_macros */ 0,
   /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
   /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
-  /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
+  /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1,
+  /* init_ase */ 0
 };
 
 /* This is similar to file_mips_opts, but for the current set of options.  */
@@ -300,7 +307,8 @@ static struct mips_set_options mips_opts =
   /* noreorder */ 0,  /* at */ ATREG, /* warn_about_macros */ 0,
   /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE,
   /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE,
-  /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1
+  /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1,
+  /* init_ase */ 0
 };
 
 /* Which bits of file_ase were explicitly set or cleared by ASE options.  */
@@ -4086,8 +4094,6 @@ mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks)
 static void
 file_mips_check_options (void)
 {
-  const struct mips_cpu_info *arch_info = 0;
-
   if (file_mips_opts_checked)
     return;
 
@@ -4130,8 +4136,6 @@ file_mips_check_options (void)
 	file_mips_opts.fp = 32;
     }
 
-  arch_info = mips_cpu_info_from_arch (file_mips_opts.arch);
-
   /* Disable operations on odd-numbered floating-point registers by default
      when using the FPXX ABI.  */
   if (file_mips_opts.oddspreg < 0)
@@ -4175,7 +4179,7 @@ file_mips_check_options (void)
 
   /* If the user didn't explicitly select or deselect a particular ASE,
      use the default setting for the CPU.  */
-  file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit);
+  file_mips_opts.ase |= (file_mips_opts.init_ase & ~file_ase_explicit);
 
   /* Set up the current options.  These may change throughout assembly.  */
   mips_opts = file_mips_opts;
@@ -15189,6 +15193,7 @@ mips_after_parse_args (void)
 
   file_mips_opts.arch = arch_info->cpu;
   file_mips_opts.isa = arch_info->isa;
+  file_mips_opts.init_ase = arch_info->ase;
 
   /* Set up initial mips_opts state.  */
   mips_opts = file_mips_opts;
@@ -16559,6 +16564,7 @@ parse_code_option (char * name)
 	      mips_opts.arch = p->cpu;
 	      mips_opts.isa = p->isa;
 	      isa_set = TRUE;
+	      mips_opts.init_ase = p->ase;
 	    }
 	}
       else if (strncmp (name, "mips", 4) == 0)
@@ -16573,6 +16579,7 @@ parse_code_option (char * name)
 	      mips_opts.arch = p->cpu;
 	      mips_opts.isa = p->isa;
 	      isa_set = TRUE;
+	      mips_opts.init_ase = p->ase;
 	    }
 	}
       else
@@ -16646,6 +16653,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     {
       mips_opts.isa = file_mips_opts.isa;
       mips_opts.arch = file_mips_opts.arch;
+      mips_opts.init_ase = file_mips_opts.init_ase;
       mips_opts.gp = file_mips_opts.gp;
       mips_opts.fp = file_mips_opts.fp;
     }
diff --git a/gas/testsuite/gas/mips/elf_mach_p6600.d b/gas/testsuite/gas/mips/elf_mach_p6600.d
new file mode 100644
index 0000000..a977d3b
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf_mach_p6600.d
@@ -0,0 +1,23 @@
+#readelf: -Ah
+#name: ELF p6600 markings
+#as: -64 -march=p6600
+#source: empty.s
+
+ELF Header:
+#...
+  Flags: +0xa......., .*mips64r6.*
+#...
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r6
+GPR size: 64
+CPR1 size: 128
+CPR2 size: 0
+FP ABI: .*
+ISA Extension: None
+ASEs:
+	VZ ASE
+	MSA ASE
+FLAGS 1: .*
+FLAGS 2: .*
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index a009c6e..5969c59 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1151,6 +1151,7 @@ if { [istarget mips*-*-vxworks*] } {
     # Verify that machine markings are handled properly.
     run_dump_test "elf_mach_5900"
     run_dump_test "elf_mach_interaptiv-mr2"
+    run_dump_test "elf_mach_p6600"
 
     run_dump_test "mips-gp32-fp32-pic"
     run_dump_test "mips-gp32-fp64-pic"
-- 
2.9.5

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Paul Hua]

Hi,
The follow test failure.
FAIL: ELF p6600 markings
FAIL: ELF i6400 markings
FAIL: ELF i6500 markings

On Wed, Apr 10, 2019 at 4:40 AM Faraz Shahbazker
<fshahbazker@wavecomp.com> wrote:
>
> From: Matthew Fortune <matthew.fortune@mips.com>
>
> gas/
>         * config/tc-mips.c (mips_cpu_info_table): Add i6500.  Update
>         default ASEs for i6400.
>         * doc/c-mips.texi (-march): Document i6500.
>         * testsuite/gas/mips/elf_mach_i6400.d: New test.
>         * testsuite/gas/mips/elf_mach_i6500.d: New test.
>         * testsuite/gas/mips/mips.exp: Run the new tests.
> ---
>  gas/config/tc-mips.c                    |  4 +++-
>  gas/doc/c-mips.texi                     |  1 +
>  gas/testsuite/gas/mips/elf_mach_i6400.d | 23 +++++++++++++++++++++++
>  gas/testsuite/gas/mips/elf_mach_i6500.d | 25 +++++++++++++++++++++++++
>  gas/testsuite/gas/mips/mips.exp         |  2 ++
>  5 files changed, 54 insertions(+), 1 deletion(-)
>  create mode 100644 gas/testsuite/gas/mips/elf_mach_i6400.d
>  create mode 100644 gas/testsuite/gas/mips/elf_mach_i6500.d
>
> diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
> index 45e8f38..7eab392 100644
> --- a/gas/config/tc-mips.c
> +++ b/gas/config/tc-mips.c
> @@ -20018,7 +20018,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
>    { "xlp",           0, 0,                     ISA_MIPS64R2, CPU_XLR },
>
>    /* MIPS 64 Release 6.  */
> -  { "i6400",         0, ASE_MSA,               ISA_MIPS64R6, CPU_MIPS64R6},
> +  { "i6400",         0, ASE_VIRT | ASE_MSA,    ISA_MIPS64R6, CPU_MIPS64R6},
> +  { "i6500",         0, ASE_VIRT | ASE_MSA | ASE_CRC | ASE_GINV,
> +                                               ISA_MIPS64R6, CPU_MIPS64R6},
>    { "p6600",         0, ASE_VIRT | ASE_MSA,    ISA_MIPS64R6, CPU_MIPS64R6},
>
>    /* End marker.  */
> diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
> index 1ef289a..1df28c6 100644
> --- a/gas/doc/c-mips.texi
> +++ b/gas/doc/c-mips.texi
> @@ -449,6 +449,7 @@ p5600,
>  sb1,
>  sb1a,
>  i6400,
> +i6500,
>  p6600,
>  loongson2e,
>  loongson2f,
> diff --git a/gas/testsuite/gas/mips/elf_mach_i6400.d b/gas/testsuite/gas/mips/elf_mach_i6400.d
> new file mode 100644
> index 0000000..ca1619a
> --- /dev/null
> +++ b/gas/testsuite/gas/mips/elf_mach_i6400.d
> @@ -0,0 +1,23 @@
> +#readelf: -Ah
> +#name: ELF i6400 markings
> +#as: -64 -march=i6400
> +#source: empty.s
> +
> +ELF Header:
> +#...
> +  Flags: +0xa......., .*mips64r6.*
> +#...
> +
> +MIPS ABI Flags Version: 0
> +
> +ISA: MIPS64r6
> +GPR size: 64
> +CPR1 size: 128
> +CPR2 size: 0
> +FP ABI: .*
> +ISA Extension: None
> +ASEs:
> +       VZ ASE
> +       MSA ASE
> +FLAGS 1: .*
> +FLAGS 2: .*
> diff --git a/gas/testsuite/gas/mips/elf_mach_i6500.d b/gas/testsuite/gas/mips/elf_mach_i6500.d
> new file mode 100644
> index 0000000..f1bb235
> --- /dev/null
> +++ b/gas/testsuite/gas/mips/elf_mach_i6500.d
> @@ -0,0 +1,25 @@
> +#readelf: -Ah
> +#name: ELF i6500 markings
> +#as: -64 -march=i6500
> +#source: empty.s
> +
> +ELF Header:
> +#...
> +  Flags: +0xa......., .*mips64r6.*
> +#...
> +
> +MIPS ABI Flags Version: 0
> +
> +ISA: MIPS64r6
> +GPR size: 64
> +CPR1 size: 128
> +CPR2 size: 0
> +FP ABI: .*
> +ISA Extension: None
> +ASEs:
> +       VZ ASE
> +       MSA ASE
> +       CRC ASE
> +       GINV ASE
> +FLAGS 1: .*
> +FLAGS 2: .*
> diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
> index 5969c59..635c7dc 100644
> --- a/gas/testsuite/gas/mips/mips.exp
> +++ b/gas/testsuite/gas/mips/mips.exp
> @@ -1152,6 +1152,8 @@ if { [istarget mips*-*-vxworks*] } {
>      run_dump_test "elf_mach_5900"
>      run_dump_test "elf_mach_interaptiv-mr2"
>      run_dump_test "elf_mach_p6600"
> +    run_dump_test "elf_mach_i6400"
> +    run_dump_test "elf_mach_i6500"
>
>      run_dump_test "mips-gp32-fp32-pic"
>      run_dump_test "mips-gp32-fp64-pic"
> --
> 2.9.5
>

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Faraz Shahbazker]

Hi Paul,

On 4/10/19 7:44 PM, Paul Hua wrote:
> The follow test failure.
> FAIL: ELF p6600 markings
> FAIL: ELF i6400 markings
> FAIL: ELF i6500 markings
Did you perhaps miss [PATCH 1/2] [MIPS] Apply ASE information for the selected processor?

ASE information has been broken for processors which do not also correspond to unique `arch' designations. The testsuite does not include coverage for any such processor, so it was never detected. The first patch fixes this and the second adds new tests which rely upon it.

Regards,
Faraz

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Paul Hua]

Hi, Faraz,

> > FAIL: ELF i6500 markings
> Did you perhaps miss [PATCH 1/2] [MIPS] Apply ASE information for the selected processor?
I apply both patches, but refused, I changed by hand, maybe I miss
something, please let your patch base new repo and resend it.
>
> ASE information has been broken for processors which do not also correspond to unique `arch' designations. The testsuite does not include coverage for any such processor, so it was never detected. The first patch fixes this and the second adds new tests which rely upon it.
>
> Regards,
> Faraz

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Faraz Shahbazker]

Hi Paul

On 04/11/2019 06:14 PM, Paul Hua wrote:
>>> FAIL: ELF i6500 markings
>> Did you perhaps miss [PATCH 1/2] [MIPS] Apply ASE information for the selected processor?
> I apply both patches, but refused, I changed by hand, maybe I miss
> something, please let your patch base new repo and resend it.

I rebased and regenerated both the patches but the output of 
format-patch was identical to what I had posted earlier, except for the 
time-stamp. I don't see the point in re-posting them unless we can 
figure out the problem.

Could this be a charset/encoding issue? It seems 
us-ascii/quoted-printable is the closest thing to plain-text that my 
mail server allows me to transmit.

Regards,
Faraz

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Paul Hua]

Hi:
Which commit is your patch based on?

I based on 35add35e85c21f02e3e5808273cb77b24069b0aa, output is :
$ patch -p1 < patch/11.patch
patching file gas/config/tc-mips.c
Hunk #5 succeeded at 4136 with fuzz 1.
Hunk #8 FAILED at 16564.
Hunk #9 FAILED at 16578.
2 out of 10 hunks FAILED -- saving rejects to file
gas/config/tc-mips.c.rej
patching file gas/testsuite/gas/mips/elf_mach_p6600.d
patching file gas/testsuite/gas/mips/mips.exp

$ cat gas/config/tc-mips.c.rej
--- gas/config/tc-mips.c
+++ gas/config/tc-mips.c
@@ -16564,6 +16569,7 @@ parse_code_option (char * name)
              mips_opts.arch = p->cpu;
              mips_opts.isa = p->isa;
              isa_set = TRUE;
+             mips_opts.init_ase = p->ase;
            }
        }
       else if (strncmp (name, "mips", 4) == 0)
@@ -16578,6 +16584,7 @@ parse_code_option (char * name)
              mips_opts.arch = p->cpu;
              mips_opts.isa = p->isa;
              isa_set = TRUE;
+             mips_opts.init_ase = p->ase;
            }
        }
       else

Can you try the same commit ?
ps: My configure option is : ../configure --prefix=/opt/binutils
--target=mips64el-linux-gnu, then make ; make check.

On Fri, Apr 12, 2019 at 10:09 AM Faraz Shahbazker
<fshahbazker@wavecomp.com> wrote:
>
> Hi Paul
>
> On 04/11/2019 06:14 PM, Paul Hua wrote:
> >>> FAIL: ELF i6500 markings
> >> Did you perhaps miss [PATCH 1/2] [MIPS] Apply ASE information for the selected processor?
> > I apply both patches, but refused, I changed by hand, maybe I miss
> > something, please let your patch base new repo and resend it.
>
> I rebased and regenerated both the patches but the output of
> format-patch was identical to what I had posted earlier, except for the
> time-stamp. I don't see the point in re-posting them unless we can
> figure out the problem.
>
> Could this be a charset/encoding issue? It seems
> us-ascii/quoted-printable is the closest thing to plain-text that my
> mail server allows me to transmit.
>
> Regards,
> Faraz

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Faraz Shahbazker]

Hi Paul,

On 04/12/2019 07:06 PM, Paul Hua wrote:
> Hi:
> Which commit is your patch based on?
> 
> I based on 35add35e85c21f02e3e5808273cb77b24069b0aa, output is :
> 
> Can you try the same commit ?
> ps: My configure option is : ../configure --prefix=/opt/binutils
> --target=mips64el-linux-gnu, then make ; make check.

I tried with the same commit as well as HEAD. I tried the file generated 
using 'Save as' in thunderbird and the patch from the mailing list 
digest dated 9th April and with 'raw text' downloaded from the mailing 
list archives. All 3 applied cleanly and gave identical test results. 
The only difference is that I used 'git am' to apply the patches.

Regards,
Faraz

Re: [PATCH 1/2] [MIPS] Apply ASE information for the selected processor

[Paul Hua]

Hi, Faraz,

Just small comments.

>    /* Set up the current options.  These may change throughout assembly.  */
>    mips_opts = file_mips_opts;
> @@ -15189,6 +15193,7 @@ mips_after_parse_args (void)
>
>    file_mips_opts.arch = arch_info->cpu;
>    file_mips_opts.isa = arch_info->isa;
> +  file_mips_opts.init_ase = arch_info->ase;
>
>    /* Set up initial mips_opts state.  */
>    mips_opts = file_mips_opts;
> @@ -16559,6 +16564,7 @@ parse_code_option (char * name)
>               mips_opts.arch = p->cpu;
>               mips_opts.isa = p->isa;
>               isa_set = TRUE;
> +             mips_opts.init_ase = p->ase;
>             }
>         }

Mentions this in changelog.

>        else if (strncmp (name, "mips", 4) == 0)
> @@ -16573,6 +16579,7 @@ parse_code_option (char * name)
>               mips_opts.arch = p->cpu;
>               mips_opts.isa = p->isa;
>               isa_set = TRUE;
> +             mips_opts.init_ase = p->ase;
>             }
>         }
>        else

same as above.

> @@ -16646,6 +16653,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
>      {
>        mips_opts.isa = file_mips_opts.isa;
>        mips_opts.arch = file_mips_opts.arch;
> +      mips_opts.init_ase = file_mips_opts.init_ase;
>        mips_opts.gp = file_mips_opts.gp;
>        mips_opts.fp = file_mips_opts.fp;
>      }

Same.

After added those in changelog, apply to reop.

Re: [PATCH 2/2] [MIPS] Add i6500 CPU and fix i6400 default ASEs

[Paul Hua]

Hi,

Finally, I applied the patch.

ok for committed.

On Sat, Apr 13, 2019 at 12:55 PM Faraz Shahbazker
<fshahbazker@wavecomp.com> wrote:
>
> Hi Paul,
>
> On 04/12/2019 07:06 PM, Paul Hua wrote:
> > Hi:
> > Which commit is your patch based on?
> >
> > I based on 35add35e85c21f02e3e5808273cb77b24069b0aa, output is :
> >
> > Can you try the same commit ?
> > ps: My configure option is : ../configure --prefix=/opt/binutils
> > --target=mips64el-linux-gnu, then make ; make check.
>
> I tried with the same commit as well as HEAD. I tried the file generated
> using 'Save as' in thunderbird and the patch from the mailing list
> digest dated 9th April and with 'raw text' downloaded from the mailing
> list archives. All 3 applied cleanly and gave identical test results.
> The only difference is that I used 'git am' to apply the patches.
>
> Regards,
> Faraz